STLR4200S [ETC]
USB/lrDA Bridge Controller; USB / lrDA桥控制器
| 型号： | STLR4200S |
| 厂家： | 
ETC |
| 描述： | USB/lrDA Bridge Controller |
| 文件： | 总21页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated Mixed-Signal Solutions
STIr4200
USB/IrDA Bridge Controller
Version 2.0 April ‘03
OFFICIAL PRODUCT DOCUMENTATION
3-4200-D1-2.0-0403
Copyright © 2003 SigmaTel, Inc. All rights reserved.
All contents of this document are protected by copyright law and may not be reproduced without the express written consent of SigmaTel, Inc.
SigmaTel, the SigmaTel logo, and combinations thereof are registered trademarks of SigmaTel, Inc. Other product names used in this pub-
lication are for identification purposes only and may be trademarks or registered trademarks of their respective companies. The contents of
this document are provided in connection with SigmaTel, Inc. products. SigmaTel, Inc. has made best efforts to ensure that the information
contained herein is accurate and reliable. However, SigmaTel, Inc. makes no warranties, express or implied, as to the accuracy or com-
pleteness of the contents of this publication and is providing this publication "AS IS". SigmaTel, Inc. reserves the right to make changes to
specifications and product descriptions at any time without notice, and to discontinue or make changes to its products at any time without
notice. SigmaTel, Inc. does not assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation special, consequential, or incidential damages.
O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
1. TABLE OF CONTENTS
1. TABLE OF CONTENTS .............................................................................................. 2
1.1. List of Figures ....................................................................................................................3
1.2. List of Tables .....................................................................................................................3
2. PRODUCT OVERVIEW ............................................................................................... 4
2.1. Features ............................................................................................................................4
2.2. Description ........................................................................................................................4
2.3. Ordering Information .........................................................................................................4
2.4. STIr4200 Block Diagram ..................................................................................................5
3. CHARACTERISTICS AND SPECIFICATIONS ........................................................... 5
3.1. Absolute Maximum Ratings ..............................................................................................5
3.2. Recommended Operating Conditions ...............................................................................5
3.3. Electrical Characteristics ...................................................................................................6
4. FUNCTIONAL DESCRIPTION .................................................................................... 6
4.1. Overview ...........................................................................................................................6
4.2. USB Interface ....................................................................................................................7
4.3. Vendor-Specific Device Requests .....................................................................................7
4.3.1. Write Multiple Registers .......................................................................................7
4.3.2. Write One Register ...............................................................................................7
4.3.3. Read Multiple Registers .......................................................................................8
4.3.4. Read ROM ...........................................................................................................8
4.3.5. Vendor Clear Stall ................................................................................................8
4.4. Digital IR Transceiver ........................................................................................................9
4.5. FIFO Contents ...................................................................................................................9
5. IR FRAMING FORMATS ........................................................................................... 10
5.1. Transmit Frame Format ..................................................................................................10
5.1.1. SIR Transmit Frame ...........................................................................................10
5.1.2. FIR Transmit Frame ...........................................................................................11
5.1.3. Receive Frame Format .......................................................................................12
5.1.3.1. SIR Receive Frame ............................................................................12
5.1.3.2. FIR Receive Frame ............................................................................13
6. DIGITAL IR TRANSCEIVER REGISTERS ................................................................ 14
6.1. Detailed STIr4200 Register Descriptions .......................................................................14
6.1.1. FIFO Data Register ............................................................................................14
6.1.2. Mode and Baud Rate Registers .........................................................................15
6.1.2.1. Mode Register ....................................................................................15
6.1.2.2. Baud Rate Register ............................................................................15
6.1.3. Control Register .................................................................................................16
6.1.4. Sensitivity Register .............................................................................................17
6.1.5. Status Register ...................................................................................................17
6.1.6. FIFO Count Registers (LSB,MSB) .....................................................................18
6.1.6.1. FIFO Count LSB .................................................................................18
6.1.6.2. FIFO Count MSB ................................................................................18
6.1.7. DPLL Tune Register ...........................................................................................18
6.1.8. IRDIG Setup Register .........................................................................................19
6.1.9. Test Register ......................................................................................................19
7. PIN DESCRIPTION .................................................................................................... 20
7.1. STIr4200S 28-Pin SSOP Pin Description .......................................................................20
8. PACKAGE DRAWINGS ............................................................................................ 21
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O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
1.1. List of Figures
Figure 1. STIr4200 Block Diagram .................................................................................................5
Figure 2. Typical USB-IR Application .............................................................................................6
Figure 3. Block Diagram of Digital IR Transceiver ..........................................................................9
Figure 4. SIR Transmit Frame Format ..........................................................................................10
Figure 5. FIR Transmit Frame Format ..........................................................................................11
Figure 6. SIR Receive Frame Format ...........................................................................................12
Figure 7. FIR Receive Frame Format ...........................................................................................13
Figure 8. STIr4200S 28-Pin SSOP Pin Assignment Drawing .......................................................20
Figure 9. 28-Pin SSOP Package Drawing ....................................................................................21
1.2. List of Tables
Table 1. Absolute Maximum Ratings ..............................................................................................5
Table 2. Recommended Operating Conditions ..............................................................................5
Table 3. Electrical Characteristics ..................................................................................................6
Table 4. Write Multiple Registers ....................................................................................................7
Table 5. Write One Register ...........................................................................................................7
Table 6. Read Multiple Registers ...................................................................................................8
Table 7. Read ROM ........................................................................................................................8
Table 8. Vendor Clear Stall ............................................................................................................8
Table 9. IrLAP Frame .....................................................................................................................9
Table 10. Ir Transceiver Registers ...............................................................................................14
Table 11. FIFO Data Register ......................................................................................................14
Table 12. Mode Register ..............................................................................................................15
Table 13. Baud Rate Register ......................................................................................................15
Table 14. Mode and Buad Rate Values for Required IrDA Modes of Operation ..........................15
Table 15. Control Register ............................................................................................................16
Table 16. Sensitivity Register .......................................................................................................17
Table 17. Status Register .............................................................................................................17
Table 18. FIFO Count LSB ...........................................................................................................18
Table 19. FIFO Count MSB ..........................................................................................................18
Table 20. DPLL Tune Register .....................................................................................................18
Table 21. IRDIG Setup Register ...................................................................................................19
Table 22. Test Register ................................................................................................................19
Table 23. Pin Descriptions for STIr4200S 28-Pin SSOP Package ...............................................20
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O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
2. PRODUCT OVERVIEW
2.1. Features
•
•
•
•
•
Low-power CMOS design
IrDA data rates from 2.4 Kbps to 4 Mbps
Obtains power from USB port
Uses standard IrDA transceivers
Optional LED driver for additional flexibility
–
LED driver capable of > 650 ma @ 5V, 25% duty cycle
•
•
•
•
•
Full compliance to IrDA 1.3 and USB 1.1 specifications
4 Kbyte FIFO buffer memory
Requires a single 12 Mhz crystal
Windows 98/98SE/ME/2000/XP™ NDIS/USB driver
Low-profile 28-Pin SSOP package
2.2. Description
The SigmaTel STIr4200 is a low cost, low power, USB/IrDA Bridge Controller inte-
grated circuit for enabling IrDA wireless data communications through a standard
PC USB port. The STIr4200 directly interfaces to both single path and dual path
receive IrDA transceiver module architectures and contains a USB controller, IrDA
controller, interface logic, and memory buffer for full IrDA 1.3, 4 Mbps data transfer
rates. A block diagram is hown in Figure 1.
The STIr4200 is bundled with a Windows 98/98SE/ME/2000/XP™ NDIS/USB driver
for enabling the implementation of a cost effective USB/IrDA Adapter solution for
wireless data communications.
Infrared
Communication
Transmission
Infrared
Transceiver
SigmaTel USB/
IrDA Bridge
Controller
Data
Transfer
USB
Connection
to the PC
2.3. Ordering Information
Part Number
Package
Temp Range
0° C to +70° C
Supply Range
Vdd = 3.1 - 3.6V
STIr4200S
28-Pin SSOP
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O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
2.4. STIr4200 Block Diagram
Optional LED Driver
TX DIODE
USB - IRDA Bridge IC
IrDA
Transceiver
Interface
IrDA Controller
USB Port
USB Controller
Bulk In
UOUT
SD/MODE (TEMIC
ONLY)
+V
4K FIFO
Buffer
TXDATA
TXD
D
D
POS
NEG
Bulk Out
Control
RXFAST
IR Register
Set
RXD/R XFAST
RXSLOW
RXSLOW (DUAL
RECEIVE PATH)
Gnd
12 Mhz
Figure 1. STIr4200 Block Diagram
3. CHARACTERISTICS AND SPECIFICATIONS
3.1. Absolute Maximum Ratings
Symbol
Parameter
MIN
MAX
UNITS
CONDITIONS
PD
TA
Power Dissipation (Package constraint)
Operating Temperature
mW
0
70
260
°C
TJ
TS
Lead Solder Temperature
Storage Temperature
Supply Voltage
°C
°C
V
for 10 sec max.
-55
125
VCC
Vmax
ESD
-0.3 V
6
Voltage at any pin
V
DD + 0.4V
V
Electrostatic Discharge (ESD)
+/- 2KV
V
See Note 1
Note: 1. The device meets the JESD22-A114-A Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model
(HBM) requirements of +/- 2KV on all pins, except the TXDIODE pin (Pin 2), where the limit is +/1.5KV.
Table 1. Absolute Maximum Ratings
3.2. Recommended Operating Conditions
Symbol
VDD
Parameter
Supply Voltage
Operating Temperature Range
MIN
3.1
0
TYP
3.3
25
MAX
3.6
UNITS
V
CONDITION
TA
70
°C
Table 2. Recommended Operating Conditions
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O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
3.3. Electrical Characteristics
TA = 25°CA VDD = 3.3V unless otherwise specified. Cap Load = 50pF
Symbol
ICC
Parameter
Active Supply Current
MIN
TYP
12
MAX
19
UNITS
CONDITION
mA
µA
V
ICC
Suspend Supply Current
Receive Data Logic High
Receive Data Logic Low
Transmit Data Logic High
Transmit Data Logic Low
14
50
VRXDH
VRXDL
VTXDH
VTXDL
VDD x 0.8
VDD x 0.6
0.8
V
V
VDD x 0.4
V
Table 3. Electrical Characteristics
4. FUNCTIONAL DESCRIPTION
4.1. Overview
The STIr4200 consists of two major functional blocks, the USB controller and the
digital IR transceiver. The USB controller provides a Control, Bulk-In, and Bulk- Out
endpoints to the USB host. The digital IR transceiver consists of a transmit and
receive interface that connects to an analog IR front end. Figure 1shows a block dia-
gram of the device.
This USB/IrDA Bridge Controller has full interface capability to connect between a
USB bus , and an IrDA-compatible infrared transceiver device. A simplified sche-
matic of this arrangement is shown in Figure 2.
Voltage
Regulator
USB
Vcc
V+
STIr4200S
D-
GND
RXD
TXD
SD
USB-IrDA
Bridge
Controller
D+
GND
Figure 2. Typical USB-IR Application
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O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
4.2. USB Interface
The USB interface to the host controller includes a Control endpoint, a Bulk-In end-
point, and a Bulk-Out endpoint. The USB controller supports the USB 1.1 specifica-
tion. Hence, it supports all standard functionality associated with device
enumeration, standard USB device requests, etc. In addition, there is a set of ven-
dor specific commands provided to allow a USB driver to access registers in the
Digital IR Transceiver and ROM in the USB controller.
Note: The STIr4200 device conforms to all of the USB 1.1 specifications with one
exception of the "get_interface" command. This command is used only during USB
conformance testing, and during that testing, improper operation will be noted on
test results. However, the software drivers provided by SigmaTel, Inc. do NOT use
that command at all, and this does NOT cause any problem of any kind in operation.
A waiver for this command has been obtained from USBIF by SigmaTel, Inc. This
command is not used by the software, and therefore has no effect on device and
system operation. The only time this "get_interface" command is even accessed is
during USB conformance testing.
4.3. Vendor-Specific Device Requests
4.3.1.
Write Multiple Registers
The write multiple registers vendor specific command allows the user to write multi-
ple sequential registers to the Digital IR Transceiver. Each register is one byte wide,
so the command indicates first register to write, the number of registers to write, and
the data phase supplies the data for those registers.
Offset
Field
Size
Value (hex)
0x40
Description
0
1
2
4
6
bmRequestType 1
Host to device, vendor type, device recipient
Write multiple registers
Brequest
Wvalue
1
2
2
2
0x00
Not used (0x0000)
0x0001–0x000f
0x0001–0x000f
Windex
First register to write
Wlength
Data phase
Number of registers to write
1-15 bytes of Register Data
Table 4. Write Multiple Registers
4.3.2.
Write One Register
The write one register vendor specific command allows the user to write a single
register to the Digital IR Transceiver.
Offset
Field
Size
Value (hex)
0x40
0x03
Description
0
1
2
4
6
bmRequestType 1
Host to device, vendor type, device recipient
Write one register
Brequest
Wvalue
Windex
Wlength
1
2
2
2
LSB contains data The data to write the register
0x0001 – 0x000f Register to write
Not used (0x0000)
Table 5. Write One Register
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O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
4.3.3.
Read Multiple Registers
The read multiple registers vendor specific command allows the user to read multi-
ple sequential registers from the Digital IR Transceiver. Each register is one byte
wide, so the command indicates the first register to read, the number of registers to
read, and the responding data phase supplies the data from those registers. This
command is also used for the case of reading only one register.
Offset
Field
Size
Value (hex)
0xc0
Description
0
1
2
4
6
bmRequestType 1
Device to host, vendor type, device recipient
Read multiple registers
BRequest
Wvalue
1
2
2
2
0x01
Not used (0x0000)
Windex
0x0001 – 0x000f First register to read
0x0001 – 0x000f Number of registers to read
Table 6. Read Multiple Registers
Wlength
4.3.4.
Read ROM
The read ROM vendor specific command allows the user to read the contents of the
USB controller endpoint zero ROM. This is primarily a debug feature that allows ver-
ification of the endpoint zero ROM contents. Only 64 bytes of ROM data can be
requested at a time. The responding data phase supplies the data from the endpoint
zero ROM.
Offset
Field
Size
Value (hex)
0xc0
Description
0
1
2
4
6
BmRequestType 1
Device to host, vendor type, device recipient
Read ROM
Brequest
Wvalue
Windex
Wlength
1
2
2
2
0x02
Not used (0x0000)
0x0000–0x00ff
0x01–0x0040
Base ROM address
Number of ROM locations to read (64 bytes
max per request)
Table 7. Read ROM
4.3.5.
Vendor Clear Stall
The vendor clear stall command is included as a potential work around for limita-
tions in early versions of the Microsoft™ USB driver stack. Although not a concern
with the latest operating systems, the earlier versions could have the possibility that
the USB driver stack would not properly clear endpoint stalls. The standard device
clear stall request is also supported.
Offset
Field
Size
Value (hex)
0x42
Description
0
BmRequestType 1
Device to host, vendor type, endpoint
recipient
1
2
4
6
Brequest
Wvalue
Windex
Wlength
1
2
2
2
0x01
Clear endpoint stall
Not used (0x0000)
0x0000 – 0x0002 Endpoint on which to clear stall
Not used (0x0000)
Table 8. Vendor Clear Stall
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O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
4.4. Digital IR Transceiver
The Digital IR Transceiver is responsible for driving the transmit diode and receiving
the digital input from an analog IR front end. The primary components are the trans-
mit modulator, the receive demodulator, the FIFO, the analog transmit section, and
the register array. Figure 3 shows a block diagram of the Digital IR Transceiver. By
programming the registers in the register array, the device’s operation is deter-
mined. Various registers are used to specify operations such as the modulation
scheme, the baud rate, the current frame size in the FIFO, the RX input selection,
etc. The FIFO is 4K bytes in size.
Analog TX
Section
TX Modulator
(ASK, IrDA FIR,MIR,SIR)
TXDIODE
FIFO
TXDATA
RXFAST
RXSLOW
RX Demodulator
(ASK, IrDA FIR,MIR,SIR)
Register Array
Figure 3. Block Diagram of Digital IR Transceiver
In steady state transmit operation, the USB controller is filling the FIFO with data
while the Digital IR Transceiver is emptying it via the transmit modulator. In steady
state receive operation, the USB controller is emptying the FIFO while the RX
demodulator is filling the FIFO.
4.5. FIFO Contents
Data sent to the USB controller for transmission by the TX modulator must be orga-
nized into frames. An IrLAP frame is made up of the following portions:
BOF
A
C
I
FCS
EOF
BOF
Beginning of frame(s)
Address field
A
C
Control field
I
Information field
FCS
EOF
Frame check sequence (CRC)
End of frame
Table 9. IrLAP Frame
The NDIS IR stack only provides the A, C, and I fields to the NDIS mini-port device
driver that communicates with the USB/IrDA transceiver. Hence, the mini-port must
fill in the BOF, FCS, and EOF fields. Additionally, the driver must add a 2-byte
header ID code and a 2-byte frame size to the packet before passing the packet
onto the USB stack for delivery to the USB/IrDA transceiver. There are additional
special characters and required escape sequences depending upon the rate of
transfer. Details on the frame format for each of the support rates is discussed in the
following sections.
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O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
5. IR FRAMING FORMATS
5.1. Transmit Frame Format
5.1.1.
SIR Transmit Frame
The SIR rates include 2.4, 9.6, 19.2, 38.4, 57.6, and 115.2 Kbps. For SIR, the frame
presented to the USB bulk transmit interface must be organized in the following
fashion as shown in Figure 4.
0x55
Header ID
0xAA
LSB size
Number of following bytes
MSB size
0xC0
0xC0
BOF = Beginning of frame characters
The number of beginning of frame
characters is determined during the
negotiation stage.
0xC0
0xC0
0xC0
…
Data
A
C
I
Data
Address/Control/Information Fields
Special characters must be escaped
Data
Data
Original Data
0xC0
0xC1
Escaped Data
0x7D 0xE0
0x7D 0xE1
0x7D 0x5D
Data
Data
0x7D
Data
…
LSB CRC
MSB CRC
0xC1
FCS : 16 bit CRC-CCITT
EOF - End of frame
Figure 4. SIR Transmit Frame Format
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STIr4200
USB/IrDA Bridge Controller
5.1.2.
FIR Transmit Frame
The FIR rate is 4 Mbps The frame organization is detailed in Figure 5.
0x55
Header ID
0xAA
LSB size
Number of following bytes
MSB size
0x7F
0x7F
0x7F
0x7F
PREAMBLE : These characters
cause the STIr4200S to generate the
preamble sequence used by the
0x7F
0x7F
receiving device for synchronization.
There must be exactly 16 characters.
0x7F
0x7F
0x7F
0x7F
0x7F
0x7F
0x7F
0x7F
0x7F
0x7F
0x7E
0x7E
Data
Data
Data
Data
Data
Data
Data
BOF = Beginning of frame
A
C
I
Address/Control/Information Fields
Special characters must be escaped
Original Data
0x7D
0x7E
Escaped Data
0x7D 0x5D
0x7D 0x5E
0x7D 0x5F
0x7F
LSB CRC
FCS : 32 bit CRC-IEEE802
EOF - End of frame
MSB CRC
0x7E
0x7E
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O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
5.1.3.
Receive Frame Format
Data received into the STIr4200 FIFO from the digital infrared interface can be
accessed by performing a bulk read on the USB interface. The received data con-
tains the encoded infrared data. The STIr4200 does not perform any frame valida-
tion or CRC-Checking. Multiple frames may exist within one bulk read depending
upon the size of the bulk read. However, the end of the bulk read buffer may not
necessarily coincide with the end of an infrared frame. It is highly likely that the data
at the end of a bulk read will be a partial frame. The remaining frame data will be
acquired in the next bulk read.
The bulk data thus contains start-of-frame (BOF) characters, end-of-frame (EOF)
characters, and escape characters that delineate the actual frame. It is the responsi-
bility of the host software to reconstruct the frame.
5.1.3.1.
SIR Receive Frame
The standard SIR encoding scheme provides all information needed to delineate
the encoded receive frames. Figure 6 summarizes the SIR receive frame format
encoding scheme.
0xC0
BOF = Beginning of frame characters
The number of beginning of frame
characters is determined during the
negotiation stage.
0xC0
0xC0
0xC0
0xC0
…
Data
A
C
I
Data
Address/Control/Information Fields
Special characters have been escaped. Software
must un-escape the data
Data
Data
Escaped Data
0x7D 0xE0
0x7D 0xE1
0x7D 0x5D
Original Data
0xC0
0xC1
Original Data
0xC0
0xC1
Data
Data
Data
0x7D
0x7D
…
LSB CRC
MSB CRC
0xC1
FCS : 16 bit CRC-CCITT
EOF - End of frame
Figure 6. SIR Receive Frame Format
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STIr4200
USB/IrDA Bridge Controller
5.1.3.2.
FIR Receive Frame
The FIR encoding scheme is modified slightly from the standard scheme. The char-
acter 0x7E is used to delineate the BOF and EOF. The STIr4200 escapes three
characters in the data field on receive, 0x7F, 0x7E and 0x7D, which allows the 0x7E
characters used as BOF and EOF to be unique. The 0x7E character can then be
used to delineate the infrared frame boundaries. This hardware escaping in the
data portion is specific to the STIr4200, and the software must un-escape the data
portion of the received frame to restore the original data. Figure 7 summarizes the
FIR receive frame format encoding scheme.
0x7E
BOF = Beginning of frame
0x7E
Data
Data
Data
Data
A
C
I
Data
Data
Data
Data
…
Address/Control/Information Fields
Special characters must be un-escaped
Escaped Data
0x7D 0x5D
0x7D 0x5E
0x7D 0x5F
Original Data
0x7D
0x7E
0x7F
LSB CRC
…
FCS : 32 bit CRC-IEEE802
EOF - End of frame
…
MSB CRC
0x7E
0x7E
Figure 7. FIR Receive Frame Format
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O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
6. DIGITAL IR TRANSCEIVER REGISTERS
Offset
Description
Access
Bit Position
7
6
5
4
3
2
1
0
0
1
2
3
4
FIFO Data
R/W
R/W
R/W
R/W
Reserved
Mode Register
FIR
Reserved
SIR
ASK FASTRXEN FFRSTEN FFSPRST PDCLK(8)
PDCLK(7: 0)
Baud Rate Register
Control Register
Sensitivity Register
SDMODE RXSLOW DLOOP1 TXPWD RXPWD
RXDSNS(2: 0) BSTUFF SPWIDTH
R/W R/W
EOFRAME FFUNDER FFOVER FFDIR
TXPWR(1: 0)
ID(2) ID(1)
RO RO
SRESET
ID(0)
RO
5
6
7
Status Register
FFCLR FFEMPTY FFRXERR FFTXERR
RO
ROC
ROC
RO
WO
RO
ROC
ROC
FIFO Count (Note 1)
Register (LSB)
RO
RO
FFCNT(7:0)
FIFO Count (Note 1)
Register (MSB)
0
0
0
FFCNT(12: 8)
8
DPLL Tune Register
IRDIG Setup Register
Reserved
RO
DPCNT(5: 0)
LONGP(1: 0)
9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RXHIGH TXLOW Reserved Reserved Reserved Reserved Reserved Reserved
10
11
12
13
14
15
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Test Register
PLLDWN LOOPIR LOOPUSB TSTENA
TSTOSC(3: 0)
R/W : Read/Write
RO : Read only
ROC : Read only, clear on read
WO : Write only
Note: 1. Due to double buffering, FFCNT could be off by as much as 3 bytes
Table 10. Ir Transceiver Registers
6.1.
Detailed STIr4200 Register Descriptions
6.1.1.
FIFO Data Register
Offset 0
7
6
5
4
3
2
1
0
FIFO Data
Reserved
Default State
0
0
0
0
0
0
0
0
Bit Number Bit Mnemonic
7 – 0 Reserved
Access
Function
R/W
The FIFO data register is used internally by the USB interface to
access the FIFO data in the digital infrared block. Although this
register is accessible through the USB interface, it should never be
accessed during normal operation.
Table 11. FIFO Data Register
14
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O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
6.1.2.
Mode and Baud Rate Registers
Offset 1 and 2
6.1.2.1.
Mode Register
Offset 1
7
6
5
4
3
2
1
0
Mode Register
Default State
FIR
0
Reserved
0
SIR
1
ASK
0
FASTRXEN FFRSTEN FFSPRST PDCLK(8)
0
0
0
0
Bit Number Bit Mnemonic Access
Function
7
FIR
R/W When set, puts the infrared modulators into fast infrared mode (4PPM). Must
be mutually exclusive with the SIR bit.
6
5
Reserved
SIR
RO Reserved. Write as zero.
R/W When set, puts the infrared modulators into slow infrared mode. Must be
mutually exclusive with the FIR bit.
4
ASK
R/W When set, puts the infrared modulators into amplitude shift keying infrared
mode.
3
2
1
FASTRXEN
FFRSTEN
FFSPRST
R/W Enables simultaneous reads and writes to/from the FIFO.
R/W Allows the FIFO receive shift register to be automatically reset in FIR mode.
R/W Manually resets the FIFO shift register. Must be set to ‘1’ to release the FIFO
shift register from reset.
0
PDCLK(8)
R/W MSB of baud rate register.
Table 12. Mode Register
6.1.2.2.
Offset 2
Baud Rate Register
7
6
5
4
3
2
1
0
Baud Rate Register
Default State
PDCLK(7: 0)
0
1
1
1
0
1
1
1
Bit Number Bit Mnemonic Access
Function
7:0
PDCLK (7 : 0)
R/W Sets the divide ratio of the PLL for the infrared modulator/demodulator.
Table 13. Baud Rate Register
Below is a table of values to be written to the mode and baud rate registers to set
the required IrDA modes of operation:
Operational Mode
Speed
Mode Register
Baud Rate Register
FIR
4.0 Mbps
115.2 Kbps
57.6 Kbps
38.4 Kbps
19.2 Kbps
9.6 Kbps
0x80
0x20
0x20
0x20
0x20
0x20
0x21
0x02
0x09
0x13
0x1D
0x3B
0x77
0xDF
SIR
2.4 Kbps
Table 14. Mode and Buad Rate Values for Required IrDA Modes of Operation
3-4200-D1-2.0-0403
15
O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
6.1.3.
Control Register
Offset 3
7
6
5
4
3
2
1
0
Control Register
Default State
Bit Number Bit Mnemonic Access
7 SD/MODE
SDMODE RXSLOW Reserved
TXPWD
0
RXPWD
0
TXPWR(1: 0)
SRESET
0
0
0
0
0
0
Function
R/W Use this bit only when the STIr4200 is connected to a TEMIC style infrared
transceiver. This bit is used to put the infrared transceiver into the power
down state or toggle the transceiver between high and low speed.
POWER DOWN STATE: Set the SD/MODE bit to enter the power down state.
Clear the SD/MODE bit to exit the power down state.
SET TEMIC HIGH SPEED: Set the FIR bit (bit 7) in the Mode Register, then
set SD/MODE bit, then clear SD/MODE bit.
SET TEMIC LOW SPEED: Clear the FIR bit (bit 7) in the Mode Register, then
set the SD/MODE bit, then clear the SD/MODE bit.
The sequences described above for setting the high or low speed mode
enables a state machine in the STIr4200 to automatically toggle the TXDATA
and UOUT (SD/MODE) pins on the STIr4200.
6
RXSLOW
R/W When set, selects RXSLOW as the receive input. When cleared, selects
RXFAST as the receive input.
5
4
Reserved
TXPWD
R
Reserved
R/W When set, powers down the infrared transmitter (modulator).
R/W When set, powers down the infrared receiver (demodulator).
3
RXPWD
2-1
TXPWR(1: 0)
R/W Sets the internal pull down resistance to control the current presented to the
transmit diode.
00 : HIGH (max current)
01 : MED HIGH
10 : MED LOW
11 : LOW (min current)
0
SRESET
R/W When set, performs soft reset of the infrared modulator/demodulator.
Table 15. Control Register
16
3-4200-D1-2.0-0403
O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
6.1.4.
Sensitivity Register
Offset 4
7
6
5
4
3
2
1
0
Sensitivity Register
Default State
RXDSNS(2: 0)
0
Reserved SPWIDTH
ID(2: 0)
ID(1)
0
1
0
0
ID(2)
ID(0)
Bit Number Bit Mnemonic Access
Function
7-5
RXDSNS(2: 0)
R/W Used to program the sensitivity of the DRS demodulator. The corresponding
samples is the number of consecutive samples of an IrDA pulse it takes the
digital detector to declare the presence of a valid IrDA pulse.
Value
FIR
SIR
4
000
1
001
2
3
8
010
12
011
4
16
100
5
20
101
Illegal
Illegal
Illegal
24
110
111
28
Illegal
4
3
Reserved
SPWIDTH
RO Reserved. Write as zero.
R/W SIR transmit pulse width. When cleared, the pulse width for SIR mode
transmission is 1.6usec. When set, the pulse width is 3/16th the bit rate.
2-0
ID(2: 0) (Note 1) RO Revision ID of the chip.
Note: 1. For LA9 device revision, ID (2::0) = 1 1 1
Table 16. Sensitivity Register
6.1.5.
Status Register
Offset 5
7
6
5
4
3
2
1
0
Status Register
Default State
Reserved
0
FFDIR FFCLR FFEMPTY
Reserved
0
1
0
1
Bit Number Bit Mnemonic Access
Function
7-5
4
Reserved
FFDIR
N/A Reserved
RO When set, the FIFO is in transmit mode. When cleared, the FIFO is in receive mode.
3
FFCLR
WO When set, clears the FIFO by resetting the pointers to the empty position. This bit
must then be cleared to enable operation of the FIFO. Failing to do so, will
prohibit operation of the FIFO. The state of the bit can not be read.
2
FFEMPTY
Reserved
RO When set, indicates there is no data in the FIFO.
N/A Reserved
1-0
Table 17. Status Register
3-4200-D1-2.0-0403
17
O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
6.1.6.
FIFO Count Registers (LSB,MSB)
Offset 6&7
6.1.6.1.
FIFO Count LSB
Offset 6
7
6
5
4
3
2
1
0
FIFO Count Register (LSB)
Default State
FFCNT(7: 0)
0
0
0
0
0
0
0
0
Bit Number Bit Mnemonic Access
7-0 FFCNT(7:0)
Function
RO When combined with the FIFO Count Registers (MSB), indicates the number
of bytes in the FIFO.
Table 18. FIFO Count LSB
6.1.6.2.
Offset 7
FIFO Count MSB
7
6
5
4
3
2
1
0
FIFO Count Register (MSB)
Default State
Reserved
0
FFCNT(12: 8)
0
0
0
0
0
0
0
Bit Number Bit Mnemonic Access
Function
7-5
4-0
Reserved
RO
Write as zeros.
FFCNT(12:8)
RO When combined with the FIFO Count Registers (LSB), indicates the number
of bytes in the FIFO.
Table 19. FIFO Count MSB
6.1.7.
DPLL Tune Register
Offset 8
7
6
5
4
3
2
1
0
DPLL Tune Register
Default State
DPCNT(5: 0)
LONGP(1: 0)
0
1
0
1
0
0
1
0
Bit Number Bit Mnemonic Access
Function
7-2
1-0
DPCNT(5: 0)
LONGP(1: 0)
R/W Sets the sensitivity of the receiver’s digital PLL. This bit should be used for
chip debug purposes only. This register setting only affects FIR mode. The
default setting is proper for normal operation.
R/W Sets the sensitivity of the pulse detector of the receiver. These bits should be
used for chip debug purposes only.
Table 20. DPLL Tune Register
18
3-4200-D1-2.0-0403
O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
6.1.8.
IRDIG Setup Register
Offset 9
7
6
5
4
3
2
1
0
IRDIG Setup Register
Default State
RXHIGH TXLOW
Reserved
0
0
0
Bit Number Bit Mnemonic Read/Write Access
Function
7
RXHIGH
R/W
R/W
R/W
When set, this bit inverts the polarity of the data received by the
digital interface on the RXFAST and RXSLOW pins.
6
TXLOW
When set, this bits inverts the polarity of the data transmitted by
the digital interface on the TXDATA pin.
5-0
Reserved
Reserved
Table 21. IRDIG Setup Register
6.1.9.
Test Register
Offset 15
7
6
5
4
3
2
1
0
Test Register
Default State
PLLDWN LOOPIR
LOOPUSB Reserved
TSTOSC(3 : 0)
0
0
0
0
0
0
0
0
Bit Number Bit Mnemonic Read/Write Access
Function
7
PLLDWN
R/W
When set, powers down the secondary infrared transceiver PLL.
This bit should be cleared for SIR operation. Two independent
PLLs are required in this mode of operation. This bit should be
set for FIR operation since the infrared transceiver uses the USB
PLL in this mode of operation.
6
5
LOOPIR
R/W
R/W
When set, puts the infrared transceiver into internal loop back
using the FIFO to buffer data. This bit should be used for chip
debug purposes only.
LOOPUSB
When set, puts the USB interface into loop back mode using the
FIFO to buffer data. This bit should be used for chip debug
purposes only.
4
TSTENA
R/W
R/W
Enables the oscillator to be powered down while in USB Suspend
Mode.
3-0
TSTOSC(3: 0)
Sets the bias currents for the crystal oscillator circuitry. These bits
should be used for chip debug purposes only.
Table 22. Test Register
3-4200-D1-2.0-0403
19
O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
7. PIN DESCRIPTION
7.1. STIr4200S 28-Pin SSOP Pin Description
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TX
N/C
N/C
DIODE GND
2
TX
DIODE
3
N/C
N/C
X
X
TALO
TALI
4
5
RX
G
R
FAST
ND D
6
TX
DATA
ESET Z
ST_EN
ST D
7
RX
T
T
T
SLOW
STIr4200S
8
28-Pin SSOP
U
OUT
9
D
A
IGITAL GND
ST-CLK
10
11
12
13
14
V
U
V
DD
IN
NALOG GND
DA
D
D
NEG
POS
N/C
N/C
N/C
N/C
Note: “N/C” indicates the pin is “not connected”
Figure 8. STIr4200S 28-Pin SSOP Pin Assignment Drawing
Pin Number
Signal Name
Type
Description
1
2
3
TXDIODE GND
TXDIODE
NC
PWR
O
TXDIODE power supply ground
Optional LED driver output
No connect
4
NC
No connect
5
6
7
8
RXFAST
TXDATA
RXSLOW
UOUT
DGND
VDD
AGND
DNEG
NC
NC
NC
NC
DPOS
I
O
I
Receive data from IR module (Fast)
Transmit data output to IR module
Receive data from IR module (Slow)
SD/Mode control to IR module
Digital power supply ground
Digital power supply (+)
USB transceiver power supply ground
USB interface negative (-) data
No connect
No connect
No connect
No connect
USB interface positive (+) data
USB transceiver power supply (+)
Test
Test clock input
Test data input/output
Test enable
O
9
PWR
PWR
PWR
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O
PWR
I/O
I
I/O
I
I
PWR
I
VDA
UIN
TST-CLK
TSTD
TST_EN
RESETZ
GNDD
XTALI
XTALO
NC
Master reset, active low
Power supply ground
12Mhz crystal/clock input
12Mhz crystal/clock output
No connect
O
NC
No connect
Table 23. Pin Descriptions for STIr4200S 28-Pin SSOP Package
20
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O F F I C I A L P R O D U C T D O C U M E N T A T I O N
STIr4200
USB/IrDA Bridge Controller
8. PACKAGE DRAWINGS
Figure 9. 28-Pin SSOP Package Drawing
3-4200-D1-2.0-0403
21
相关型号：
STLS2F02-LP
MICROPROCESSOR, PBGA452, 27 X 27 MM, 2.90 MM HEIGHT, ROHS COMPLIANT, HFCBGA-452
STMICROELECTR
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