TECEV103 [ETC]
TEC CONTROLLER EVALUATION KIT TECEV103; TEC控制器评估板TECEV103
| 型号： | TECEV103 |
| 厂家： | 
ETC |
| 描述： | TEC CONTROLLER EVALUATION KIT TECEV103 |
| 文件： | 总5页 (文件大小：1032K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECEV103
Analog Technologies, Inc.
TEC CONTROLLER EVALUATION KIT TECEV103
(updated 06/17/04)
Our TEC controller modules can be evaluated conveniently by using this evaluation kit TECEV103 which comes with an
evaluation board, TECEVB103 and a TEC controller module of TEC-A1 (there is no internal compensation network inside).
The main purpose of using the evaluation board is to tune the compensation network on the board for matching the
characteristics of users’ thermal load. The objectives of the tuning are to minimize the response time of the thermal control
loop and the dynamic temperature tracking errors, while keeping the control loop stable.
1. Connection
For
For
multimeter oscilloscope
probing probing
To power supply
5V Imax = 2A
To A/D, D/A, and/or microprocessor
To TEC To Thermistor
TECN
TECP
RTH
TECN
TECP
+5V
GND
TEC- TEC+ Rth GND
LEDC
LEDA
TEC
Controller
RTH
Vlim
On
Power
On
Temp. good
LED
S3
Off
Off
TMPS
TMPS
TMPO
VDR
CMPIN
CMPO
Ri
Rp
TMPO
VDR
Cd
Ci
Rd
CIRP
CLHT
CDRD
3V
Cd
0
Ci
0
4.7uF
3.3uF
2.2uF
1.5uF
330nF
470nF
680nF
820nF
1uF
82nF
TMPGD
TMPGD
820nF
680nF
470nF
100nF
150nF
220nF
S1
S2
1uF
330nF
SDNG
GND
SDNG
GND
Wi
2M
Wd
Wp
2M
W1
5K
W2
5K
W3
500K
20K
Figure 1 TEC Controller Evaluation Board TECEV103
550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com
ã Copyright 1999 – 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04
1
TECEV103
Analog Technologies, Inc.
Figure 2 TECEV103 Photo
positions (down side). Check the evaluation board
connections, making sure that they are all correctly
connected. Turn on the Power side switch and see how
the Controller works.
Figure 1 shows the layout of the evaluation board and Figure
2 shows its photo.
These are the procedures for the adjustment.
2. Tune the compensation network. The purpose for this
step is to match the controller compensation network
with the thermal load characteristics thus that the
response time and temperature tracking error are
minimized. Adjust the potentiometer W1 to change
1. Set up basic connections. Connect a 5V DC power
supply and the TEC terminals in the right polarity as
indicated onto the board. Connect the thermistor
terminals to the board, there is no polarity requirement.
Turn the two switches, for Vlim and Power, to the off
550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com
ã Copyright 1999 – 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04
2
TECEV103
Analog Technologies, Inc.
the set-point temperature TMPS just a small amount,
simulating a step function. At the same time, connect
an oscilloscope at the VDR test pin (on the right side
of the evaluation board), set it to a scrolling mode (0.2
Second/Division or slower) and monitor the waveform
of VDR as TMPS is fed by a step function signal. The
circuit in the compensation network is shown in
Figure 3 below.
frequency goes down. It determines the cut-off
frequency below which the TEC controller will start
having a large open loop gain. The higher the open loop
gain, the smaller the tracking error will be.
d. Cd*Ri determines the corner frequency, w2=1/(Cd*Ri),
where the differential component starts picking up (see
Figure 4), as the frequency goes up.
e. Cd*Rd determines the corner frequency, w3=1/(Cd*Rd),
where the differential component starts getting flat. It
determines the cut-off frequency above which the TEC
controller will give extra weight or gain in response.
Rd
Rp
Cf
Ci
Cd
f. Cf*Rp determines the corner frequency, w4=1/(Cf*Rp),
where the differential component starts rolling down.
Since this frequency is way higher than being needed for
controlling the TEC, w4 does not need to be tuned. The
capacitor is built into the TEC controller module, not
the evaluation board.
Ri
-
+
TMPO
TMPS
VDR
To start the tuning, turn off the differential circuit by setting
Cd Open. Turn W1 quickly by a small angle, back and forth,
approximately 5 seconds per change. Set Ci to 1uF, set Ri to
1M, and increase the ratio of Rp/Ri as much as possible,
provided the loop is stable, i.e. there are no oscillations seen
in VDR. Then, minimize Ci as much as possible, provided
the loop is stable. The next step is to minimize Rd and
maximize Cd while maintaining about 10% overshoot found
in VDR. Optimum result can be obtained after diligent and
patient tuning. The tuning is fun and important.
Figure 3 Compensation network
The transfer function of the compensation network, defined
as H(w)=VDR(w)/TMPO(w), is shown in figure 4.
H(w)
Gd
0.71Gd
1.41Gp
Gp
When the TEC controller is used for driving a TEC to
stabilize the temperature of a diode laser, there is no need to
turn on the laser diode while tuning the TEC controller. To
simulate the active thermal load given by the laser diode,
setting the set-point temperature lower than the room
temperature is enough.
w
w1
w2 w3
w4
Figure 4 Transfer Function of the Compensation Network
For a typical laser head used in EDFA’s or laser transmitters
(found in DWDM applications, for instance), Ri = 1MW, Rp
= 1MW, Ci = 680nF, Cd = 1.5mF, and Rd = 250kW. These
values may vary, depending on the characteristics of a
particular thermal load.
In principle, these are the impacts of the components to the
tuning results:
a. Rp/Ri determines the gain for the proportional
component of the feedback signal which is from the
thermistor, Gp = Rp/Ri, in the control loop, the higher
the gain, the smaller the short term error in the target
temperature (which is of the cold side of the TEC)
compared with the set-point temperature, but the higher
the tendency of the loop’s instability.
To be conservative in stability, use larger Ci and larger Ri;
To have quicker response, use smaller Rd and larger Cd.
The closer to the TEC the thermistor is mounted, the easier
to have the loop stabilized, the shorter the rise time and the
settling time of the response will be.
b. Rp/Rd determines the gain for the differential
component, Gd = Rp/(Rd//Ri) » Rp/Rd, where symbol
“//” stands for two resistors in parallel, since Ri >> Rd,
Rd//Ri = Rd. The higher the gain, the shorter the rise
time of the response, the more the overshoot and/or the
undershoot will be.
3. After tuning, the values of the capacitors for Cd and Ci
can be read off the capacitor selection switches. The
values of the resistors, Ri, Rd and Rp, can be measured
by an Ohm-meter by connecting to the resistor pins. As
seen in the photo of Figure 2, Ri can be read off between
TMPO and CMPIN test points; Rd can be read off
c. Ci*Rp determines the corner frequency, w1= 1/(Ci*Rp),
where the integral component starts picking up, as the
550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com
ã Copyright 1999 – 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04
3
TECEV103
Analog Technologies, Inc.
between CMPIN and CDRD test points; Rp can be read
off between CMPIN and CIRP test points.
f. To control the TEC voltage directly by using a DAC,
connect VDR to the output of the DAC and use this formula:
TEC voltage = 2.5V – VDR (V).
4. After the compensation network is tuned properly, we
can now adjust set-point temperature to see if the TEC
controller can drive the target temperature to a certain
range and with high stability. Turn the temperature set-
point TMPS potentiometer W1 while monitoring its
output voltage at TMPS test point (4th row on either left
or right side of the board), watch the LED: when it turns
to green, the target temperature is locked to the set-point
temperature within 0.1°C or less. The relationship
between the set-point voltage vs. the set-point
temperature is given in the datasheet. After seeing the
LED lock into the set-point temperature, VDR should be
a constant voltage as shown in the oscilloscope and the
voltage between TMPS and TMPO should be very small,
less than 10mV. When a standard TEC controller is
used, the 10mV represent a 0.07° temperature error.
g. To shut down the TEC controller by using
a
microprocessor, turn off the Power switch, connect SDN test
point (2nd row from the bottom side, on both left and right
columes.) to one of its digital outputs. When pulling low,
the TEC controller is shut off. When pulling high SDN, the
TEC controller is turned on.
h. The evaluation schematic is given in Figure 5.
Using the TEC controller for more applications not
described here, and/or having any questions, please free to
contact us.
5. Set output voltage limit.
6. To know more parameters of the TEC controller.
a. To know the actual target temperature, use a voltage meter
to measure the voltage between the TMPO and the GND
pins, the reading result is: target temperature = 15°C +
(TMPO voltage (V))*6.67°C for approximation (see the
curve in the TEC controller data sheet).
b. To know how hard the TEC is working, measure the
voltage VDR by a voltage meter or an ADC, TEC voltage =
2.5V – VDR. When the TEC voltage (from the calculation)
is positive, it is in cooling mode; when the TEC voltage is
negative, it is in heating mode. Cool/Heat Balance CLHT
can be adjusted by W2. TEC maximum voltage can be
reduced by reducing W3, make sure Vlim switch is now
turned to the on position.
c. To try other values of capacitors not provided by the
evaluation board for the capacitors in the compensation
network, turn the capacitor switches you want to try to the
top point, the “0” position, connect the component to the
corresponding soldering pads as marked on the evaluation
board.
d. To shut down the TEC controller, turn the Power switch
to the “Off” position, see Figure 2.
e. To control the set-point temperature directly by using a
DAC, set the set-point temperature POT W1 to the middle
point (25°C), on which the TMPS is about 1.5V, the half
value of the reference voltage, connect TMPS test point to
the output of the DAC and use this formula for
approximation when the input voltage is between 0V and
3V:
set-point temperature (°C) = 15°C + (TMPO voltage
(V))*6.67°C. The maximum voltage allowed is Vps (power
supply). See the curve in the TEC controller data sheet.
550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com
ã Copyright 1999 – 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04
4
TECEV103
Analog Technologies, Inc.
TMPO
WI 2M
CMPIN WP 2M
CMPO
Ri
1
3
3
1
2
Left Side
SPL1
RightSide
TT1
Top Side
1
THL1
THR1
1
SPR1
SPT1
Rp
Ci
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RI
1
2
TECN
TECP
RTH
S_Pad
TECN
TECP
RTH
TECN
TECP
RTH
TECN
TECN
TECP
RTH
S_Pad
5V
PGND
TECN
TECP
RTH
L_Pad
TEC-
TT2
TEC-
SPL2
TEC-
THL2
TEC-
THR2
TEC-
SPR2
5V
SPT2
RP
1
1
1
1
1
1
1
1
1
S2
ST9P
S_Pad
TECP
RTH
S_Pad
L_Pad
S1
CD1 330nF
CI1
2
82nF
1
TEC+
TT3
TEC+
SPL3
TEC+
THL3
TEC+
THR3
TEC+
SPR3
0V
SPT3
1
2
3
4
5
6
7
8
9
2
1
1
2
3
4
5
6
7
8
9
CD2 470nF
CI2 100nF
2
S_Pad
S_Pad
L_Pad
TEC-
SPT4
2
1
1
3
1
RTH
TT4
RTH
SPL4
RTH
THL4
RTH
THR4
RTH
SPR4
WD 500K
CD3 680nF
CI3 150nF
2
1
1
1
2
1
1
TMPS
TMPO
VDR
S_Pad
TMPS
TMPS
TMPO
VDR
TMPS
TMPO
VDR
TMPS
TMPO
VDR
S_Pad
L_Pad
TMPS
TT5
TMPS
SPL5
TMPS
THL6
TMPS
THR5
TMPS
SPR5
TEC+
SPT5
CD4 820nF
CI4 220nF
2
2
1
1
S_Pad
S_Pad
S_Pad
CD5 1uF
CI5 330nF
2
TMPO
TT6
TMPO
SPL6
TMPO
THR6
TMPO
SPR6
RTH-1
SPT6
RD
2
2
1
1
1
1
1
0
CD6 1.5uF
CI6
2
470nF
1
0
S_Pad
VDR
TMPGD
SDN
S_Pad
GND
S_Pad
1
2
VDR
TT7
VDR
SPL7
VDR
THL7
VDR
THR7
VDR
SPR7
RTH-2(GND)
CD7 2.2uF
CI7 680nF
2
1
2
1
TMPGD
SDN
S_Pad
TMPGD
SDN
TMPGD
SDN
TMPGD
SDN
S_Pad
TMPGD
TT8
TMPGD
SPL8
TMPGD
THL8
1
TMPGD
THR8
1
TMPGD
SPR8
CD8 3.3uF
CI8 820nF
1
ST9P
1
2
2
S_Pad
S_Pad
CD9 4.7uF
CI9 1uF
1
SDN
TT9
SDN
SPL9
SDN
THL9
1
SDN
THR9
1
SDN
SPR9
Rd
2
1
2
Cd
GND
S_Pad
GND
GND
GND
GND
GND
S_Pad
GND
GND
10
10
GND
GND
CHB
CD
CI
1
2
1
2
LEDA
LEDC
3V
LEDA
LEDC
BottomSide
THM1
TMPO
THM2
CDRD
THM3
CMPIN
THM4
CIRP
THM5
CMPO
THM6
LEDA
THM7
LEDC
THM8
3V
THM9
CLHT
SPM1
LEDA
SPM2
LEDC
U1
TECA1
1
16
TMPGD
3V
TEMPGD
VPS
5V
PGND
TMPS
3V
5V
CHB
W3
20K
S3
5V
2
2
3
4
5
6
7
8
15
14
13
12
11
10
9
3
4
LEDC
LEDA
3V
GNDP
GNDP
SDN
VDR
W1 W2
5K 5K
LED1
R3 1K
2
2
1
3
2
1
TMPS
TEMPSP
GND
1
2
1
2
5V
N1206-4
TECNEG
TECPOS
RTH
TECN
TECP
RTH
SML-LX2832SUGC
R4
R2
1
Q1
VDR
CMPO
CMPIN
TMPO
TECCRT
VTEC
CMIN
TEMP
1
2
1
TECEV-103
R1
100
TMPGD
10K
100K
MMBT6428
GND
SDNG
SDN
Figure 5 Evaluation Board Schematic
550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com
ã Copyright 1999 – 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04
5
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