TXC-04011-BIPQ_技术文档

ADMA-T1P Device

1.544 Mbit/s to VT1.5/TU-11 Async Mapper-Desync

TXC-04011

DATA SHEET

Preliminary

FEATURES

DESCRIPTION

• Add/drop two 1.544 Mbit/s signals from an

STS-1, an STS-3/AU-3, or an STM-1 VC-4

The ADMA-T1P device is designed for add/drop

multiplexer, terminal multiplexer, and dual and single

unidirectional ring applications. Two T1 1.544 Mbit/s

signals are mapped to and from asynchronous 1.5

Virtual Tributaries (VT1.5s) or Tributary Unit - 11s (TU-

11s). The ADMA-T1P interfaces to a multiple-segment,

byte-parallel SONET/SDH-formatted bus at the 19.44

Mbit/s byte rate for STM-1/STS-3 operation or at the

6.48 Mbit/s byte rate for STS-1 operation. The T1 1.544

Mbit/s signals can be either AMI/B8ZS positive/negative

rail- or NRZ-formatted signals. The ADMA-T1P

provides performance counters, alarm detection, and

the ability to generate errors and Alarm Indication

Signals (AIS). T1 port loopback capability is also

provided. The dual timing mode Plus feature increases

the I/O signal pin count by 7 from the ADMA-T1 device

level so that the ADMA-T1P has a 120-pin package.

• Independent add and drop bus timing modes

• Selectable AMI or B8ZS positive/negative rail or

NRZ T1 interface. Performance counter

provided for illegal coding violations

• Digital desynchronizer reduces systemic jitter in

the presence of multiple pointer movements. A

register is also provided to control the internal

FIFO leak rate

• Drop buses are monitored for parity, loss of

clock, and H4 multiframe errors

• Performance counters are provided for VT/TU

pointer movements, BIP-2 errors and Far End

Block Errors (FEBEs)

The ADMA-T1P bus interface is used to connect to

other TranSwitch devices such as the STM-1/STS-3/

STS-3c Overhead Terminator (SOT-3), TXC-03003, to

form an STS-3/STM-1 add/drop or terminal system.

• VT/TUs are monitored for Loss Of Pointer, New

Data Flags (NDFs), AIS, Remote Defect

Indication (RDI), and size errors (S-bits)

APPLICATIONS

• V5 byte Signal Label Mismatch and Unequipped

detection

• STS-1/STS-3/STM-1 to 1.544 Mbit/s add/drop

mux/demux

• Loopback, generate BIP-2 errors, and send RDI

capability

• Unidirectional or bidirectional ring applications

• STS-1/STS-3/STM-1 termination terminal mode

multiplexer

• Intel microprocessor interface

• 120-pin plastic quad ﬂat package

• STS-1/STS-3/STM-1 test equipment

STS-1/STS-3/STM - 1

1.544 Mbit/s

LINE SIDE

TERMINAL SIDE

+5V

12

A - side

drop bus

Port 1 receive

P, N, and clock

3

ADMA-T1P

A - side

add bus

13

12

13

Port 1 transmit

P, N, and clock

1.544 Mbit/s to VT1.5/TU-11

Async Mapper - Desync

B - side

drop bus

Port 2 receive

P, N, and clock

TXC-04011

B - side

add bus

Port 2 transmit

P, N, and clock

Y

Timing Mode

Select

External

Clock

Microprocessor

interface

PELMINAR

U.S. Patents No.: 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,057

U.S. and/or foreign patents issued or pending

Document Number:

Copyright

1995 TranSwitch Corporation

TXC-04011-MB

TXC and TranSwitch are registered trademarks of TranSwitch Corporation

Ed. 1, September 1995

TranSwitch Corporation

8 Progress Drive

Shelton, CT 06484

USA

Tel: 203-929-8810 Fax: 203-926-9453

•

ADMA-T1P

TXC-04011

PRELIMINARY

TABLE OF CONTENTS

SECTION

PAGE

Block Diagram ..................................................................................................................... 3

Block Diagram Description .................................................................................................. 3

Pin Diagram ......................................................................................................................... 6

Pin Descriptions ................................................................................................................... 6

Absolute Maximum Ratings ............................................................................................... 14

Thermal Characteristics ..................................................................................................... 14

Power Requirements ......................................................................................................... 14

Input, Output and I/O Parameters ...................................................................................... 15

Timing Characteristics ....................................................................................................... 17

Memory Map ...................................................................................................................... 25

Memory Map Descriptions ................................................................................................. 28

Multiplex Format and Mapping Information ........................................................................ 47

Package Information .......................................................................................................... 53

Ordering Information .......................................................................................................... 54

Related Products ............................................................................................................... 54

Standards Documentation Sources ................................................................................... 55

Documentation Update Registration Form ................................................................... 59

LIST OF FIGURES

PAGE

Figure 1. ADMA-T1P TXC-04011 Block Diagram ............................................................ 3

Figure 2. 1.544 Mbit/s Mapping ....................................................................................... 5

Figure 3. ADMA-T1P TXC-04011 Pin Diagram ............................................................... 6

Figure 4. Ports 1 and 2 DS1 Transmit Timing ............................................................... 17

Figure 5. Ports 1 and 2 DS1 Receive Timing ................................................................ 18

Figure 6. STS-1 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus.......... 19

Figure 7. STS-3/STM-1 A/B Drop and Add Bus Signals,

Timing Derived from Drop Bus ....................................................................... 20

Figure 8. STS-1 A/B Add Bus Signals, Timing Derived from Add Bus ........................... 21

Figure 9. STS-3/STM-1 A/B Add Bus Signals, Timing Derived from Add Bus .............. 22

Figure 10. Microprocessor Read Cycle - Intel Timing ...................................................... 23

Figure 11. Microprocessor Write Cycle - Intel Timing ...................................................... 24

Figure 12. ADMA-T1P TXC-04011 120-Pin Plastic Quad Flat Package .......................... 53

TXC-04011-MB

Ed. 1, September 1995

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ADMA-T1P

TXC-04011

PRELIMINARY

BLOCK DIAGRAM

TERMINAL SIDE

LINE SIDE

Repeated (Ports 1 and 2)

Destuff Desync

A

Receive

VT/TU

Terminate

RPOn

AMI/B8ZS

Coder

RNOn

RCOn

VT/TU

Terminate

A

Transmit

RESET

Control

Micro-

processor

Bus

VT/TU

Select

12 13 12 13

ABUST

EXTCK

B

Receive

VT/TU

Build

Stuff/

Sync

TPIn

TNIn

TCIn

AMI/B8ZS

Decoder

•

B

VT/TU

Build

Stuff/

Sync

Transmit

Note: n=1-2

Repeated (Ports 1 and 2)

Figure 1. ADMA-T1P TXC-04011 Block Diagram

BLOCK DIAGRAM DESCRIPTION

The block diagram for the ADMA-T1P is shown in Figure 1. The ADMA-T1P interfaces to four buses, desig-

nated as A Drop, A Add, B Drop and B Add. The four buses run at the STS-3/STM-1 rate of 19.44 Mbytes/s, or

at the STS-1 rate of 6.48 Mbytes/s. For North American applications, the asynchronous T1 signals are carried

in ﬂoating Virtual Tributary 1.5s (VT1.5s) in a Synchronous Transport Signal -1 (STS-1), or in STS-1s that are

carried in the Synchronous Transport Signal - 3 (STS-3). For ITU-T applications, the T1 signals are carried in

ﬂoating mode Tributary Unit - 11s (TU-11s) in the STM-1 Virtual Container - 4 structure (VC-4) using Tributary

Unit Group - 3 (TUG-3), or in the STM-1 Virtual Container - 3 structure (VC-3) using Tributary Unit Group - 2

(TUG-2) mapping schemes. Two T1 signals can be connected (dropped) from one bus (A Drop or B Drop), or

both of the drop buses to the T1 lines. Two asynchronous T1 signals are formatted into VT1.5s or TUs and are

connected (added) to either of the add buses (or both, depending upon the mode of operation). When the

ABUST input is set high to conﬁgure the ADMA-T1P for the drop bus timing mode, the add buses are, by deﬁ-

nition, byte, frame, and multiframe synchronous with their like-named drop buses, but delayed because of

internal processing. For example, if a byte from a VT1.5 or TU-11 is to be added to the A Add bus, the time of

its placement on the bus is derived from A Drop bus timing, and from software instructions specifying which

VT/TU number is to be dropped. When the device is conﬁgured for the add bus timing mode (ABUST set low),

the add bus data, parity and add indicator signals are derived from the add clock, C1J1V1 and SPE signals.

There will be a delay of either one or two clock cycles for the output signals relative to the add bus C1J1V1 and

SPE signals.

TXC-04011-MB

Ed. 1, September 1995

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ADMA-T1P

TXC-04011

PRELIMINARY

The A Receive Block is identical to the B Receive Block. The VT/TU Terminate, Destuff, Desync, and AMI/

B8ZS Line Coder Blocks are also repeated for both ports. Twelve leads are connected between a drop bus

and the ADMA-T1P A or B Drop bus interface. The interface consists of a byte clock, byte-wide data, a C1J1

indicator signal, a payload identiﬁcation signal (SPE) and parity. Parity is selectable for odd or even parity, and

for data only.

Depending upon the application, buffers and latches may be used between the system buses and an ADMA-

T1P. Each bus interface is monitored for parity, loss of clock, and H4 multiframe errors. Under microprocessor

control, the two receive blocks extract a VT1.5 or TU-11 from the STS-3 or VC-4 in the VT/TU Terminate

Blocks.

Each Terminate Block performs pointer processing (V1 and V2), overhead byte (V5) processing, and provides

a bit status of the eight receive overhead communications bits located in the control bytes in the VT/TU (see

Figure 2). The pointer bytes are monitored for an NDF indication, and for AIS, and Loss Of Pointer alarms. In

addition, the size (S-bits) in the pointer bytes are monitored for the correct value. Overhead byte (V5) process-

ing includes a BIP-2 parity check, along with the count of detected errors, counting the number of received Far

End Block Errors (FEBE), the states of the receive signal label, mismatch of the receive signal label against a

microprocessor written value, unequipped status detection, and the status of the Remote Defect Indication

(RDI) bit, and the Remote Failure Indication (RFI) bit.

Depending on the drop bus selected, the VT/TU is destuffed using majority rule for the two sets of three justiﬁ-

cation control bits (Cn) which determines whether the two S-bits are data bits or justiﬁcation bits.

The Desync Block removes the effects on the output of systemic jitter that might occur due to signal mappings

and pointer movements. The Desync Block contains two parts, a pointer leak buffer and a T1 loop buffer. The

function of the pointer leak buffer is to accept up to ﬁve consecutive positive or negative pointer adjustments

and to ramp out the effect over a speciﬁed period of time. The T1 Loop Buffer consists of a digital loop ﬁlter,

which is designed to track the frequency of the received T1 signal and to remove both transmission and stuff-

ing jitter.

An option for each port provides either NRZ data and clock or an AMI/B8ZS-coded positive and negative rail

signals for the T1 line interface. Transmit data (towards the T1 line) is clocked out of the ADMA-T1P on rising

edges of the clock.

Towards the SONET/SDH add buses, the ADMA-T1P accepts either T1 AMI/B8ZS-coded positive and nega-

tive rail signals or NRZ data. A 16-bit performance counter is provided that counts illegal AMI or B8ZS coding

violations. The T1 line is monitored for AIS, and loss of clock or signal.

The Stuff/Sync Block time buffers the T1 signal for frequency justiﬁcation by the Stuff Block. The Stuff/Sync

Block contains a FIFO and uses threshold modulation for the VT/TU justiﬁcation process.

This Block also permits tracking of the incoming T1 signal having an average frequency offset as high as 120

ppm, and up to 5 UI of peak-to-peak jitter. The interface between this Block and the VT/TU Build Block is bi-

directional. The VT/TU Build Block request bits from the FIFO based on the VT/TU phase. The justiﬁcation

algorithm ﬁxes the ﬁrst S-bit (S1) to the pattern 1110 every four multiframes. The second S-bit contains either

data or a justiﬁcation bit based on a length measurement. Since the ADMA-T1P supports a ring system archi-

tecture, two sets of Blocks are provided for each port.

The VT/TU Block formats the VT/TU into an STS-1, STS-3 or STM-1 structure for asynchronous 1.544 Mbit/s

signals, as shown in Figure 2. The pointer value (in the V1 and V2 bytes) is ﬁxed to a value of 78. Access is

provided for determining the states of the overhead communications channel (O-bits) located in two justiﬁca-

tion control bytes in the VT/TU format. Access is also provided for transmitting the signal label and the Remote

Defect Indication (RDI) bit, both of which are located in the V5 overhead byte. The Far End Block Error (FEBE)

bit state is determined by the BIP-2 detector in the drop side. In addition, a control bit is provided for generating

a VT/TU AIS (all ones).

TXC-04011-MB

Ed. 1, September 1995

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ADMA-T1P

TXC-04011

PRELIMINARY

Figure 2. 1.544 Mbit/s Mapping

VT1.5

V5

V1 (Pointer Byte)

R R R R R R I R

24 bytes

(1.544 Mbit/s Data)

26 bytes

J2

C C O O O O I R

1

2

V2 (Pointer Byte)

26 bytes

24 bytes

(1.544 Mbit/s Data)

Z6

C C O O O O I R

1

2

V3 (Action)

26 bytes

24 bytes

(1.544 Mbit/s Data)

I = Information

O = Overhead communications

C_n= Justification control

S_n= Justification opportunity

R = Fixed stuff (set to 0)

Z7

C C R R R S S R

1

2

1

2

24 bytes

(1.544 Mbit/s Data)

V4 (Reserved)

26 bytes

104 Bytes

500 µs

Path Overhead

(V5) Byte

L₁

L₂

L₃

BIP-2

FEBE RFI

RDI

V₁

1

Signal Label

BIT 1

8

V₂

BIP-2 = Bit Interleaved Parity (2 bits)

FEBE = Far End Block Error Indication

RFI = Remote Failure Indication

L₁L₂L₃= Signal Label

NDF

S₁S₂

I

D

I

D

I

D

I

D

I

D

RDI = Remote Defect Indication

New Data Flag

Normal = 0110

New = 1001

Size

S S = 11

1

2

Positive Justiﬁcation = Invert ﬁve I-bits

Negative Justiﬁcation = Invert ﬁve D-bits

Pointer Range = 0 - 103 decimal

TXC-04011-MB

Ed. 1, September 1995

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ADMA-T1P

TXC-04011

PRELIMINARY

PIN DIAGRAM

BDSPE

UPAD0/D0

UPAD1/D1

UPAD2/D2

UPAD3/D3

NC

UPAD4/D4

UPAD5/D5

VDD

UPAD6/D6

GND

UPAD7/D7

NC

60

55

50

45

40

35

BAPAR

BA7

BA6

BA5

BA4

NC

BA3

BA2

VDD

BA1

GND

BA0

NC

95

100

105

110

115

ADMA-T1P

Pin Diagram

(Top View)

GND

HIGHZ

NC

VDD

NC

VDD

NC

SEL

VDD

RD

WR

GND

ALE

GND

ABUST

VDD

GND

NC

AA0

NC

TXC-04011

AA1

VDD

AA2

AA3

GND

AA4

AA5

AA6

AA7

AAPAR

TEST

EXTCK

RESET

ADSPE

Figure 3. ADMA-T1P TXC-04011 Pin Diagram

PIN DESCRIPTIONS

POWER SUPPLY AND GROUND

Symbol

Pin No.

I/O/P *

Type

Name/Function

VDD

8, 14, 25, 39, 45, 52,

P

I

VDD: +5-volt supply voltage, ±5%.

66, 77, 99, 107, 109, 112

GND

15, 20, 22, 36, 44, 47,

P

I

Ground: 0 volts reference

50, 69, 75, 83, 101, 104, 115

Note: I = Input; O = Output; P = Power

TXC-04011-MB

Ed. 1, September 1995

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ADMA-T1P

TXC-04011

PRELIMINARY

Symbol

Pin No.

I/O/P *

Type

Name/Function

NC

9, 11, 16, 41,

43, 48, 55, 71,

76, 80, 82, 96,

103, 106, 108, 110

--

No Connect: NC pins are not to be con-

nected, not even to another NC pin, but

must be left ﬂoating. Connection of NC

pins may impair performance or cause

damage to the device.

A DROP AND A ADD BUS I/O

Symbol

Pin No.

I/O/P

Type *

Name/Function

ADCLK

17

I

TTL

A Drop Bus Clock: This clock operates at 19.44 MHz

for STS-3/STM-1 operation, and at 6.48 MHz for STS-1

operation. A Drop bus byte-wide data (AD7-AD0), the

parity bit (ADPAR), SPE indication (ADSPE), and the

C1J1 byte indicator (ADC1J1) inputs are detected on

falling edges of this clock. In the drop timing mode (lead

ABUST is high) this clock is also used for timing and

deriving the like-named add bus byte-wide data (AA7-

AA0), add indicator (AADD), and parity bit (AAPAR).

These signals are clocked out on rising edges of this

clock during the time slots that correspond to the

selected VT/TU.

ADPAR

AD(7-0)

19

I

TTL

A Drop Bus Parity Bit: Odd parity bit input signal rep-

resenting the parity calculation for each data byte (AD7-

AD0), SPE indication (ADSPE), and the C1J1 byte indi-

cator (ADC1J1) from the drop bus. Control register bits

are provided which allow choice of even parity instead,

and/or restrict the parity bit detection to the data byte

only.

21, 23, 24,

26, 27, 28,

29, 30

A Drop Bus Data Byte: Byte-wide data corresponding

to the STS-1/STS-3/STM-1 signal from the bus. The ﬁrst

bit received (dropped) from the bus corresponds to bit 7

(pin 21).

ADSPE

ADC1J1

120

12

I

TTL

A Drop Bus SPE Indicator: A signal that is active high

during each byte of the STS-1/STS-3/STM-1 payload.

A Drop Bus C1/J1 Indications: An active high timing

signal that carries STS-1/STS-3/STM-1 frame and SPE

information. The C1 pulse identiﬁes the location of the

ﬁrst C1 byte in the STS-3/STM-1 signal and the C1 byte

in the STS-1 signal. A J1 pulse, one clock cycle wide,

identiﬁes the location of the J1 byte in the STM-1 VC-4

signal. Three J1 pulses are provided to identify the J1

byte locations in the STM-1 AU-3s or STS-3/STS-1

SPEs. One J1 pulse is provided to identify the location

of the J1 pulse for STS-1 SPE bus operation. If one or

more V1 pulses are present in the signal, they are

ignored.

*See Input, Output and I/O Parameters section below for Type deﬁnitions.

TXC-04011-MB

Ed. 1, September 1995

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ADMA-T1P

TXC-04011

PRELIMINARY

Symbol

Pin No.

I/O/P

Type *

Name/Function

AACLK

18

I

TTL

A Add Bus Clock: When the ABUST lead is low, this

clock must be provided for add bus timing. This clock

operates at 19.44 MHz for STS-3/STM-1 operation, and

at 6.48 MHz for STS-1 operation. The add bus SPE indi-

cation and the C1J1 indicators are input into the ADMA-

T1P on falling edges of this clock. The add bus byte-

wide data, add indicator, and parity bits are clocked out

on rising edges of the clock during the time slots that

correspond to the selected VT (TU). When ABUST is

high, this input is disabled.

AAPAR

31

O

CMOS 4mA A Add Bus Parity Bit: An odd parity output signal cal-

culated over the byte-wide add data. This 3-state lead is

only active when there are data being added to the add

bus. A control bit is provided that allows even parity to

be calculated.

(tristate)

AA(7-0)

AASPE

32, 33, 34,

35, 37, 38, (tristate)

40, 42

O

CMOS 4mA A Add Bus Data Byte: 3-state byte-wide data that cor-

responds to the selected VT (TU). The ﬁrst bit transmit-

ted (added) to the bus corresponds to bit 7 on pin 32.

6

I

TTL

A Add Bus SPE Indicator: When the ABUST lead is

low, this signal must be provided for add bus timing.

This signal is active high during each byte of the

STS-1/STS-3/STM-1 payload.

AAC1J1V1

13

I

TTL

A Add Bus C1J1V1 Indication: When the ABUST lead

is low, this signal must be provided for add bus timing.

This signal carries STS-1/STS-3/STM-1 frame and SPE

information. The C1 pulse identiﬁes the ﬁrst C1 byte

time in the STS-3/STM-1 signal and the C1 byte time in

the STS-1 signal. A J1 pulse, one clock cycle wide,

identiﬁes the location of the J1 byte in the STM-1 VC-4

signal. Three J1 pulses are provided to identify the loca-

tions of the STM-1 AU-3s or STS-3 SPEs. One J1 pulse

is provided to identify the location of the J1 pulse for

STS-1 SPE bus operation. The V1 pulses are used as

multiframe indications.

10

O

CMOS 4mA A Add Bus Add Data Present Indicator: This normally

active low signal is present when output data to the A

Add bus are valid. It identifies the location of the VT

(TU) time slots being selected. A control bit is provided

that allows this bit to be active high instead of active

low.

AADD

TXC-04011-MB

Ed. 1, September 1995

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ADMA-T1P

TXC-04011

PRELIMINARY

B DROP AND B ADD BUS I/O

Symbol

Pin No.

I/O/P

Type

Name/Function

BDCLK

74

I

TTL

B Drop Bus Clock: This clock operates at 19.44 MHz

for STS-3/STM-1 operation, and at 6.48 MHz for STS-1

operation. B Drop bus byte-wide data (BD7-BD0), the

parity bit (BDPAR), SPE indication (BDSPE), and the

C1J1 byte indicator (BDC1J1) inputs are detected on

falling edges of this clock. In the drop timing mode (lead

ABUST is high) this clock is also used for timing and

deriving the like-named add bus byte-wide data (BA7-

BA0), add indicator (BADD), and parity bit (BAPAR).

These signals are clocked out on rising edges of this

clock during the time slots that correspond to the

selected VT/TU.

BDPAR

BD(7-0)

72

I

TTL

B Drop Bus Parity Bit: Odd parity bit input signal rep-

resenting the parity calculation for each data byte (BD7-

BD0), SPE indication (BDSPE), and the C1J1 byte indi-

cator (BDC1J1) from the drop bus. Control register bits

are provided which allow choice of even parity instead,

and/or restrict the parity bit detection to the data byte

only.

70, 68, 67,

65, 64, 63,

62, 61

B Drop Bus Data Byte: Byte-wide data corresponding

to the STS-1/STS-3/STM-1 signal from the bus. The ﬁrst

bit received (dropped) from the bus corresponds to bit 7

(pin 70).

BDSPE

BDC1J1

91

79

I

TTL

B Drop Bus SPE Indicator: A signal that is active high

during each byte of the STS-1/STS-3/STM-1 payload.

B Drop Bus C1/J1 Byte Indicators: An active high tim-

ing signal that carries STS-1/STS-3/STM-1 frame and

SPE information. The C1 pulse identiﬁes the location of

the ﬁrst C1 byte in the STS-3/STM-1 signal and the C1

byte in the STS-1 signal. A J1 pulse, one clock cycle

wide, identiﬁes the location of the J1 byte in the STM-1

VC-4 signal. Three J1 pulses are provided to identify the

J1 byte locations in the STM-1 AU-3s or STS-3/STS-1

SPEs. One J1 pulse is provided to identify the location

of the J1 pulse for STS-1 SPE bus operation. If one or

more V1 pulses are present in this signal, they are

ignored.

BACLK

73

I

TTL

B Add Bus Clock: When the ABUST lead is low, this

clock must be provided for add bus timing. This clock

operates at 19.44 MHz for STS-3/STM-1 operation, and

at 6.48 MHz for STS-1 operation. The add bus SPE indi-

cation and the C1J1 indicators are input into the ADMA-

T1P on falling edges of this clock. The add bus byte-

wide data, add indicator, and parity bits are clocked out

on rising edges of the clock during the time slots that

correspond to the selected VT (TU). When ABUST is

high, this input is disabled.

TXC-04011-MB

Ed. 1, September 1995

- 9 -

ADMA-T1P

TXC-04011

PRELIMINARY

Symbol

Pin No.

I/O/P

Type

Name/Function

BAPAR

60

O

CMOS 4mA B Add Bus Parity Bit: An odd parity output signal cal-

culated over the byte-wide add data. This 3-state lead is

only active when there are data being added to the add

bus. A control bit is provided that allows even parity to

be calculated.

(tristate)

BA(7-0)

BASPE

59, 58, 57,

56, 54, 53, (tristate)

51, 49

O

CMOS 4mA B Add Bus Data Byte: 3-state byte-wide data that cor-

responds to the selected VT (TU). The ﬁrst bit transmit-

ted (added) to the bus corresponds to bit 7 on pin 59.

85

I

TTL

B Add Bus SPE Indicator: When the ABUST lead is

low, this signal must be provided for add bus timing.

This signal is active high during each byte of the

STS-1/STS-3/STM-1 payload.

BAC1J1V1

78

I

TTL

B Add Bus C1J1 Indications: When the ABUST lead

is low, this signal must be provided for add bus timing.

This signal carries STS-1/STS-3/STM-1 frame and SPE

information. The C1 pulse identifies the first C1 byte

time in the STS-3/STM-1 signal and the C1 byte time in

the STS-1 signal. A J1 pulse, one clock cycle wide,

identifies the location of the J1 byte in the STM-1 VC-4

signal. Three J1 pulses are provided to identify the loca-

tions of the STM-1 AU-3s or STS-3 SPEs. One J1 pulse

is provided to identify the location of the J1 pulse for

STS-1 SPE bus operation. The V1 pulses are used as

multiframe indications.

BADD

81

O

CMOS 4mA B Add Bus Add Data Present Indicator: This normally

active low signal is present when output data to the B

Add bus are valid. It identiﬁes the location of the VT

(TU) time slots being selected. A control bit is provided

that allows this bit to be active high instead of active low.

DS1 PORT 1 INTERFACE

Symbol

Pin No.

I/O/P

Type

Name/Function

RCO1

1

O

CMOS 4mA Receive DS1 Output Clock, Port 1: A 1.544 MHz clock

output. Data are clocked out of the ADMA-T1P on rising

edges of this clock. Control bits are provided for invert-

ing this clock and for forcing this lead to 3-state.

(tristate)

RPO1

RNO1

3

2

O

CMOS 4mA Receive DS1 Data Positive Rail or NRZ, Port 1: When

the ADMA-T1P is operating with a rail interface, positive

rail data are provided on this lead. When operating in

the bypass mode, an NRZ signal is provided on this

lead. A control bit is provided for forcing this lead to 3-

state.

(tristate)

O

CMOS 4mA Receive DS1 Data Negative Rail, Port 1: When the

ADMA-T1P is operating with a rail interface, negative

rail data are provided on this lead. A control bit is pro-

vided for forcing this lead to 3-state. In the NRZ mode,

this lead is forced to a high impedance state.

(tristate)

TXC-04011-MB

Ed. 1, September 1995

- 10 -

ADMA-T1P

TXC-04011

PRELIMINARY

Symbol

Pin No.

I/O/P

Type

Name/Function

TCI1

4

I

TTLs

Transmit DS1 Input Clock, Port 1: A 1.544 MHz clock

input. Data are clocked into the ADMA-T1P on falling

edges of this clock. A control bit is provided for inverting

this clock.

TPI1

7

5

I

TTL

Transmit DS1 Data Positive Rail or NRZ, Port 1:

When the ADMA-T1P is operating with a rail interface,

positive rail input data are provided on this lead. When

operating in the bypass mode, an NRZ signal is pro-

vided on this lead.

TNI1/

Transmit DS1 Data Negative Rail, Port 1/External

Transmit Loss of Signal, Port 1: When the ADMA-T1P

is operating with a rail interface, negative rail input data

are provided on this lead. When the NRZ interface is

selected, this lead can be used to provide an input for

an active low external transmit loss of signal indication.

If this pin is not used for indicating a loss of signal then it

must be held high.

TLOS1

DS1 PORT 2 INTERFACE

Symbol

Pin No.

I/O/P

Type

Name/Function

RCO2

87

O

CMOS 4mA Receive DS1 Output Clock, Port 2: A 1.544 MHz clock

output. Data are clocked out of the ADMA-T1P on rising

edges of this clock. Control bits are provided for invert-

ing this clock and for forcing this lead to 3-state.

(tristate)

RPO2

RNO2

84

86

O

CMOS 4mA Receive DS1 Data Positive Rail or NRZ, Port 2: When

the ADMA-T1P is operating with a rail interface, positive

rail data are provided on this lead. When operating in

the bypass mode, an NRZ signal is provided on this

lead. A control bit is provided for forcing this lead to 3-

state.

(tristate)

O

CMOS 4mA Receive DS1 Data Negative Rail, Port 2: When the

ADMA-T1P is operating with a rail interface, negative

rail data are provided on this lead. A control bit is pro-

vided for forcing this lead to 3-state. In the NRZ mode,

this lead is forced to a high impedance state.

(tristate)

TCI2

TPI2

90

88

I

TTLs

Transmit DS1 Input Clock, Port 2: A 1.544 MHz clock

input. Data are clocked into the ADMA-T1P on falling

edges of this clock. A control bit is provided for inverting

this clock.

TTL

Transmit DS1 Data Positive Rail or NRZ, Port 2:

When the ADMA-T1P is operating with a rail interface,

positive rail input data are provided on this lead. When

operating in the bypass mode, an NRZ signal is pro-

vided on this lead.

TXC-04011-MB

Ed. 1, September 1995

- 11 -

ADMA-T1P

TXC-04011

PRELIMINARY

Symbol

Pin No.

I/O/P

Type

Name/Function

TNI2/

89

I

TTL

Transmit DS1 Data Negative Rail, Port 2/External

Transmit Loss or Signal, Port 2: When the ADMA-

T1P is operating with a rail interface, negative rail input

data are provided on this lead. When the NRZ interface

is selected, this lead can be used to provide an input for

an active low external transmit loss of signal indication.

If this pin is not used for indicating a loss of signal then it

must be held high.

TLOS2

MICROPROCESSOR BUS INTERFACE

Symbol

Pin No.

I/O/P

Type

Name/Function

UPAD(7-0)

or

D(7-0)

102, 100,

98, 97, 95,

94, 93, 92

I/O

TTL 8mA Address/Data Bus: These leads constitute the time

multiplexed address and data bus for accessing the reg-

isters which reside in the ADMA-T1P. UPAD7/D7 is the

most signiﬁcant bit. High is logic 1.

SEL

RD

111

113

114

116

I

TTLs

Select: A low enables the microprocessor to access the

memory map registers for control, status, and alarm

information.

Read: An active low signal generated by the micropro-

cessor for reading the registers which reside in the

memory map.

WR

ALE

Write: An active low signal generated by the micropro-

cessor for writing to the registers which reside in the

memory map.

Address Latch Enable: An active high signal gener-

ated by the microprocessor. Used by the processor for

holding an address stable during a read/write cycle.

TXC-04011-MB

Ed. 1, September 1995

- 12 -

ADMA-T1P

TXC-04011

PRELIMINARY

CONTROLS

Symbol

Pin No.

I/O/P

Type

Name/Function

TranSwitch Test Bit: Must be held high.

117

I

TTLs

TEST

EXTCK

118

I

CMOS

External Reference Clock: A 48.6360 MHz (+/- 32

ppm over life) clock that has a duty cycle of 50 +/- 10%

must be applied to this pin for operating the desynchro-

nizer, generating line AIS, and driving other internal cir-

cuitry.

119

I

TTLs

Hardware Reset: An active low pulse that must be

applied to this pin for a minimum of 150 nanoseconds

after power is ﬁrst applied. The reset clears all perfor-

mance counters and alarms, resets the control bits, and

initializes the internal FIFO. The microprocessor must

initialize the control bits for normal operation.

RESET

HIGHZ

ABUST

105

46

I

TTLs

TTL

High Impedance Select: A 0 sets all output pins to the

high impedance state for testing purposes. Otherwise,

this pin must be held high.

Add Bus Timing Select: A low selects the add bus tim-

ing mode. The add bus clock (AACLK, BACLK), SPE

(AASPE, BASPE) and C1J1V1 (AAC1J1V1,

BAC1J1V1) input signals are used for deriving data,

parity and add indicator signals for the A and B buses. A

high selects the drop bus timing mode. The add bus

data, parity and add indicator signals are derived from

the drop bus timing signals.

TXC-04011-MB

Ed. 1, September 1995

- 13 -

ADMA-T1P

TXC-04011

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Min *

Max *

Unit

Supply voltage

V

-0.5

-40

+6.0

V

DD

DC input voltage

V

+ 0.5

DD

IN

o

Ambient operating temperature

Operating junction temperature

Storage temperature range

T

85

C

A

o

T

150

C

J

o

T

-55

C

S

*Note: Operating conditions exceeding those listed in Absolute Maximum Ratings may cause permanent failure. Exposure

to absolute maximum ratings for extended periods may impair device reliability.

THERMAL CHARACTERISTICS

Parameter

Min

Typ

Max

Unit

Test Conditions

Thermal resistance:

o

junction to ambient

--

61

--

C/W

0 ft/min linear airﬂow

POWER REQUIREMENTS

Parameter

Min

Typ

Max

Unit

Test Conditions

V

4.75

5.0

5.25

133

700

175

920

V

DD

I

mA

mW

mA

mW

STS-1

DD

P

STS-1

DD

I

STS-3 or STM-1

DD

P

DD

TXC-04011-MB

Ed. 1, September 1995

- 14 -

ADMA-T1P

TXC-04011

PRELIMINARY

INPUT, OUTPUT AND I/O PARAMETERS

INPUT PARAMETERS FOR CMOS

Parameter

Min

Typ

Max

Unit

Test Conditions

4.75 < V < 5.25

V

3.15

V

IH

IL

DD

1.65

10

4.75 < V < 5.25

DD

Input leakage current

Input capacitance

µA

pF

V

= 5.25

DD

3.5

INPUT PARAMETERS FOR TTL

Parameter

Min

Typ

Max

Unit

Test Conditions

4.75 < V < 5.25

V

2.0

V

IH

IL

DD

0.8

4.75 < V < 5.25

DD

Input leakage current

Input capacitance

+1.0

µA

pF

V

= 5.25

DD

3.5

INPUT PARAMETERS FOR TTLs

Parameter

Min

Typ

Max

Unit

Test Conditions

VT- Negative going,

threshold voltage

0.8

V

VT+ Positive going,

threshold voltage

2.0

V

Input leakage current

Input capacitance

1.0

0.7

µA

pF

V

= 5.25

DD

3.5

Vhys Hysteresis

(VT+ - VT-)

0.3

TXC-04011-MB

Ed. 1, September 1995

- 15 -

ADMA-T1P

TXC-04011

PRELIMINARY

OUTPUT PARAMETERS FOR CMOS 4mA

Parameter Min Typ

- 0.8

Max

Unit

Test Conditions

= 4.75; I = -4.0

V

OH

OL

DD

OH

0.5

4.0

V

= 4.75; I = 4.0

OL

I

mA

µA

OL

-4.0

OH

OZ

+10.0

(HIGHZ output current)

INPUT/OUTPUT PARAMETERS FOR TTL 8mA

Parameter

Min

Typ

Max

Unit

Test Conditions

V

2.0

V

4.75 < V < 5.25

DD

IH

IL

0.8

4.75 < V < 5.25

DD

Input leakage current

Input capacitance

+1.0

µA

pF

V

= 5.25

DD

5.5

V

- 0.8

V

= 4.75; I = -8.0

OH

OL

DD

0.5

8.0

V

= 4.75; I = 8.0

OL

I

mA

OL

OH

-8.0

TXC-04011-MB

Ed. 1, September 1995

- 16 -

ADMA-T1P

TXC-04011

PRELIMINARY

TIMING CHARACTERISTICS

Detailed timing diagrams for the ADMA-T1P device are illustrated in Figures 4 through 11, with values of the

timing intervals tabulated below each timing diagram. All output times are measured with a maximum 45 pF

load capacitance. Timing parameters are measured at voltage levels of (V + V )/2 for input signals or (V

+

IH

IL

OH

V

)/2 for output signals.

OL

Figure 4. Ports 1 and 2 DS1 Transmit Timing

t

CYC

t

PWH

PWL

TCIn

(INPUT)

t

SU

t

H

TPIn/TNIn

(INPUT)

Note: n = 1 - 2

Note: TCIn is shown for TCLKI = 0, where data are clocked in on falling edges. Data are clocked in on rising edges when

TCLKI =1. For NRZ operation, TNIn may be used to input an external loss of signal indication. Otherwise, this pin

must be held high.

Parameter

TCIn clock period

Symbol

Min

Typ

Max

Unit

t

560.0

280.0

10.0

647.7

ns

CYC

PWL

PWH

TCIn clock low time

t

TCIn clock high time

t

TPIn/TNIn data set-up time before TCIn↓

TPIn/TNIn data hold time after TCIn↓

t

SU

t

2.0

H

TXC-04011-MB

Ed. 1, September 1995

- 17 -

ADMA-T1P

TXC-04011

PRELIMINARY

Figure 5. Ports 1 and 2 DS1 Receive Timing

t

CYC

t

PWL

PWH

RCOn

(OUTPUT)

t

OD

RPOn/RNOn

(OUTPUT)

Note: n = 1 - 2

Note: RCOn is shown for RCLKI=0, where data are clocked out on rising edges. Data are clocked out on falling edges

when RCLKI=1.

Parameter

RCOn clock period

Symbol

Min

Typ

Max

Unit

t

637

318

0.0

658

329

5.0

ns

CYC

PWL

PWH

RCOn clock low time

t

RCOn clock high time

t

RPOn/RNOn data delay from RCOn↑

t

OD

TXC-04011-MB

Ed. 1, September 1995

- 18 -

ADMA-T1P

TXC-04011

PRELIMINARY

Figure 6. STS-1 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus

t_CYC

t_PWH

A/BDCLK

(INPUT)

t_SU(1)

A2

t_H(1)

A/BD(7-0)

(INPUT)

A1

C1

1

2

3

J1

t_SU(2)

t_H(2)

A/BDSPE

(INPUT)

t_SU(1)

t_H(1)

A/BDC1J1

(INPUT)

J1

t_OD(3)

t_OD(2)

A/BA(7-0)

(OUTPUT)

3

t_OD(1)

A/BADD

(OUTPUT)

Note: The add bus output A/BA(7-0) shown above corresponds to the 0 state of control bit ABD, when there is one data

byte (or one clock cycle) of delay between the drop and add buses. This delay is increased to two data bytes when

control bit ABD is set to 1.

Parameter

Symbol

Min

Typ

Max

Unit

A/BDCLK drop clock period

t

154.32

50

ns

%

CYC

A/BDCLK drop clock duty cycle, t

t

40

60

PWH/ CYC

A/BD(7-0) drop data and A/BDC1J1 set-up time

t

4.0

ns

SU(1)

before A/BDCLK↓

A/BD(7-0) drop data and A/BDC1J1 hold time

t

5.0

ns

H(1)

after A/BDCLK↓

A/BDSPE set-up time before A/BDCLK↓

A/BDSPE hold time after A/BDCLK↓

t

4.0

5.0

6.0

ns

SU(2)

t

H(2)

A/BA(7-0) add data out (from tri-state) delay

from A/BDCLK↑

t

18.5

20.0

19.0

OD(2)

OD(3)

OD(1)

A/BA(7-0) add data out (to tri-state) delay

from A/BDCLK ↑

6.0

ns

A/BADD add indicator delay from A/BDCLK↑

TXC-04011-MB

Ed. 1, September 1995

- 19 -

ADMA-T1P

TXC-04011

PRELIMINARY

Figure 7. STS-3/STM-1 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus

t_CYC

t_PWH

A/BDCLK

(INPUT)

t_SU(1)

C1(2)

t_H(1)

A/BD(7-0)

(INPUT)

C1(1)

C1(3)

t_SU(2)

1

2

3

J1

FIXED STUFF FIXED STUFF

t_H(2)

A/BDSPE

(INPUT)

t_SU(1)

t_H(1)

A/BDC1J1

(INPUT)

C1(1)

J1

t_OD(3)

t_OD(2)

A/BA(7-0)

(OUTPUT)

3

t_OD(1)

A/BADD

(OUTPUT)

Note: The add bus output A/BA(7-0) shown above corresponds to the 0 state of control bit ABD, when there is one data

byte (or one clock cycle) of delay between the drop and add buses. This delay is increased to two data bytes when

control bit ABD is set to 1.

Parameter

Symbol

Min

Typ

Max

Unit

A/BDCLK drop clock period

t

51.44

50

ns

%

CYC

A/BDCLK drop clock duty cycle, t

/t

-

45

55

PWH CYC

A/BD(7-0) drop data and A/BDC1J1 set-up time

t

4.0

ns

SU(1)

before A/BDCLK↓

A/BD(7-0) drop data and A/BDC1J1 hold time

t

5.0

ns

H(1)

after A/BDCLK↓

A/BDSPE set-up time before A/BDCLK↓

A/BDSPE hold time after A/BDCLK↓

t

4.0

5.0

6.0

ns

SU(2)

t

H(2)

A/BA(7-0) add data out (from tri-state) delay

from A/BDCLK↑

t

18.3

19.8

18.8

OD(2)

OD(3)

OD(1)

A/BA(7-0) add data out (to tri-state) delay from

A/BDCLK↑

6.0

ns

A/BADD add indicator delay from A/BDCLK↑

TXC-04011-MB

Ed. 1, September 1995

- 20 -

ADMA-T1P

TXC-04011

PRELIMINARY

Figure 8. STS-1 A/B Add Bus Signals, Timing Derived from Add Bus

t_CYC

t_PWH

A/BACLK

(INPUT)

t_SU(2)

t_H(2)

A/BASPE

(INPUT)

t_SU(1)

t_H(1)

A/BAC1J1V1

(INPUT)

J1

C1

V1

t_OD(3)

t_OD(2)

A/BA(7-0)

(OUTPUT)

t_OD(1)

A/BADD

(OUTPUT)

Note: The add bus output A/BA(7-0) shown above corresponds to the 0 state of control bit ABD, when there is one data

byte (or one clock cycle) of delay between the drop and add buses. This delay is increased to two data bytes when

control bit ABD is set to 1.

Parameter

Symbol

Min

Typ

Max

Unit

A/BACLK drop clock period

t

154.32

50

ns

%

CYC

A/BACLK duty cycle, t

/t

40

4.0

5.0

4.0

5.0

6.0

60

PWH CYC

A/BAC1J1V1 set-up time to A/BACLK↓

A/BAC1J1V1 hold time after A/BACLK↓

A/BASPE set-up time to A/BACLK↓

A/BASPE hold time after A/BACLK↓

t

ns

SU(1)

t

H(1)

SU(2)

t

H(2)

A/BA(7-0) data out (from tristate) delay

from A/BACLK↑

t

18.5

20.0

19.0

OD(2)

OD(3)

OD(1)

A/BA(7-0) data to tristate delay from

A/BACLK↑

6.0

ns

A/BADD add indicator delay from

A/BACLK↑

TXC-04011-MB

Ed. 1, September 1995

- 21 -

ADMA-T1P

TXC-04011

PRELIMINARY

Figure 9. STS-3/STM-1 A/B Add Bus Signals, Timing Derived from Add Bus

t_CYC

t_PWH

A/BACLK

(INPUT)

t_SU(2)

t_H(2)

A/BASPE

(INPUT)

t_SU(1)

t_H(1)

A/BAC1J1V1

(INPUT)

C1(1)

J1

V1

t_OD(3)

t_OD(2)

A/BA(7-0)

(OUTPUT)

t_OD(1)

A/BADD

(OUTPUT)

Note: The add bus output A/BA(7-0) shown above corresponds to the 0 state of control bit ABD, when there is one data

byte (or one clock cycle) of delay between the drop and add buses. This delay is increased to two data bytes when

control bit ABD is set to 1.

Parameter

Symbol

Min

Typ

Max

Unit

A/BACLK drop clock period

t

51.44

50

ns

%

CYC

A/BACLK duty cycle, t

/t

40

4.0

5.0

4.0

5.0

6.0

60

PWH CYC

A/BAC1J1V1 set-up time to A/BACLK ↓

A/BAC1J1V1 hold time after A/BACLK ↓

A/BASPE set-up time to A/BACLK ↓

A/BASPE hold time after A/BACLK ↓

t

ns

SU(1)

t

H(1)

SU(2)

t

H(2)

A/BA(7-0) data out (from tristate) delay

from A/BACLK ↑

t

18.5

20.0

19.0

OD(2)

OD(3)

OD(1)

A/BA(7-0) data to tristate delay from

A/BACLK ↑

6.0

ns

A/BADD add indicator delay from

A/BACLK ↑

TXC-04011-MB

Ed. 1, September 1995

- 22 -

ADMA-T1P

TXC-04011

PRELIMINARY

Figure 10. Microprocessor Read Cycle - Intel Timing

PW(1)

t

W(1)

ALE

UPAD/D (0-7)

SEL

t

OD(1)

SU(1)

H(1)

H(2)

Address

Data

t

OD(2)

t

H(3)

SU(2)

t

PW(2)

W(2)

RD

Parameter

Symbol

Min

Typ

Max

Unit

ALE pulse width

t

20.0

5.0

ns

PW(1)

UPAD(0-7) address set-up time before ALE↓

UPAD(0-7) address hold time after ALE↓

UPAD(0-7) address hold time after RD↓

D(0-7) data available delay time after RD↓

D(0-7) data delay time to tri-state after RD↑

ALE wait after RD↑

t

SU(1)

t

3.0

H(1)

H(2)

0.0

17.0

8.0

t

5.0

2.0

OD(2)

OD(1)

t

0.0

W(1)

SEL set-up time before RD↓

t

0.0

SU(2)

SEL hold time after RD↑

t

0.0

H(3)

RD wait after ALE ↓

t

20.0

45.0

W(2)

RD pulse width

t

PW(2)

TXC-04011-MB

Ed. 1, September 1995

- 23 -

ADMA-T1P

TXC-04011

PRELIMINARY

Figure 11. Microprocessor Write Cycle - Intel Timing

t

PW(1)

t

W(1)

ALE

UPAD/D (0-7)

SEL

t

H(1)

H(2)

SU(1)

Address

Data

t

H(3)

SU(3)

t

PW(2)

W(2)

WR

Parameter

Symbol

Min

Typ

Max

Unit

ALE pulse width

ALE wait after WR↑

t

20.0

0.0

ns

PW(1)

t

W(1)

UPAD(0-7) address set-up time before ALE↓

UPAD(0-7) address hold time after ALE↓

D(0-7) data input hold time after WR↑

SEL set-up time before WR↓

SEL hold time after WR↑

t

5.0

SU(1)

t

3.0

H(1)

H(2)

16.0

0.0

t

SU(3)

t

0.0

H(3)

WR wait after ALE↓

t

20.0

45.0

W(2)

WR pulse width

t

PW(2)

TXC-04011-MB

Ed. 1, September 1995

- 24 -

ADMA-T1P

TXC-04011

PRELIMINARY

MEMORY MAP

The ADMA-T1P memory map consists of counters and register bit positions which may be accessed by the

microprocessor. Addresses which are shown as TranSwitch test registers or as wholly ‘Unused’ bytes in the

memory map must not be accessed by the microprocessor. No value is speciﬁed for the content to be read

from an ‘Unused’ bit position when the address which contains it is selected for a read cycle, but the bit posi-

tion should be written as 0 when the address is selected for a write cycle (if it is a R/W or W address).

COMMON CONTROL

Address

Status*

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Hex)

00

01

02

03

40

41

42

43

44

W

RESET

T1SEL1

MOD1

RESETS RESETC

Unused

R/W

T1SEL0

MOD0

UQAE

BAHZE

NPIA

BYPAS1

T1B8ZS

R1AIS

ADDI

BYPAS2

T2B8ZS

R2AIS

ABD

T1LOOP T2LOOP

R1EN

Unused

T2SEL0

R2EN

TCLKI

T1AIS

RDIEN

APE

T2AIS

TAISE

T2SEL1

RCLKI

PTALTE

Unused

AAHZE

Unused

PDDO

NPIB

NPIC

E1AISD

DPE

TranSwitch Test Register

* R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write only.

A-SIDE DROP BUS STATUS REGISTERS

Address

Status*

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Hex)

04

05

06

07

R(L)

R

ADLOC

Unused

AALOC

Unused

A2DH4E

A1DH4E ADPAR

Unused

R

PORT 1 STATUS/TRANSMIT REGISTERS

Address

Status*

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Hex)

08

09

0A

0B

0C

0D

0E

0F

R/W

R

Port 1 Pointer Leak Rate

Port 1 B8ZS/AMI Coding Errors (low order byte)

Unused R1FFE

R(L)

R

T1LOCS

T1AIS

Port 1 B8ZS/AMI Coding Errors (high order byte)

Unused

R

R/W

T1VTAIS

R1SEL

T1FB2

T1FFB

T1RDI

Port 1 TX O-Bits

VTN1 (VT#)

T1RFI

A1 TX Label

TXC-04011-MB

Ed. 1, September 1995

- 25 -

ADMA-T1P

TXC-04011

PRELIMINARY

PORT 1 A-SIDE DROP BUS RECEIVE REGISTERS

Address

Status*

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Hex)

10

11

12

13

14

15

16

17

R

A1BIP2 Error Count

A1FEBE Count

R(L)

R

A1UNEQ

A1AIS

A1SLER

A1LOP

Unused

A1NDF

A1RFI

Unused

A1 RX Label

A1NJ Counter

TA1FE

A1SIZE

A1RDI

A1PJ Counter

R

A1 RX O-Bits

R/W

Unused

A1UPSL

TranSwitch Test Register

PORT 1 B-SIDE DROP BUS RECEIVE REGISTERS

Address

Status*

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Hex)

18

19

1A

1B

1C

1D

1E

1F

R

B1BIP2 Error Count

B1FEBE Count

R(L)

R

B1UNEQ

B1AIS

B1SLER

B1LOP

Unused

B1NDF

B1RFI

Unused

B1 RX Label

B1NJ Counter

TB1FE

B1SIZE

B1RDI

B1PJ Counter

R

B1 RX O-Bits

R/W

Unused

B1UPSL

TranSwitch Test Register

B-SIDE DROP BUS STATUS REGISTERS

Address

Status*

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Hex)

24

25

26

27

R(L)

BDLOC

Unused

BALOC

Unused

B2DH4E

B1DH4E BDPAR

Unused

TXC-04011-MB

Ed. 1, September 1995

- 26 -

ADMA-T1P

TXC-04011

PRELIMINARY

PORT 2 STATUS/TRANSMIT REGISTERS

Address

Status*

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Hex)

28

29

2A

2B

2C

2D

2E

2F

R/W

R

Port 2 Pointer Leak Rate

Port 2 B8ZS/AMI Coding Errors (low order byte)

Unused R2FFE

R(L)

R

T2LOCS

T2AIS

Port 2 B8ZS/AMI Coding Errors (high order byte)

Unused

R/W

T2VTAIS

R2SEL

T2FB2

T2FFB

T2RDI

Port 2 TX O-Bits

VTN2 (VT#)

T2RFI

A2 TX Label

PORT 2 A-SIDE DROP BUS RECEIVE REGISTERS

Address

Status*

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Hex)

30

31

32

33

34

35

36

37

R

A2BIP2 Error Count

A2FEBE Count

R(L)

R

A2UNEQ

A2AIS

A2SLER

A2LOP

Unused

A2NDF

A2RFI

Unused

A2 RX Label

A2NJ Counter

TA2FE

A2SIZE

A2RDI

A2PJ Counter

R

A2 RX O-Bits

R/W

R

Unused

A2UPSL

TranSwitch Test Register

PORT 2 B-SIDE DROP BUS RECEIVE REGISTERS

Address

Status*

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Hex)

38

39

3A

3B

3C

3D

3E

3F

R

B2BIP2 Error Count

B2FEBE Count

R(L)

R

B2UNEQ

B2AIS

B2SLER

B2LOP

Unused

B2NDF

B2RFI

Unused

B2 RX Label

B2NJ Counter

TB2FE

B2SIZE

B2RDI

B2PJ Counter

R

B2 RX O-Bits

R/W

Unused

B2UPSL

TranSwitch Test Register

TXC-04011-MB

Ed. 1, September 1995

- 27 -

ADMA-T1P

TXC-04011

PRELIMINARY

MEMORY MAP DESCRIPTIONS

CONTROL REGISTERS

Address

Bit

Symbol

Description

00

7

RESET

Reset ADMA-T1P: A 1 conﬁgures the controls to their power-up states,

resets all the performance counters to 0, and re-centers the internal

FIFOs. Afterwards this bit is self-clearing and resets to a 0.

Note: Upon power-up all control bits, except the BPASn, MODn, AAHZE,

and BAHZE, are reset to 0 (where n represents port 1 or 2). Upon power-

up, all alarms, except AnLOP and BnLOP, are reset to 0. The MODn con-

trol bits select the STS-3 format, while the BPASn, AAHZE, BAHZE,

AnLOP, and BnLOP control bits are set to 1.

6

5

RESETS Reset Selected Functions: A 1 resets the performance counters and

alarms to 0, and re-centers the internal FIFOs. The control register bits are

not reset, and will maintain their existing states. Afterwards this bit is self-

clearing and resets to a 0. See Note 1.

RESETC Reset Counters: A 1 causes all the performance counters to reset to 0.

Afterwards this bit is self-clearing and resets to a 0. See Note 1.

01

7

6

T1SEL1

T1SEL0

Port 1 Transmit A/B-side Add Bus Selection: This bit works in conjunc-

tion with the R1SEL bit to provide the following modes of operation for port

1. Timing for the VT/TU to be added to the A (or B) Add bus is derived from

either the A (or B) Drop bus.

T1SEL1 T1SEL0 R1SEL

Mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A-side drop only

B-side drop only

A-side drop, A-side add

B-side drop, B-side add

A-side drop, B-side add

B-side drop, A-side add

A-side drop, A-side and B-side add

B-side drop, B-side and A-side add

5

4

3

BYPAS1

BYPAS2

Bypass CODEC Port 1: A 1 arranges the B8ZS/AMI CODEC for port 1 to

be bypassed for NRZ operation. A 0 enables the CODEC for port 1.

Bypass CODEC Port 2: A 1 arranges the B8ZS/AMI CODEC for port 2 to

be bypassed for NRZ operation. A 0 enables the CODEC for port 2.

T1LOOP Port 1 T1 Loopback: A 1 causes a T1 loopback for port 1. The receive

output data and clock signals are looped back as the transmit input, and

the receive data signals are provided as an output. The input signal from

the line is disabled.

Add

Bus

TX

RX

SONET

Port n

Drop

Bus

Note 1: This bit position should be written to 1 after device initialization and after any mode changes (i.e., after changing

any of the T1SEL1, T1SEL0, T2SEL1, T2SEL0, R1SEL, VTN1, R2SEL or VTN2 bits) in order to prevent a FIFO

error from occurring.

TXC-04011-MB

Ed. 1, September 1995

- 28 -

ADMA-T1P

TXC-04011

PRELIMINARY

Address

Bit

Symbol

Description

01

(cont.)

2

T2LOOP Port 2 T1 Loopback: A 1 causes a T1 loopback for port 2. The receive

output data and clock signals are looped back as the transmit input, and

the receive data signals are provided as an output. The input signal from

the line is disabled.

1

0

R1EN

Receive Port 1 Enable: A 1 enables the receive data (NRZ or rail) output

and clock output for port 1. A 0 forces the data and clock output leads to a

high impedance state.

R2EN

Receive Port 2 Enable: A 1 enables the receive data (NRZ or rail) output

and clock output for port 2. A 0 forces the data and clock output leads to a

high impedance state.

02

7

6

MOD1

MOD0

SONET/SDH Bus Format Selection: The SONET/SDH bus format selec-

tion is according to the table below:

MOD1

MOD0

Bus Format Selected

STS-1 format

STS-3 format

STM-1 AU3 format

STM-1 TUG-3/VC-4 format

0

1

0

1

0

1

5

4

3

2

0

T1B8ZS

T2B8ZS

T1AIS

Port 1 B8ZS CODEC Enable: A 1 selects the B8ZS CODEC function for

port 1. A 0 selects the AMI CODEC function for port 1.

Port 2 B8ZS CODEC Enable: A 1 selects the B8ZS CODEC function for

port 2. A 0 selects the AMI CODEC function for port 2.

Port 1 Transmit AIS: A 1 causes a T1 AIS (unframed all ones signal) to

be generated in the transmit (add) direction for port 1.

T2AIS

Port 2 Transmit AIS: A 1 causes a T1 AIS (unframed all ones signal) to

be generated in the transmit (add) direction for port 2.

TCLKI

Port 1 and 2 Transmit Clock Inversion: A 1 causes the T1 data for ports

1 and 2 to be clocked in on positive clock edges. A 0 causes data to be

clocked in on negative clock edges.

03

7

6

TAISE

UQAE

Port 1 and 2 Transmit AIS Enable: A 1 enables a T1 AIS to be sent when

loss of signal or clock is detected in the port 1 or port 2 T1 interface sig-

nals. A T1 AIS is an unframed all ones data signal.

Unequipped Alarm AIS Enable: A 1 enables receive AIS and RDI to be

sent when an unequipped status is detected in either the A-side or B-side

drop data. An unequipped status is deﬁned as 000 in the VT/TU signal

label.

TXC-04011-MB

Ed. 1, September 1995

- 29 -

ADMA-T1P

TXC-04011

PRELIMINARY

Address

Bit

Symbol

Description

03

(cont.)

5

R1AIS

Generate Receive AIS for Port 1: A 1 causes a T1 AIS to be generated

for the receive data for port 1, independent of internal alarm detection. A

T1 AIS is an unframed all ones data signal. The conditions for generating a

T1 AIS for port 1 are:

When control bit R1SEL is a 0 and any one or more of the following:

- R1AIS=1.

- Loss of Pointer (A1LOP).

- VT/TU AIS (A1AIS).

- A-side drop bus loss of clock (ADLOC).

- A-side H4 Error (A1DH4E).

- Unequipped signal label (A1UNEQ), and UQAE is a 1.

- Mismatch signal label (A1SLER).

- VT/TU selection out of range or equal to 0.

When control bit R1SEL is a 1 and any one or more of the following:

- R1AIS=1.

- Loss of Pointer (B1LOP).

- VT/TU AIS (B1AIS).

- B-side drop bus loss of clock (BDLOC).

- B-side H4 Error (B1DH4E).

- Unequipped signal label (B1UNEQ), and UQAE is a 1.

- Mismatch signal label (B1SLER).

- VT/TU selection out of range or equal to 0.

Microprocessor writes a 1 to R1AIS.

4

R2AIS

Generate Receive AIS for Port 2: A 1 causes a T1 AIS to be generated

for the receive data for port 2, independent of internal alarm detection. A

T1 AIS is an unframed all ones data signal. The conditions for generating a

T1 AIS for port 2 are:

When control bit R2SEL is a 0 and any one or more of the following:

- R2AIS=1.

- Loss of Pointer (A2LOP).

- VT/TU AIS (A2AIS).

- A-side drop bus loss of clock (ADLOC).

- A-side H4 Error (A2DH4E).

- Unequipped signal label (A2UNEQ), and UQAE is a 1.

- Mismatch signal label (A2SLER).

- VT/TU selection out of range or equal to 0.

When control bit R2SEL is a 1 and any one or more of the following:

- R2AIS=1.

- Loss of Pointer (B2LOP).

- VT/TU AIS (B2AIS).

- B-side drop bus loss of clock (BDLOC).

- B-side H4 Error (B2DH4E).

- Unequipped signal label (B2UNEQ), and UQAE is a 1.

- Mismatch signal label (B2SLER).

- VT/TU selection out of range or equal to 0.

Microprocessor writes a 1 to R2AIS.

TXC-04011-MB

Ed. 1, September 1995

- 30 -

ADMA-T1P

TXC-04011

PRELIMINARY

Address

Bit

Symbol

Description

03

(cont.)

3

RDIEN

Transmit Receive Defect Indication Enable: A 1 enables the ADMA-T1P

to send RDI when a receive alarm occurs. A 0 disables the automatic

insertion, and allows the microprocessor to control both states of the trans-

mitted RDI status bit (Bit 8 in V5). For port 1 the alarms causing RDI are a

function of the R1SEL, T1SEL1 and T1SEL0 control bits. For port 2 the

alarms causing RDI are a function of the R2SEL, T2SEL1 and T2SEL0

control bits. The following is a summary of the various alarms and control

bits that may cause an RDI. The n represents port 1 or 2.

When RDIEN is a 1:

- Loss Of Pointer (AnLOP, BnLOP).

- VT/TU AIS (AnAIS, BnAIS).

- A/B-side drop bus H4 Error (AnDH4E, BnDH4E).

- Unequipped signal label (AnUNEQ, BnUNEQ), and UQAE is a 1.

- Signal label mismatch (AnSLER, BnSLER).

When RDIEN is a 0:

- Microprocessor writes a 1 to TnRDI.

Note. The microprocessor may send an RDI anytime by writing a 1 to

TnRDI. However, to prevent contention between the internal alarms caus-

ing RDI and microprocessor controlling RDI, control bit RDIEN must be

written with a 0.

2

1

T2SEL1

T2SEL0

Port 2 Transmit A/B-side Add Bus Selection: This bit works in conjunc-

tion with the R2SEL bit to provide the following modes of operation for port

2. Timing for the VT/TU to be added to the A (or B) Add bus is derived from

either the A (or B) Drop bus.

T2SEL1 T2SEL0 R2SEL

Mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A-side drop only

B-side drop only

A-side drop, A-side add

B-side drop, B-side add

A-side drop, B-side add

B-side drop, A-side add

A-side drop, A-side and B-side add

B side drop, B-side and A-side add

0

RCLKI

Port 1 and 2 Receive Clock Inversion: A 1 causes the receive clock to

clock out data on the negative edge instead of on the positive edge for

both ports.

TXC-04011-MB

Ed. 1, September 1995

- 31 -

ADMA-T1P

TXC-04011

PRELIMINARY

Address

Bit

Symbol

Description

40

7

AAHZE

A-side Add Bus High Impedance Enable: A 1 forces the A-side add bus

output signals to a high impedance state. A 0 allows normal operation.

6

5

BAHZE

ADDI

B-side Add Bus High Impedance Enable: A 1 forces the B-side add bus

outputs signals to a high impedance state. A 0 allows normal operation.

Add Indicator Inversion: A 1 enables the A and B-side add indicator sig-

nals to be active high instead of active low. A 0 enables the A and B-side

add indicator signals to be active low instead of active high.

4

ABD

Add Bus Delayed: A 1 causes the add bus data to be delayed by two

clock cycles with respect to the drop bus data. A 0 causes the add bus

data to be delayed by one clock cycle with respect to the drop bus data.

3

0

APE

A/B-side Add Bus Even Parity Generated: A 1 enables even parity to be

generated, while 0 enables odd parity to be generated.

PTALTE

Pointer Tracking AIS to LOP Transition Enabled: A 1 enables the AIS to

LOP transition in the pointer tracking state machine, as required per ITU-T

requirements. A 0 disables the transition as required per Bellcore stan-

dards.

41

6

5

4

NPIA

NPIB

NPIC

Null Pointer Indicator Selection: A 1 enables the null pointer indicator to

be generated for one or more of the TUG-3s when the STM-1 TUG-3 for-

mat is selected. A null pointer indicator is deﬁned as a 1001 in bits 1-4, bits

5 and 6 are unspeciﬁed and set to 0, ﬁve 1s in bits 7-11, followed by ﬁve

zeros in bits 12-16 (two bytes). Those bytes which are designated as stuff

are not generated, and the data bus is forced to a high impedance state

during those time slots.

3

2

1

E1AISD

DPE

Receive E1 Byte AIS Disable: A 1 disables the add/drop bus TOH E1

byte from generating a T1 AIS for ports 1 and 2 when the E1 byte is all

ones.

A/B-side Drop Bus Even Parity Detected: A 1 enables even parity to be

detected in the A/B-side drop buses. A 0 enables odd parity to be

detected.

PDDO

A/B-side Drop Bus Parity Detected on Data Only: A 1 causes parity to

be detected for the data byte only. A 0 causes parity to be detected for the

data byte, C1J1 and the SPE signals.

TXC-04011-MB

Ed. 1, September 1995

- 32 -

ADMA-T1P

TXC-04011

PRELIMINARY

A-SIDE DROP BUS STATUS REGISTERS

Address

Bit

Symbol

Description

04

7

ADLOC

A-side Drop Bus Loss Of Clock: A latched bit position that indicates a

loss of clock in the A-side drop bus has been detected. A loss of clock

alarm causes a receive AIS for the duration of the alarm, and sets the like-

named add bus signals (data and PAR signal) to the high impedance state.

The AADD indication signal becomes inactive for the duration of the alarm.

This bit position is cleared on a microprocessor read cycle. If the alarm is

active, this bit position will re-latch. The loss of clock alarm occurs when

the input drop clock (ADCLK) is stuck high or low for 10 or more clock

cycles. Recovery occurs on the first drop clock transition.

5

AALOC

A Add Bus Loss Of Clock: A latched bit position which indicates that the

A Add bus has detected a loss of clock, when control lead ABUST is low. A

loss of clock alarm causes the add data and parity bit to 3-state, and sets

the add indicator off for the duration of the alarm. This bit position is

cleared on a microprocessor read cycle. If the alarm is active, this bit posi-

tion will re-latch. The loss of clock alarm occurs when the input add clock

(AACLK) is stuck high or low for 10 or more clock cycles. Recovery occurs

on the first add clock transition.

2

1

0

A2DH4E

A1DH4E

ADPAR

A-side Drop Bus Port 2 Loss of H4 Indication: A latched bit position that

indicates that the anticipated received H4 multiframe sequence of 00, 01,

10, 11 has not been received properly. The ADMA-T1P will continue to

operate in a free running mode, but will lock to a new H4 sequence after

two consecutive sequences have been received properly. This bit position

is cleared on a microprocessor read cycle. If the alarm is active, this bit

position will re-latch.

A-side Drop Bus Port 1 Loss of H4 Indication: A latched bit position

which indicates that the anticipated received H4 multiframe sequence of

00, 01, 10, 11 has not been received properly. The ADMA-T1P will con-

tinue to operate in a free running mode, but will lock to a new H4 sequence

after two consecutive sequences have been received properly. This bit

position is cleared on a microprocessor read cycle. If the alarm is active,

this bit position will re-latch.

A-side Drop Bus Parity Error Detected: A latched bit position which indi-

cates that an odd parity error has been detected in the A-side drop bus sig-

nals. Even parity detection is enabled by writing a 1 to the Drop Bus Parity

Even (DPE) control bit. Other than an alarm indication, no other action is

taken. This bit position is cleared on a microprocessor read cycle. If the

alarm is active, this bit position will re-latch.

TXC-04011-MB

Ed. 1, September 1995

- 33 -

ADMA-T1P

TXC-04011

PRELIMINARY

PORT 1 STATUS/TRANSMIT REGISTERS

Address

Bit

Symbol

Description

Port 1

Pointer

Leak

Rate

Value

08

7-0

Port 1 FIFO Leak Rate Register: The count written into this location is

used for the internal leak buffer, and represents the average leak rate. A

count of one represents 8 frames, or 2 multiframes, in the rate of occur-

rence of pointer movements from the number of counts read from positive/

negative stuff counters. A count of 0 is invalid, and no selection takes

place.

09

0A

7-0

Port 1

Coding

Error

Port 1 Transmit Coding Violation Counter: Low order byte of a 16-bit

saturating counter that counts the number of coding errors that have

occurred in the AMI or B8ZS line codes. During a read cycle internal logic

holds a count of 1 until the read cycle is complete, and then updates the

Counter

Low Order counter. This counter is cleared on a reset pulse, when a 1 is written to the

Byte

reset counter control bit (RESETC), or by a read cycle. This location must

be read ﬁrst before the high order byte.

2

1

R1FFE

Port 1 Receive FIFO Error: A latched bit position which indicates that the

receive FIFO for port 1 has overflowed or underflowed. The FIFO will reset

automatically. Other than an alarm indication, no other action will be taken.

This bit position is cleared on a microprocessor read cycle. If the alarm is

active, this bit position re-latches.

T1LOCS

Port 1 Transmit Loss Of T1 Clock or Signal: A latched bit position which

indicates that the Port 1 T1 clock or data signal has failed. This bit position

is cleared on a microprocessor read cycle, but if either of the alarms is

then active this bit position re-latches. Loss of clock occurs when the T1

input clock (TCI1) is stuck high or low for 10 or more clock cycles. Recov-

ery occurs on the first T1 input clock transition. Loss of signal for the rail

interface occurs when no TPI1 signal transitions occur in a period of 175 ±

75 consecutive pulse positions. Recovery occurs when there is an average

pulse density of at least 12.5% over a period of 175 ± 75 contiguous pulse

positions starting with the receipt of a detected pulse.

0

T1AIS

Port 1 Transmit AIS Detected: A latched bit position which indicates that

a T1 AIS (unframed all ones) has been detected in the Port 1 data. This bit

position is cleared on a microprocessor read cycle. If the alarm is active,

this bit position re-latches.

0B

7-0

Port 1

Coding

Error

Port 1 Transmit Coding Violation Counter: High order byte of a 16-bit

saturating counter which counts the number of coding errors that have

occurred in the AMI or B8ZS line codes. This counter is cleared on a reset

pulse, when a 1 is written to the reset counter control bit (RESETC), or by

Counter

High Order a read cycle.

Byte

TXC-04011-MB

Ed. 1, September 1995

- 34 -

ADMA-T1P

TXC-04011

PRELIMINARY

Address

Bit

Symbol

Description

0D

7

T1VTAIS Port 1 Transmit VT/TU AIS: A 1 causes a VT/TU AIS to be generated and

transmitted. A VT/TU AIS consists of all ones in the entire VT, including

bytes V1 through V4.

6

T1FB2

Port 1 Transmit BIP-2 Error Mask (Force BIP-2 Error): A 1 causes bits 1

and 2 (BIP-2 value) in the transmitted V5 byte to be sent inverted from the

calculated value continuously.

5

4

T1FFB

T1RDI

T1RFI

Port 1 Transmit Force FEBE Error: A 1 causes bit 3 (FEBE) in the V5

byte to be transmitted inverted from its normally transmitted value.

Port 1 Transmit Remote Defect Indication (Yellow/FERF): A 1 causes

an RDI alarm to be transmitted (Bit 8 in V5 = 1).

3

Port 1 Transmit Remote Failure Indication: A 1 causes an RFI alarm to

be transmitted (Bit 4 in V5 = 1).

2-0

A1 TX

Label

Port 1 Transmit Signal Label: The three bit positions written by the pro-

cessor correspond to bits 5 through 7 in the V5 byte. Bit 2 corresponds to

bit 7 in the V5 byte.

0E

0F

7-0

Port 1

Transmit

O-bits

Port 1Transmit Overhead Communication Channel Bits: Bits 3-0 corre-

spond to bits 3-6 in the ﬁrst justiﬁcation control byte, while bits 7-4 corre-

spond to bits 3-6 in the second justiﬁcation control byte in the VT/TU

format.

7

R1SEL

VTN1

Port 1 Receive A or B-side VT/TU Bus Selection: Determines the drop

bus VT/TU selection. A 1 selects the B-side drop bus, and a 0 selects the

A-side drop bus.

6-0

Port 1 VT/TU Selection: Works in conjunction with the R1SEL control bit.

The seven bit binary code written into this location selects the VT or TU

that is to be dropped from the A or B-side drop bus. The binary value of 0

and a value above the range will not select a VT or TU. For example, the

VT selection in an STS-3 format is given below:

Bit 6 5 4 3 2 1 0 STS-3 Mapping

0 0 0 0 0 0 0 No VT# selected, AIS generated

0 0 0 0 0 0 1 STS-1#1, GP#1, VT#1 selected

0 0 1 1 1 0 1 STS-1#2, GP#1, VT#1 selected

0 1 1 1 0 0 1 STS-1#3, GP#1, VT#1 selected

- - - - - - -

1 0 1 0 1 0 0 STS-1#3, GP#7, VT#4 selected

1 0 1 0 1 0 1 No VT# selected, AIS generated

- - - - - - -

1 1 1 1 1 1 1 No VT# selected, AIS generated

Note: AIS may be over-written by writing a 0 to R1EN which will 3-state the

port 1 data and clock output leads.

TXC-04011-MB

Ed. 1, September 1995

- 35 -

ADMA-T1P

TXC-04011

PRELIMINARY

PORT 1 A-SIDE DROP BUS RECEIVE REGISTERS

Address

Bit

Symbol

Description

10

7-0

A1BIP2

Count

Port 1 A-side Drop Bus BIP-2 Counter: An 8-bit saturating counter which

counts the number of BIP-2 errors detected in the receive direction. A

maximum of two errors can be detected each frame. During a read cycle

internal logic holds an incoming error count until the read cycle is com-

plete, and then updates the counter. This counter is cleared on a reset

pulse, when a 1 is written to the reset counter control bit (RESETC), or by

a read cycle.

11

12

7-0

A1FEBE

Count

Port 1 A-side Drop Bus FEBE Counter: An 8-bit saturating counter

which counts the number of FEBE errors received (Bit 3 in V5 = 1). During

a read cycle internal logic holds an incoming error count until the read

cycle is complete, and then updates the counter. This counter is cleared

on a reset pulse, when a 1 is written to the reset counter control bit

(RESETC), or by a read cycle.

7

6

A1UNEQ Port 1 A-side Drop Bus Unequipped Indication: A latched bit position

which indicates an Unequipped status has been detected in the V5 signal

label bits (Bits 5-7 in V5 = 0). This bit position is cleared on a microproces-

sor read cycle. If the alarm is active, this bit position will re-latch.

A1SLER

A1NDF

TA1FE

Port 1 A-side Drop Bus Signal Label Mismatch Indication: A latched bit

position which indicates that the receive signal label bits (Bits 5-7 in V5)

did not match the microprocessor-written signal label. This bit position is

cleared on a microprocessor read cycle. If the alarm is active, this bit posi-

tion re-latches.

3

0

Port 1 A-side Drop Bus New Data Flag Indication: A latched bit position

which indicates a New Data Flag (1001) has been detected in the V1

pointer byte (Bits 1-4 in V1 are the inverse of the 0110). This bit position is

cleared on a microprocessor read cycle. If the alarm is active, this bit posi-

tion re-latches.

Port 1 Transmit A-side Add Bus FIFO Error: A latched bit position which

indicates that the A-side add bus FIFO has overﬂowed or underﬂowed.

The FIFO resets automatically. This bit position is cleared on a micropro-

cessor read cycle. If the alarm is active, this bit position re-latches.

TXC-04011-MB

Ed. 1, September 1995

- 36 -

ADMA-T1P

TXC-04011

PRELIMINARY

Address

Bit

Symbol

Description

13

7

A1AIS

Port 1 A-side Drop Bus VT AIS Alarm: A latched bit position which indi-

cates a VT (TU) AIS has been detected. This bit position is cleared on a

microprocessor read cycle. If the alarm is active, this bit position will re-

latch.

6

5

A1LOP

A1SIZE

Port 1 A-side Drop Bus Loss Of Pointer Alarm: A latched bit position

which indicates a loss of pointer has been detected. This bit position is

cleared on a microprocessor read cycle. If the alarm is active, this bit posi-

tion will re-latch.

Port 1 A-side Drop Bus Pointer Size Error Indication: A latched bit

position which indicates that the receive size indicator in the pointer (Bits 5

and 6 in the V1 pointer byte) does not = 11. This bit position is cleared on a

microprocessor read cycle. If the alarm is active, this bit position will re-

latch.

4

3

A1RDI

A1RFI

Port 1 A-side Drop Bus Remote Defect Indication (FERF): A latched bit

position which indicates an RDI (FERF/Yellow) alarm has been detected

(Bit 8 in V5 = 1). This bit position is cleared on a microprocessor read

cycle. If the alarm is active, this bit position will re-latch.

Port 1 A-side Drop Bus Remote Failure Indication: A latched bit posi-

tion which indicates an RFI alarm has been detected (Bit 4 in V5 = 1). This

bit position is cleared on a microprocessor read cycle. If the alarm is

active, this bit position will re-latch.

2-0

A1 RX

Label

Port 1 A-side Drop Bus Received Signal Label: The three bit positions

correspond to the three signal label bits found in bits 5 through 7 in V5.

These bits are updated each V5 time. Bit 2 corresponds to bit 7 in the V5

byte. These bits are also compared against the microprocessor-written

mismatch signal label bits for a mismatch indication.

14

7-4

3-0

7-0

2-0

A1PJ

Count

Port 1 A-side Drop Bus Positive Pointer Justiﬁcation Counter: A four

bit counter that increments on a positive pointer movement. During a read

cycle internal logic holds the count until the read cycle is complete, and

then updates the counter. This counter is cleared on a reset pulse, when a

1 is written to the reset counter control bit (RESETC), or by a read cycle.

A1NJ

Count

Port 1 A-side Drop Bus Negative Pointer Justiﬁcation Counter: A four

bit counter that increments on a negative pointer movement. During a read

cycle internal logic holds the count until the read cycle is complete, and

then updates the counter. This counter is cleared on a reset pulse, when a

1 is written to the reset counter control bit (RESETC), or by a read cycle.

15

16

A1 RX

O-bits

Port 1 A-side Drop Bus Receive 0-bits: The eight bits indicate the states

of the eight overhead communication bits received in the VT/TU. Bits 3-0

correspond to bits 3-6 in the ﬁrst justiﬁcation control byte, while bits 7-4

correspond to bits 3-6 in the second justiﬁcation control byte in the VT/TU

format.

A1UPSL

Port 1 A-side Drop Bus Microprocessor-Written Signal Label: The

three bit positions correspond to the three signal label bits found in bits 5

through 7 in V5. Bit 2 corresponds to bit 7 in the V5 byte. These bits are

written by the microprocessor, and compared against the received signal

label for a mismatch signal label alarm.

TXC-04011-MB

Ed. 1, September 1995

- 37 -

ADMA-T1P

TXC-04011

PRELIMINARY

PORT 1 B-SIDE DROP BUS RECEIVE REGISTERS

Address

Bit

Symbol

Description

18

7-0

B1BIP2

Count

Port 1 B-side Drop Bus BIP-2 Counter: An 8-bit saturating counter which

counts the number of BIP-2 errors detected in the receive direction. A

maximum of two errors can be detected each frame. During a read cycle

internal logic holds the incoming error count until the read cycle is com-

plete, and then updates the counter. This counter is cleared on a reset

pulse, when a 1 is written to the reset counter control bit (RESETC), or by

a read cycle.

19

1A

7-0

B1FEBE

Count

Port 1 B-side Drop Bus FEBE Counter: An 8-bit saturating counter

which counts the number of FEBE errors received (Bit 3 in V5 = 1). During

a read cycle internal logic holds an incoming error count until the read

cycle is complete, and then updates the counter. This counter is cleared on

a reset pulse, when a 1 is written to the reset counter control bit

(RESETC), or by a read cycle.

7

6

B1UNEQ Port 1 B-side Drop Bus Unequipped Indication: A latched bit position

which indicates an Unequipped status has been detected in the V5 signal

label bits (Bits 5-7 in V5 = 0). This bit position is cleared on a microproces-

sor read cycle. If the alarm is active, this bit position will re-latch.

B1SLER

Port 1 B-side Drop Bus Signal Label Mismatch Indication: A latched bit

position which indicates that the receive signal label bits (Bits 5-7 in V5)

did not match the microprocessor-written signal label. This bit position is

cleared on a microprocessor read cycle. If the alarm is active, this bit posi-

tion re-latches.

3

B1NDF

Port 1 B-side Drop Bus New Data Flag Indication: A latched bit position

which indicates a New Data Flag (1001) has been detected in the V1

pointer byte (Bits 1-4 in V1 are the inverse of the 0110). This bit position is

cleared on a microprocessor read cycle. If the alarm is active, this bit posi-

tion re-latches.

0

7

6

5

TB1FE

B1AIS

Port 1 Transmit B-side Add Bus FIFO Error: A latched bit position which

indicates that the B-side add bus FIFO has overﬂowed or underﬂowed.

The FIFO will reset automatically. This bit position is cleared on a micro-

processor read cycle. If the alarm is active, this bit position re-latches.

1B

Port 1 B-side Drop Bus VT AIS Alarm: A latched bit position which indi-

cates a VT (TU) AIS has been detected. This bit position is cleared on a

microprocessor read cycle. If the alarm is active, this bit position will re-

latch.

B1LOP

B1SIZE

Port 1 B-side Drop Bus Loss Of Pointer Alarm: A latched bit position

which indicates a loss of pointer has been detected. This bit position is

cleared on a microprocessor read cycle. If the alarm is active, this bit posi-

tion will re-latch.

Port 1 B-side Drop Bus Pointer Size Error Indication: A latched bit

position which indicates that the receive size indicator in the pointer (Bits 5

and 6 in the V1 pointer byte) does not = 11. This bit position is cleared on a

microprocessor read cycle. If the alarm is active, this bit position will re-

latch.

TXC-04011-MB

Ed. 1, September 1995

- 38 -

ADMA-T1P

TXC-04011

PRELIMINARY

Address

Bit

Symbol

Description

1B

(cont.)

4

B1RDI

Port 1 B-side Drop Bus Remote Defect Indication (FERF): A latched bit

position which indicates an RDI (FERF/Yellow) alarm has been detected

(Bit 8 in V5 = 1). This bit position is cleared on a microprocessor read

cycle. If the alarm is active, this bit position will re-latch.

3

B1RFI

Port 1 B-side Drop Bus Remote Failure Indication: A latched bit posi-

tion which indicates an RFI alarm has been detected (Bit 4 in V5 = 1). This

bit position is cleared on a microprocessor read cycle. If the alarm is

active, this bit position will re-latch.

2-0

B1 RX

Label

Port 1 B-side Drop Bus Received Signal Label: The three bit positions

correspond to the three signal label bits found in bits 5 through 7 in V5.

These bits are updated each V5 time. Bit 2 corresponds to bit 7 in the V5

byte. These bits are also compared against the microprocessor-written

mismatch signal label bits for a mismatch indication.

1C

7-4

3-0

B1PJ

Count

Port 1 B-side Drop Bus Positive Pointer Justiﬁcation Counter: A four

bit counter that increments on a positive pointer movement. During a read

cycle internal logic holds an incoming count of 1 until the read cycle is

complete, and then updates the counter. This counter is cleared on a reset

pulse, when a 1 is written to the reset counter control bit (RESETC), or by

a read cycle.

B1NJ

Count

Port 1 B-side Drop Bus Negative Pointer Justiﬁcation Counter: A four

bit counter that increments on a negative pointer movement. During a read

cycle internal logic holds an incoming count of 1 until the read cycle is

complete, and then updates the counter. This counter is cleared on a reset

pulse, when a 1 is written to the reset counter control bit (RESETC), or by

a read cycle.

1D

1E

7-0

2-0

B1 RX

O-bits

Port 1 B-side Drop Bus Receive 0-bits: The eight bits indicate the states

of the eight overhead communication bits received in the VT. Bits 3-0 cor-

respond to bits 3-6 in the ﬁrst justiﬁcation control byte, while bits 7-4 corre-

spond to bits 3-6 in the second justiﬁcation control byte in the VT/TU

format.

B1UPSL

Port 1 B-side Drop Bus Microprocessor-Written Signal Label: The

three bit positions correspond to the three signal label bits found in bits 5

through 7 in V5. Bit 2 corresponds to bit 7 in the V5 byte. These bits are

written by the microprocessor, and compared against the received signal

label for a mismatch signal label alarm.

TXC-04011-MB

Ed. 1, September 1995

- 39 -

ADMA-T1P

TXC-04011

PRELIMINARY

B-SIDE DROP BUS STATUS REGISTERS

Address

Bit

Symbol

Description

24

7

BDLOC

B-side Drop Bus Loss Of Clock: A latched bit position that indicates a

loss of clock in the B-side drop bus has been detected. A loss of clock

alarm causes a receive AIS for the duration of the alarm, and sets the like-

named add bus signals (data and PAR signal) to the high impedance state.

The BADD indication signal becomes inactive for the duration of the alarm.

This bit position is cleared on a microprocessor read cycle. If the alarm is

active, this bit position will re-latch. The loss of clock alarm occurs when

the input drop clock (BDCLK) is stuck high or low for 10 or more clock

cycles. Recovery occurs on the first drop clock transition.

5

BALOC

B Add Bus Loss Of Clock: A latched bit position which indicates that the

B Add bus has detected a loss of clock, when control lead ABUST is low. A

loss of clock alarm causes the add data and parity bit to 3-state, and sets

the add indicator off for the duration of the alarm. This bit position is

cleared on a microprocessor read cycle. If the alarm is active, this bit posi-

tion will re-latch. The loss of clock alarm occurs when the input add clock

(BACLK) is stuck high or low for 10 or more clock cycles. Recovery occurs

on the first add clock transition.

2

1

0

B2DH4E

B1DH4E

BDPAR

B-side Drop Bus Port 2 Loss of H4 Indication: A latched bit position that

indicates that the anticipated received H4 multiframe sequence of 00, 01,

10, 11 has not been received properly. The ADMA-T1P will continue to

operate in a free running mode, but will lock to a new H4 sequence after

two consecutive sequences have been received properly. This bit position

is cleared on a microprocessor read cycle. If the alarm is active, this bit

position will re-latch.

B-side Drop Bus Port 1 Loss of H4 Indication: A latched bit position

which indicates that the anticipated received H4 multiframe sequence of

00, 01, 10, 11 has not been received properly. The ADMA-T1P will con-

tinue to operate in a free running mode, but will lock to a new H4 sequence

after two consecutive sequences have been received properly. This bit

position is cleared on a microprocessor read cycle. If the alarm is active,

this bit position will re-latch.

B-side Drop Bus Parity Error Detected: A latched bit position which indi-

cates that an odd parity error has been detected in the B-side drop bus sig-

nals. Even parity detection is provided by writing a 1 to the Drop Bus Parity

Even (DPE) control bit. Other than an alarm indication, no other action is

taken. This bit position is cleared on a microprocessor read cycle. If the

alarm is active, this bit position will re-latch.

TXC-04011-MB

Ed. 1, September 1995

- 40 -

ADMA-T1P

TXC-04011

PRELIMINARY

PORT 2 STATUS/TRANSMIT REGISTERS

Address

Bit

Symbol

Description

28

7-0

Port 2

Pointer

Leak

Rate

Value

Port 2 FIFO Leak Rate Register: The count written into this location is

used for the internal leak buffer, and represents the average leak rate. A

count of one represents 8 frames, or 2 multiframes in the rate of occur-

rence of pointer movements from the number of counts read from positive/

negative stuff counters. A count of 0 is invalid, and no selection takes

place.

29

2A

7-0

Port 2

Coding

Error

Port 2 Transmit Coding Violation Counter: Low order byte of a 16-bit

saturating counter that counts the number of coding errors that have

occurred in the AMI or B8ZS line codes. During a read cycle internal logic

holds a count of 1 until the read cycle is complete, and then updates the

Counter

Low Order counter. This counter is cleared on a reset pulse, when a 1 is written to the

Byte

reset counter control bit (RESETC), or by a read cycle. This location must

be read first before reading the high order byte.

2

1

R2FFE

Port 2 Receive FIFO Error: A latched bit position which indicates that the

receive FIFO for port 2 has overflowed or underflowed. The FIFO will reset

automatically. Other than an alarm indication, no other action will be taken.

This bit position is cleared on a microprocessor read cycle. If the alarm is

active, this bit position re-latches.

T2LOCS

Port 2 Transmit Loss Of T1 Clock or Signal: A latched bit position which

indicates that the Port 2 T1 clock or data signal has failed. This bit position

is cleared on a microprocessor read cycle, but if either of the alarms is

then active this bit position re-latches. Loss of clock occurs when the T1

input clock (TCI2) is stuck high or low for 10 or more clock cycles. Recov-

ery occurs on the first T1 input clock transition. Loss of signal for the rail

interface occurs when no TPI2 signal transitions occur in a period of 175 ±

75 consecutive pulse positions. Recovery occurs when there is an average

pulse density of at least 12.5% over a period of 175 ± 75 contiguous pulse

positions starting with the receipt of a detected pulse.

0

T2AIS

Port 2 Transmit AIS Detected: A latched bit position which indicates that

a T1 AIS (unframed all ones) has been detected in the Port 2 data. This bit

position is cleared on a microprocessor read cycle. If the alarm is active,

this bit position re-latches.

2B

7-0

Port 2

Coding

Error

Port 2 Transmit Coding Violation Counter: High order byte of an 16-bit

saturating counter which counts the number of coding errors that have

occurred in the AMI or B8ZS line codes. This counter is cleared on a reset

pulse, when a 1 is written to the reset counter control bit (RESETC), or by

Counter

High Order a read cycle.

Byte

TXC-04011-MB

Ed. 1, September 1995

- 41 -

ADMA-T1P

TXC-04011

PRELIMINARY

Address

Bit

Symbol

Description

2D

7

T2VTAIS Port 2 Transmit VT/TU AIS: A 1 causes a VT/TU AIS to be generated and

transmitted. A VT/TU AIS consists of all ones in the entire VT, including

bytes V1 through V4.

6

T2FB2

Port 2 Transmit BIP-2 Error Mask (Force BIP-2 Error): A 1 causes bits 1

and 2 (BIP-2 value) in the transmitted V5 byte to be sent inverted from the

calculated value continuously.

5

4

T2FFB

T2RDI

T2RFI

Port 2 Transmit Force FEBE Error: A 1 causes bit 3 (FEBE) in the V5

byte to be transmitted inverted from its normally transmitted value.

Port 2 Transmit Remote Defect Indication (Yellow/FERF): A 1 causes

an RDI alarm to be transmitted (Bit 8 in V5 = 1).

3

Port 2 Transmit Remote Failure Indication: A 1 causes an RFI alarm to

be transmitted (Bit 4 in V5 = 1).

2-0

A2 TX

Label

Port 2 Transmit Signal Label: The three bit positions written by the pro-

cessor correspond to bits 5 through 7 in the V5 byte. Bit 2 corresponds to

bit 7 in the V5 byte.

2E

2F

7-0

Port 2

Transmit

O-bits

Port 2 Transmit Overhead Communication Channel Bits: Bits 3-0 cor-

respond to bits 3-6 in the ﬁrst justiﬁcation control byte, while bits 7-4 corre-

spond to bits 3-6 in the second justiﬁcation control byte in the VT/TU

format.

7

R2SEL

VTN2

Port 2 Receive A or B-side VT/TU Bus Selection: Determines the drop

bus VT/TU selection. A 1 selects the B-side drop bus, and a 0 selects the

A-side drop bus.

6-0

Port 2 VT/TU Selection: Works in conjunction with the R2SEL control bit.

The seven bit binary code written into this location selects the VT or TU

that is to be dropped from the A or B-side drop bus. The binary value of 0

and a value above the range will not select a VT or TU. For example, the

VT selection in an STS-3 format is given below:

Bit 6 5 4 3 2 1 0 STS-3 Mapping

0 0 0 0 0 0 0 No VT# selected, AIS generated

0 0 0 0 0 0 1 STS-1#1, GP#1, VT#1 selected

0 0 1 1 1 0 1 STS-1#2, GP#1, VT#1 selected

0 1 1 1 0 0 1 STS-1#3, GP#1, VT#1 selected

- - - - - - -

1 0 1 0 1 0 0 STS-1#3, GP#7, VT#4 selected

1 0 1 0 1 0 1 No VT# selected, AIS generated

- - - - - - -

1 1 1 1 1 1 1 No VT# selected, AIS generated

Note: AIS may be over-written by writing a 0 to R2EN which will 3-state the

port 2 data and clock output leads.

TXC-04011-MB

Ed. 1, September 1995

- 42 -

ADMA-T1P

TXC-04011

PRELIMINARY

PORT 2 A-SIDE DROP BUS RECEIVE REGISTERS

Address

Bit

Symbol

Description

30

7-0

A2BIP2

Count

Port 2 A-side Drop Bus BIP-2 Counter: An 8-bit saturating counter which

counts the number of BIP-2 errors detected in the receive direction. A

maximum of two errors can be detected each frame. During a read cycle

internal logic holds the incoming error count until the read cycle is com-

plete, and then updates the counter. This counter is cleared on a reset

pulse, when a 1 is written to the reset counter control bit (RESETC), or by

a read cycle.

31

32

7-0

A2FEBE

Count

Port 2 A-side Drop Bus FEBE Counter: An 8-bit saturating counter

which counts the number of FEBE errors received (Bit 3 in V5 = 1). During

a read cycle internal logic holds an incoming error count until the read

cycle is complete, and then updates the counter. This counter is cleared on

a reset pulse, when a 1 is written to the reset counter control bit

(RESETC), or by a read cycle.

7

6

A2UNEQ Port 2 A-side Drop Bus Unequipped Indication: A latched bit position

which indicates an Unequipped status has been detected in the V5 signal

label bits (Bits 2-0 in V5 = 0). This bit position is cleared on a microproces-

sor read cycle. If the alarm is active, this bit position will re-latch.

A2SLER

Port 2 A-side Drop Bus Signal Label Mismatch Indication: A latched bit

position which indicates that the receive signal label bits (Bits 2-0 in V5)

did not match the microprocessor-written signal label. This bit position is

cleared on a microprocessor read cycle. If the alarm is active, this bit posi-

tion re-latches.

3

A2NDF

Port 2 A-side Drop Bus New Data Flag Indication: A latched bit position

which indicates a New Data Flag (1001) has been detected in the V1

pointer byte (Bits 1-4 in V1 are the inverse of the 0110). This bit position is

cleared on a microprocessor read cycle. If the alarm is active, this bit posi-

tion re-latches.

0

7

6

5

TA2FE

A2AIS

Port 2 Transmit A-side Add Bus FIFO Error: A latched bit position which

indicates that the A-side add bus FIFO has overﬂowed or underﬂowed.

The FIFO will reset automatically. This bit position is cleared on a micro-

processor read cycle. If the alarm is active, this bit position re-latches.

33

Port 2 A-side Drop Bus VT AIS Alarm: A latched bit position which indi-

cates a VT (TU) AIS has been detected. This bit position is cleared on a

microprocessor read cycle. If the alarm is active, this bit position will re-

latch.

A2LOP

A2SIZE

Port 2 A-side Drop Bus Loss Of Pointer Alarm: A latched bit position

which indicates a loss of pointer has been detected. This bit position is

cleared on a microprocessor read cycle. If the alarm is active, this bit posi-

tion will re-latch.

Port 2 A-side Drop Bus Pointer Size Error Indication: A latched bit

position which indicates that the receive size indicator in the pointer (Bits 5

and 6 in the V1 pointer byte) does not = 11. This bit position is cleared on a

microprocessor read cycle. If the alarm is active, this bit position will re-

latch.

TXC-04011-MB

Ed. 1, September 1995

- 43 -

ADMA-T1P

TXC-04011

PRELIMINARY

Address

Bit

Symbol

Description

33

(cont.)

4

A2RDI

Port 2 A-side Drop Bus Remote Defect Indication (FERF): A latched bit

position which indicates an RDI (FERF/Yellow) alarm has been detected

(Bit 8 in V5 = 1). This bit position is cleared on a microprocessor read

cycle. If the alarm is active, this bit position will re-latch.

3

A2RFI

Port 2 A-side Drop Bus Remote Failure Indication: A latched bit posi-

tion which indicates an RFI alarm has been detected (Bit 4 in V5 = 1). This

bit position is cleared on a microprocessor read cycle. If the alarm is

active, this bit position will re-latch.

2-0

A2 RX

Label

Port 2 A-side Drop Bus Received Signal Label: The three bit positions

correspond to the three signal label bits found in bits 5 through 7 in V5.

These bits are updated each V5 time. Bit 2 corresponds to bit 7 in the V5

byte. These bits are also compared against the microprocessor written

mismatch signal label bits for a mismatch indication.

34

7-4

3-0

Port 2

A2PJ

Count

Port 2 A-side Drop Bus Positive Pointer Justiﬁcation Counter: A four

bit counter that increments on a positive pointer movement. During a read

cycle internal logic holds an incoming count of 1 until the read cycle is

complete, and then updates the counter. This counter is cleared on a reset

pulse, when a 1 is written to the reset counter control bit (RESETC), or by

a read cycle.

Port 2

A2NJ

Count

Port 2 A-side Drop Bus Negative Pointer Justiﬁcation Counter: A four

bit counter that increments on a negative pointer movement. During a read

cycle internal logic holds an incoming count of 1 until the read cycle is

complete, and then updates the counter. This counter is cleared on a reset

pulse, when a 1 is written to the reset counter control bit (RESETC), or by

a read cycle.

35

36

7-0

2-0

A2 RX

O-bits

Port 2 A-side Drop Bus Receive 0-bits: The eight bits indicate the states

of the eight overhead communication bits received in the VT/TU. Bits 3-0

correspond to bits 3-6 in the ﬁrst justiﬁcation control byte, while bits 7-4

correspond to bits 3-6 in the second justiﬁcation control byte in the VT/TU

format.

A2UPSL

Port 2 A-side Drop Bus Microprocessor-Written Signal Label: The

three bit positions correspond to the three signal label bits found in bits 5

through 7 in V5. Bit 2 corresponds to bit 7 in the V5 byte. These bits are

written by the microprocessor, and compared against the received signal

label for a mismatch signal label alarm.

TXC-04011-MB

Ed. 1, September 1995

- 44 -

ADMA-T1P

TXC-04011

PRELIMINARY

PORT 2 B-SIDE DROP BUS RECEIVE REGISTERS

Address

Bit

Symbol

Description

38

7-0

B2BIP2

Count

Port 2 B-side Drop Bus BIP-2 Counter: An 8-bit saturating counter which

counts the number of BIP-2 errors detected in the receive direction. A

maximum of two errors can be detected each frame. During a read cycle

internal logic holds the incoming error count until the read cycle is com-

plete, and then updates the counter. This counter is cleared on a reset

pulse, when a 1 is written to the reset counter control bit (RESETC), or by

a read cycle.

39

3A

7-0

B2FEBE

Count

Port 2 B-side Drop Bus FEBE Counter: An 8-bit saturating counter

which counts the number of FEBE errors received (Bit 3 in V5 = 1). During

a read cycle internal logic holds an incoming error count until the read

cycle is complete, and then updates the counter. This counter is cleared on

a reset pulse, when a 1 is written to the reset counter control bit

(RESETC), or by a read cycle.

7

6

B2UNEQ Port 2 B-side Drop Bus Unequipped Indication: A latched bit position

which indicates an Unequipped status has been detected in the V5 signal

label bits (Bits 2-0 in V5 = 0). This bit position is cleared on a microproces-

sor read cycle. If the alarm is active, this bit position will re-latch.

B2SLER

Port 2 B-side Drop Bus Signal Label Mismatch Indication: A latched bit

position which indicates that the receive signal label bits (Bits 2-0 in V5)

did not match the microprocessor-written signal label. This bit position is

cleared on a microprocessor read cycle. If the alarm is active, this bit posi-

tion re-latches.

3

B2NDF

Port 2 B-side Drop Bus New Data Flag Indication: A latched bit position

which indicates a New Data Flag (1001) has been detected in the V1

pointer byte (Bits 1-4 in V1 are the inverse of the 0110). This bit position is

cleared on a microprocessor read cycle. If the alarm is active, this bit posi-

tion re-latches.

0

7

6

5

TB2FE

B2AIS

Port 2 Transmit B-side Add Bus FIFO Error: A latched bit position which

indicates that the B-side add bus FIFO has overﬂowed or underﬂowed.

The FIFO will reset automatically. This bit position is cleared on a micro-

processor read cycle. If the alarm is active, this bit position re-latches.

3B

Port 2 B-side Drop Bus VT AIS Alarm: A latched bit position which indi-

cates a VT (TU) AIS has been detected. This bit position is cleared on a

microprocessor read cycle. If the alarm is active, this bit position will re-

latch.

B2LOP

B2SIZE

Port 2 B-side Drop Bus Loss Of Pointer Alarm: A latched bit position

which indicates a loss of pointer has been detected. This bit position is

cleared on a microprocessor read cycle. If the alarm is active, this bit posi-

tion will re-latch.

Port 2 B-side Drop Bus Pointer Size Error Indication: A latched bit

position which indicates that the receive size indicator in the pointer (Bits 5

and 6 in the V1 pointer byte) does not = 11. This bit position is cleared on a

microprocessor read cycle. If the alarm is active, this bit position will re-

latch.

TXC-04011-MB

Ed. 1, September 1995

- 45 -

ADMA-T1P

TXC-04011

PRELIMINARY

Address

Bit

Symbol

Description

3B

(cont.)

4

B2RDI

Port 2 B-side Drop Bus Remote Defect Indication (FERF): A latched bit

position which indicates an RDI (FERF/Yellow) alarm has been detected

(Bit 8 in V5 = 1). This bit position is cleared on a microprocessor read

cycle. If the alarm is active, this bit position will re-latch.

3

B2RFI

Port 2 B-side Drop Bus Remote Failure Indication: A latched bit posi-

tion which indicates an RFI alarm has been detected (Bit 4 in V5 = 1). This

bit position is cleared on a microprocessor read cycle. If the alarm is

active, this bit position will re-latch.

2-0

B2 RX

Label

Port 2 B-side Drop Bus Received Signal Label: The three bit positions

correspond to the three signal label bits found in bits 5 through 7 in V5.

These bits are updated each V5 time. Bit 2 corresponds to bit 7 in the V5

byte. These bits are also compared against the microprocessor-written

mismatch signal label bits for a mismatch indication.

3C

7-4

3-0

B2PJ

Count

Port 2 B-side Drop Bus Positive Pointer Justiﬁcation Counter: A four

bit counter that increments on a positive pointer movement. During a read

cycle internal logic holds an incoming count of 1 until the read cycle is

complete, and then updates the counter. This counter is cleared on a reset

pulse, when a 1 is written to the reset counter control bit (RESETC), or by

a read cycle.

B2NJ

Count

Port 2 B-side Drop Bus Negative Pointer Justiﬁcation Counter: A four

bit counter that increments on a negative pointer movement. During a read

cycle internal logic holds an incoming count of 1 until the read cycle is

complete, and then updates the counter. This counter is cleared on a reset

pulse, when a 1 is written to the reset counter control bit (RESETC), or by

a read cycle.

3D

3E

7-0

2-0

B2 RX

O-bits

Port 2 B-side Drop Bus Receive 0-bits: The eight bits indicate the states

of the eight overhead communication bits received in the VT. Bits 3-0 cor-

respond to bits 3-6 in the ﬁrst justiﬁcation control byte, while bits 7-4 corre-

spond to bits 3-6 in the second justiﬁcation control byte in the VT/TU

format.

B2UPSL

Port 2 B-side Drop Bus Microprocessor-Written Signal Label: The

three bit positions correspond to the three signal label bits found in bits 5

through 7 in V5. Bit 2 corresponds to bit 7 in the V5 byte. These bits are

written by the microprocessor, and compared against the received signal

label for a mismatch signal label alarm.

TXC-04011-MB

Ed. 1, September 1995

- 46 -

ADMA-T1P

TXC-04011

PRELIMINARY

MULTIPLEX FORMAT AND MAPPING INFORMATION

STS-1 VT1.5 (1.544 Mbit/s) Multiplex Format

The following diagram and table illustrate the mapping of the 28 VT1.5s into a STS-1 SPE. Column 1 is

assigned to carry the path overhead bytes.

VT1.5

3 COLUMNS

1

2

3

1

4

2

3

27

1

29 30 31

58 59 60

87

J1

B3

R

VT VT

1.5 1.5

#1 #2

VT

1.5

#

VT VT

1.5 1.5

#1 #2

VT

1.5

#

VT VT

1.5 1.5

#1 #2

VT

1.5

#

C2

G1

F2

H4

Z3

Z4

Z5

R

28

STS-1 SPE

TXC-04011-MB

Ed. 1, September 1995

- 47 -

ADMA-T1P

TXC-04011

PRELIMINARY

STS-1 Mapping

0F & 2F Registers

VT1.5

VT#

Column Numbers*

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

No VT Selected

2, 31,60

1

2

3, 32,61

3

4, 33,62

4

5, 34,63

5

6, 35,64

6

7, 36,65

7

8, 37,66

8

9, 38,67

9

10, 39, 68

11, 40, 69

12, 41, 70

13, 42, 71

14, 43, 72

15, 44, 73

16, 45, 74

17, 46, 75

18, 47, 76

19, 48, 77

20, 49, 78

21, 50, 79

22, 51, 80

23, 52, 81

24, 53, 82

25, 54, 83

26, 55, 84

27, 56, 85

28, 57, 86

29, 58, 87

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

* Note: Columns 30 and 59 carry ﬁxed Stuff bytes. Column 1 is assigned for the POH bytes.

TXC-04011-MB

Ed. 1, September 1995

- 48 -

ADMA-T1P

TXC-04011

PRELIMINARY

STS-3/AU-3 VT1.5/TU-11 (1.544 Mbit/s) Multiplex Format Mapping

The following diagram and table illustrate the mapping of the VT1.5/TU-11s into a STS-3/AU-3 SPE. Each

STS-3 carries three STS-1s. Column 1 in each STS-1/AU-3 is assigned to carry the path overhead bytes.

VT1.5

3 COLUMNS

1

2

3

1

4

2

3

27

1

2

29 30 31

58 59 60

87

1

87

1

87

J1

R

J1

B3

C2

G1

F2

H4

Z3

Z4

Z5

B3

C2

G1

F2

H4

Z3

Z4

Z5

B3

C2

G1

F2

H4

Z3

Z4

Z5

VT VT

1.5 1.5

#1 #2

VT

1.5

#

VT VT

1.5 1.5

#1 #2

VT

1.5

#

VT VT

1.5 1.5

#1 #2

VT

1.5

#

VT VT

1.5 1.5

#1 #2

VT

1.5

#

VT VT

1.5 1.5

#1 #2

VT

1.5

#

R

28

STS-1 #1

#2

#3

1

261

STS-3/AU-3 SPE

TXC-04011-MB

Ed. 1, September 1995

- 49 -

ADMA-T1P

TXC-04011

PRELIMINARY

STS-3 AU-3 Mapping

VT

TU

#

0F & 2F

Registers

6 5 4 3 2 1 0 Numbers

VT/TU

Column

VT

TU

#

0F & 2F

Registers

6 5 4 3 2 1 0 Numbers

VT/TU

Column

VT

TU

#

0F & 2F

Registers

6 5 4 3 2 1 0 Numbers*

VT/TU

Column

0 0 0 0 0 0 0

No TU Selected

1

2

3

4

5

6

7

8

9

0 0 0 0 0 0 1 4 91 178 29 0 0 1 1 1 0 1

0 0 0 0 0 1 0 7 94 181 30 0 0 1 1 1 1 0

5

8

92 179 57 0 1 1 1 0 0 1 6 93 180

95 182 58 0 1 1 1 0 1 0 9 96 183

0 0 0 0 0 1 1 10 97 184 31 0 0 1 1 1 1 1 11 98 185 59 0 1 1 1 0 1 1 12 99 186

0 0 0 0 1 0 0 13 100 187 32 0 1 0 0 0 0 0 14 101 188 60 0 1 1 1 1 0 0 15 102 189

0 0 0 0 1 0 1 16 103 190 33 0 1 0 0 0 0 1 17 104 191 61 0 1 1 1 1 0 1 18 105 192

0 0 0 0 1 1 0 19 106 193 34 0 1 0 0 0 1 0 20 107 194 62 0 1 1 1 1 1 0 21 108 195

0 0 0 0 1 1 1 22 109 196 35 0 1 0 0 0 1 1 23 110 197 63 0 1 1 1 1 1 1 24 111 198

0 0 0 1 0 0 0 25 112 199 36 0 1 0 0 1 0 0 26 113 200 64 1 0 0 0 0 0 0 27 114 201

0 0 0 1 0 0 1 28 115 202 37 0 1 0 0 1 0 1 29 116 203 65 1 0 0 0 0 0 1 30 117 204

10 0 0 0 1 0 1 0 31 118 205 38 0 1 0 0 1 1 0 32 119 206 66 1 0 0 0 0 1 0 33 120 207

11 0 0 0 1 0 1 1 34 121 208 39 0 1 0 0 1 1 1 35 122 209 67 1 0 0 0 0 1 1 36 123 210

12 0 0 0 1 1 0 0 37 124 211 40 0 1 0 1 0 0 0 38 125 212 68 1 0 0 0 1 0 0 39 126 213

13 0 0 0 1 1 0 1 40 127 214 41 0 1 0 1 0 0 1 41 128 215 69 1 0 0 0 1 0 1 42 129 216

14 0 0 0 1 1 1 0 43 130 217 42 0 1 0 1 0 1 0 44 131 218 70 1 0 0 0 1 1 0 45 132 219

15 0 0 0 1 1 1 1 46 133 220 43 0 1 0 1 0 1 1 47 134 221 71 1 0 0 0 1 1 1 48 135 222

16 0 0 1 0 0 0 0 49 136 223 44 0 1 0 1 1 0 0 50 137 224 72 1 0 0 1 0 0 0 51 138 225

17 0 0 1 0 0 0 1 52 139 226 45 0 1 0 1 1 0 1 53 140 227 73 1 0 0 1 0 0 1 54 141 228

18 0 0 1 0 0 1 0 55 142 229 46 0 1 0 1 1 1 0 56 143 230 74 1 0 0 1 0 1 0 57 144 231

19 0 0 1 0 0 1 1 58 145 232 47 0 1 0 1 1 1 1 59 146 233 75 1 0 0 1 0 1 1 60 147 234

20 0 0 1 0 1 0 0 61 148 235 48 0 1 1 0 0 0 0 62 149 236 76 1 0 0 1 1 0 0 63 150 237

21 0 0 1 0 1 0 1 64 151 238 49 0 1 1 0 0 0 1 65 152 239 77 1 0 0 1 1 0 1 66 153 240

22 0 0 1 0 1 1 0 67 154 241 50 0 1 1 0 0 1 0 68 155 242 78 1 0 0 1 1 1 0 69 156 243

23 0 0 1 0 1 1 1 70 157 244 51 0 1 1 0 0 1 1 71 158 245 79 1 0 0 1 1 1 1 72 159 246

24 0 0 1 1 0 0 0 73 160 247 52 0 1 1 0 1 0 0 74 161 248 80 1 0 1 0 0 0 0 75 162 249

25 0 0 1 1 0 0 1 76 163 250 53 0 1 1 0 1 0 1 77 164 251 81 1 0 1 0 0 0 1 78 165 252

26 0 0 1 1 0 1 0 79 166 253 54 0 1 1 0 1 1 0 80 167 254 82 1 0 1 0 0 1 0 81 168 255

27 0 0 1 1 0 1 1 82 169 256 55 0 1 1 0 1 1 1 83 170 257 83 1 0 1 0 0 1 1 84 171 258

28 0 0 1 1 1 0 0 85 172 259 56 0 1 1 1 0 0 0 86 173 260 84 0 0 1 0 1 0 0 87 174 261

STS-1 #1, AU-3 A

STS-1 #2, AU-3 B

STS-1 #3, AU-3 C

* Note: Columns 88, 89, 90, 175, 176, 177 are ﬁxed stuff.

TXC-04011-MB

Ed. 1, September 1995

- 50 -

ADMA-T1P

TXC-04011

PRELIMINARY

TU-11 - VC-4 Multiplex Format Mapping

The following diagram and table illustrate the mapping of TU-11s into a VC-4. The ADMA-T1P provides control

bits for enabling the Null Pointer Indicators (NPIs) for the columns indicated.

3 COLUMNS

1

2

3

1

4

2

3

TU-11

27

1

2

3

TUG-2

4

1

31

59

86

7

1

86

7

1

86

7

N

P

I

N

P

I

N

P

I

TUG-3

1

6

7

1

2

7

1

2

3

1

10

VC-4

P

O

H

1

4

261

TXC-04011-MB

Ed. 1, September 1995

- 51 -

ADMA-T1P

TXC-04011

PRELIMINARY

TU-11 - VC-4 Multiplex Format Mapping

0F & 2F

VC-4

0F & 2F

VC-4

0F & 2F

VC-4

TU

#

Registers

6 5 4 3 2 1 0 Numbers

Column

TU

#

Registers

6 5 4 3 2 1 0 Numbers

Column

TU

#

Registers

6 5 4 3 2 1 0 Numbers

Column

0 0 0 0 0 0 0

No TU Selected

1

2

3

4

5

6

7

8

9

0 0 0 0 0 0 1 10 94 178 29 0 0 1 1 1 0 1 11 95 179 57 0 1 1 1 0 0 1 12 96 180

0 0 0 0 0 1 0 13 97 181 30 0 0 1 1 1 1 0 14 98 182 58 0 1 1 1 0 1 0 15 99 183

0 0 0 0 0 1 1 16 100 184 31 0 0 1 1 1 1 1 17 101 185 59 0 1 1 1 0 1 1 18 102 186

0 0 0 0 1 0 0 19 103 187 32 0 1 0 0 0 0 0 20 104 188 60 0 1 1 1 1 0 0 21 105 189

0 0 0 0 1 0 1 22 106 190 33 0 1 0 0 0 0 1 23 107 191 61 0 1 1 1 1 0 1 24 108 192

0 0 0 0 1 1 0 25 109 193 34 0 1 0 0 0 1 0 26 110 194 62 0 1 1 1 1 1 0 27 111 195

0 0 0 0 1 1 1 28 112 196 35 0 1 0 0 0 1 1 29 113 197 63 0 1 1 1 1 1 1 30 114 198

0 0 0 1 0 0 0 31 115 199 36 0 1 0 0 1 0 0 32 116 200 64 1 0 0 0 0 0 0 33 117 201

0 0 0 1 0 0 1 34 118 202 37 0 1 0 0 1 0 1 35 119 203 65 1 0 0 0 0 0 1 36 120 204

10 0 0 0 1 0 1 0 37 121 205 38 0 1 0 0 1 1 0 38 122 206 66 1 0 0 0 0 1 0 39 123 207

11 0 0 0 1 0 1 1 40 124 208 39 0 1 0 0 1 1 1 41 125 209 67 1 0 0 0 0 1 1 42 126 210

12 0 0 0 1 1 0 0 43 127 211 40 0 1 0 1 0 0 0 44 128 212 68 1 0 0 0 1 0 0 45 129 213

13 0 0 0 1 1 0 1 46 130 214 41 0 1 0 1 0 0 1 47 131 215 69 1 0 0 0 1 0 1 48 132 216

14 0 0 0 1 1 1 0 49 133 217 42 0 1 0 1 0 1 0 50 134 218 70 1 0 0 0 1 1 0 51 135 219

15 0 0 0 1 1 1 1 52 136 220 43 0 1 0 1 0 1 1 53 137 221 71 1 0 0 0 1 1 1 54 138 222

16 0 0 1 0 0 0 0 55 139 223 44 0 1 0 1 1 0 0 56 140 224 72 1 0 0 1 0 0 0 57 141 225

17 0 0 1 0 0 0 1 58 142 226 45 0 1 0 1 1 0 1 59 143 227 73 1 0 0 1 0 0 1 60 144 228

18 0 0 1 0 0 1 0 61 145 229 46 0 1 0 1 1 1 0 62 146 230 74 1 0 0 1 0 1 0 63 147 231

19 0 0 1 0 0 1 1 64 148 232 47 0 1 0 1 1 1 1 65 149 233 75 1 0 0 1 0 1 1 66 150 234

20 0 0 1 0 1 0 0 67 151 235 48 0 1 1 0 0 0 0 68 152 236 76 1 0 0 1 1 0 0 69 153 237

21 0 0 1 0 1 0 1 70 154 238 49 0 1 1 0 0 0 1 71 155 239 77 1 0 0 1 1 0 1 72 156 240

22 0 0 1 0 1 1 0 73 157 241 50 0 1 1 0 0 1 0 74 158 242 78 1 0 0 1 1 1 0 75 159 243

23 0 0 1 0 1 1 1 76 160 244 51 0 1 1 0 0 1 1 77 161 245 79 1 0 0 1 1 1 1 78 162 246

24 0 0 1 1 0 0 0 79 163 247 52 0 1 1 0 1 0 0 80 164 248 80 1 0 1 0 0 0 0 81 165 249

25 0 0 1 1 0 0 1 82 166 250 53 0 1 1 0 1 0 1 83 167 251 81 1 0 1 0 0 0 1 84 168 252

26 0 0 1 1 0 1 0 85 169 253 54 0 1 1 0 1 1 0 86 170 254 82 1 0 1 0 0 1 0 87 171 255

27 0 0 1 1 0 1 1 89 172 256 55 0 1 1 0 1 1 1 89 173 257 83 1 0 1 0 0 1 1 90 174 258

28 0 0 1 1 1 0 0 91 175 259 56 0 1 1 1 0 0 0 92 176 260 84 0 0 1 0 1 0 0 93 177 261

TUG-3 A

TUG-3 B

TUG-3 C

TXC-04011-MB

Ed. 1, September 1995

- 52 -

ADMA-T1P

TXC-04011

PRELIMINARY

PACKAGE INFORMATION

The ADMA-T1P is available in a 120-pin plastic quad ﬂat package suitable for surface mounting, as illustrated

in Figure 12.

90

61

91

60

See Details “B” and “C”

TRANSWITCH

0.80 TYP

Detail “B”

0.35 TYP

Detail “C”

120

31

1

30

INDEX

PIN #1

23.20 SQ.

28.00 SQ.

31.20 SQ.

0.16 TYP

4.07 MAX

3.42

SEE DETAIL “A”

0.25 MIN

DETAIL “A”

0 -7 DEGREES

0.80

Note: All dimensions are shown in millimeters and are nominal unless otherwise indicated.

Figure 12. ADMA-T1P TXC-04011 120-Pin Plastic Quad Flat Package

TXC-04011-MB

Ed. 1, September 1995

- 53 -

ADMA-T1P

TXC-04011

PRELIMINARY

ORDERING INFORMATION

Part Number: TXC-04011-BIPQ

120-pin Plastic Quad Flat Package (PQFP)


型号：	TXC-04011-BIPQ
厂家：	ETC
描述：	Telecomm/Datacomm 电信/数据通信\n 电信集成电路数据通信
文件：	总60页 (文件大小：162K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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