U62H256SK55 [ETC]
x8 SRAM ; X8 SRAM\n
| 型号： | U62H256SK55 |
| 厂家： | 
ETC |
| 描述： | x8 SRAM
|
| 文件： | 总9页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U62H256S
Automotive Fast 32K x 8 SRAM
Description
Features
The U62H256S is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
32768 x 8 bit static CMOS RAM
information is available. The data
outputs have no preferred state. If
the memory is driven by CMOS
levels in the active state, and if
there is no change of the address,
data input and control signals W or
G, the operating current (IO = 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of W, or by the rising edge of
E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
35 and 55 ns Access Time
Common data inputs and
data outputs
Three-state outputs
Typ. operating supply current
35 ns: 45mA
- Read
- Write
- Standby
- Data Retention
The memory array is based on a
MIXMOS cell.
55 ns: 30mA
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
E = L each address change leads
to a new Read or Write cycle. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word will be
available at the outputs DQ0-DQ7.
After the address change, the data
outputs go High-Z until the new
Standby current < 2 mA
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature range
-40 °C to 85 °C
-40 °C to 125 °C
CECC 90000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity >100 mA
Package:
SOP28 (300 mil)
Pin Configuration
Pin Description
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A14
A12
A7
2
W
3
A13
A8
A6
4
Signal Name Signal Description
A5
5
A9
A0 - A14
Address Inputs
A4
6
A11
DQ0 - DQ7
Data In/Out
A3
7
G
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
E
SOP
A2
8
A10
G
A1
9
E
W
A0
DQ7
10
11
12
13
14
VCC
VSS
DQ0
DQ1
DQ2
VSS
DQ6
DQ5
DQ4
DQ3
Top View
March 8, 1999
1
U62H256S
Block Diagram
A7
A8
A9
A4
Memory Cell
Array
A11
A12
A13
A14
256 Rows x
128 x 8 Columns
A0
A1
A2
A3
A10
A5
DQ0
DQ1
Sense Amplifier/
Write Control Logic
DQ2
DQ3
DQ4
DQ5
A6
Address
Change
Detector
Clock
Generator
DQ6
DQ7
Truth Table
VCC
VSS
E
W
G
Operating Mode
E
W
G
DQ0 - DQ7
H
*
*
High-Z
Standby/not selected
Internal Read
Read
L
L
L
H
H
L
H
L
*
High-Z
Data Outputs Low-Z
Data Inputs High-Z
Write
H or L
*
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.5
-0.5
-
7
V
V
VCC + 0.5
VCC + 0.5
1
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
W
°C
K-Type
A-Type
-40
-40
85
125
Storage Temperature
Tstg
-65
150
200
°C
Output Short-Circuit Current
at VCC = 5 V and VO = 0 V**
| IOS
|
mA
**Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
2
March 8, 1999
U62H256S
Recommended
Operating Conditions
Symbol
VCC
Conditions
Min.
4.5
Max.
5.5
Unit
V
Power Supply Voltage
Input Low Voltage*
VIL
-0.3
2.2
0.8
V
Input High Voltage
VIH
VCC + 0.3
V
*
-2 V at Pulse Width 10 ns
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
ICC(OP)
VCC
VIL
VIH
tcW
tcW
= 5.5 V
= 0.8 V
= 2.2 V
= 35 ns
= 55 ns
90
70
mA
mA
Supply Current - Standby Mode
(CMOS level)
ICC(SB)
VCC
VE
= 5.5 V
= VCC - 0.2 V
K-Type
A-Type
0.5
2
mA
mA
Supply Current - Standby Mode
(TTL level)
ICC(SB)1
VCC
VE
= 5.5 V
= 2.2 V
K-Type
A-Type
10
20
mA
mA
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
VCC
IOL
= 4.5 V
= -4.0 mA
= 4.5 V
2.4
V
V
0.4
2
= 8.0 mA
Input High Leakage Current
Input Low Leakage Current
IIH
IIL
VCC
VIH
VCC
VIL
= 5.5 V
= 5.5 V
= 5.5 V
µA
µA
-2
8
=
0 V
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V
-4
2
mA
mA
Output Leakage Current
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 5.5 V
= 5.5 V
= 5.5 V
µA
µA
Low at Three-State Outputs
-2
=
0 V
March 8, 1999
3
U62H256S
Symbol
IEC
35
55
Switching Characteristics
Read Cycle
Unit
Alt.
tRC
Min.
Max.
Min.
Max.
Read Cycle Time
tcR
35
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time to Data Valid
Chip Enable Access Time to Data Valid
G LOW to Data Valid
tAA
ta(A)
35
35
15
12
12
55
55
25
15
15
tACE
tOE
ta(E)
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
E HIGH to Output in High-Z
G HIGH to Output in High-Z
E LOW to Output in Low-Z
G LOW to Output in Low-Z
Output Hold Time from Address Change
E LOW to Power-Up Time
tHZCE
tHZOE
tLZCE
tLZOE
tOH
3
0
3
0
3
0
3
0
tPU
E HIGH to Power-Down Time
tPD
35
55
Symbol
35
55
Switching Characteristics
Write Cycle
Unit
Min.
35
20
20
0
Max.
Min.
55
35
35
0
Max.
Alt.
tWC
IEC
tcW
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
tWP
tw(W)
tsu(W)
tsu(A)
Write Setup Time
tWP
Address Setup Time
tAS
t
Address Valid to End of Write
Chip Enable Setup Time
Pulse Width Chip Enable to End of Write
Data Setup Time
tAW
20
25
25
15
0
40
40
40
25
0
su(A-WH)
tCW
tsu(E)
tCW
tw(E)
tsu(D)
th(D)
tDS
Data Hold Time
tDH
Address Hold from End of Write
W LOW to Output in High-Z
G HIGH to Output in High-Z
W HIGH to Output in Low-Z
G LOW to Output in Low-Z
tAH
th(A)
0
0
tHZWE
tHZOE
tLZWE
tLZOE
tdis(W)
tdis(G)
ten(W)
ten(G)
15
12
20
15
0
0
0
0
4
March 8, 1999
U62H256S
Data Retention Mode
E - controlled
VCC
4.5 V
VCC(DR) ≥ 2 V
2.2 V
2.2 V
tsu(DR)
trec
Data Retention
E
0 V
VCC(DR) - 0.2 V ≤ VE(DR) ≤ VCC(DR) + 0.3 V
Data Retention
Characteristics
Symbol
Conditions
Min. Typ. Max.
Unit
Alt.
IEC
Data Retention Supply Voltage
Data Retention Supply Current
VCC(DR)
2
5.5
V
ICC(DR) VCC(DR) = 3 V
VE
= VCC(DR) - 0.2 V
K-Type
A-Type
0.09
1
mA
mA
Data Retention Setup Time
Operating Recovery Time
tCDR
tR
tsu(DR) See Data Retention
0
ns
ns
Waveforms (above)
trec
tcR
Test Configuration for Functional Check
5 V
VCC
A0
A1
A2
A3
DQ0
DQ1
DQ2
A4
481
A5
A6
VIH
A7
DQ3
A8
A9
DQ4
DQ5
DQ6
DQ7
A10
A11
A12
A13
A14
VIL
VO
30 pF1)
E
W
G
255
VSS
1) In measurement of tdis(E),tdis(W), ten(E), ten(W), ten(G) the capacitance is 5 pF.
March 8, 1999
5
U62H256S
Capacitance
Conditions
Symbol
Min.
Max.
Unit
Input Capacitance
VCC = 5.0 V
CI
7
pF
VI
f
= VSS
=
1 MHz
Output Capacitance
Co
7
pF
T
a
= 25 °C
All pins not under test must be connected with ground by capacitors.
IC Code Numbers
U62H256
S
35
A
Type
Access Time
35 = 35 ns
Package
S = SOP
55 = 55 ns
Operating Temperature Range
K = -40 to 85 °C
A = -40 to 125 °C
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2
digits the calendar week.
6
March 8, 1999
U62H256S
Read Cycle 1: Ai-controlled (during Read Cycle : E = G = VIL, W = VIH)
tcR
Ai
Address Valid
ta(A)
Output Data
Valid
Previous
Data Valid
DQi
Output
tv(A)
Read Cycle 2: G-, E-controlled (during Read Cycle: W = VIH)
tcR
Address Valid
Ai
ta(E)
tsu(A)
tdis(E)
ten(E)
E
ta(G)
tdis(G)
ten(G)
G
High-Z
DQi
Output Data
Valid
Output
tPU
tPD
ICC(OP)
50 %
50 %
ICC(SB)
March 8, 1999
7
U62H256S
Write Cycle1: W-controlled
tcW
Address Valid
tsu(E)
Ai
E
th(A)
tsu(A-WH)
tw(W)
tsu(A)
W
th(D)
tsu(D)
DQi
Input
Input Data
Valid
tdis(W)
ten(W)
DQi
High-Z
Output
G
Write Cycle 2: E-controlled
tcW
Address Valid
tw(E)
Ai
tsu(A)
th(A)
E
tsu(W)
W
tsu(D)
th(D)
DQi
Input
Input Data
Valid
tdis(W)
ten(E)
DQi
High-Z
Output
G
undefined
L- to H-level
H- to L-level
The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and
rights to change design reserved.
8
March 8, 1999
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure of the ZMD
product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized
by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be
reliable. However Zentrum Mikroelektronik Dresden GmbH (ZMD) makes no
guarantee or warranty concerning the accuracy of said information and shall not be
responsible for any loss or damage of whatever nature resulting from the use of, or
reliance upon it. The information in this document describes the type of component
and shall not be considered as assured characteristics.
ZMD does not guarantee that the use of any information contained herein will not
infringe upon the patent, trademark, copyright, mask work right or other rights of
third parties, and no patent or licence is implied hereby. This document does not in
any way extent ZMD’s warranty on any product beyond that set forth in its standard
terms and conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the
products or specifications, or both, presented in this publication at any time and
without notice.
Zentrum Mikroelektronik Dresden GmbH
Grenzstrasse 28 · D-01109 Dresden · P. O. B. 80 01 34 · D-01101 Dresden · Germany
Phone: +49 351 88 22-3 06 • Fax: +49 351 88 22-3 37 • Email: sales@zmd.de • http://www.zmd.de
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