UC1682XHCZ [ETC]
HIGH-VOLTAGE MIXED-SIGNAL IC; 高压混合信号IC
| 型号： | UC1682XHCZ |
| 厂家： | 
ETC |
| 描述： | HIGH-VOLTAGE MIXED-SIGNAL IC |
| 文件： | 总70页 (文件大小：1137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-VOLTAGE MIXED-SIGNAL IC
80 x 104RGB C-STN LCD Controller-Driver
w/ 32-shade per dot, 12-bit per RGB (Dither 221K)
ES Specifications
Revision 0.6
August 11, 2003
ULTRACHIP
The Coolest LCD Driver. Ever!!
UC1682
80x104RGB CSTN Controller-Driver
TABLE OF CONTENT
INTRODUCTION ................................................................................................................ 1
MAIN APPLICATIONS....................................................................................................... 1
FEATURE HIGHLIGHTS.................................................................................................... 1
ORDERING INFORMATION.............................................................................................. 2
BLOCK DIAGRAM............................................................................................................. 4
PIN DESCRIPTION ............................................................................................................ 5
REFERENCE COG LAYOUT ............................................................................................ 9
COMMAND TABLE.......................................................................................................... 13
COMMAND DESCRIPTION............................................................................................. 15
LCD VOLTAGE SETTING ............................................................................................... 29
VLCD QUICK REFERENCE............................................................................................... 30
LCD DISPLAY CONTROLS............................................................................................. 32
HOST INTERFACE .......................................................................................................... 35
DISPLAY DATA RAM...................................................................................................... 42
RESET & POWER MANAGEMENT................................................................................ 45
ABSOLUTE MAXIMUM RATINGS.................................................................................. 49
SPECIFICATIONS............................................................................................................ 50
AC CHARACTERISTICS ................................................................................................. 51
PHYSICAL DIMENSIONS................................................................................................ 58
ALIGNMENT MARK INFORMATION.............................................................................. 59
PI INFORMATION ............................................................................................................ 60
PAD COORDINATES....................................................................................................... 61
TRAY INFORMATION...................................................................................................... 65
COF INFORMATION........................................................................................................ 66
REVISION HISTORY........................................................................................................ 68
Revision 0.6
1
UC1682
80x104RGB CSTN Controller-Driver
UC1682
Single-Chip, Ultra-Low Power
80COM x 312SEG Matrix
Passive Color LCD Controller-Driver
•
•
•
Support industry standard 3-wire, 4-wire
serial bus (S9, S8, S8uc) and 8-bit/4-bit
parallel bus (8080 or 6800).
INTRODUCTION
UC1682 is an advanced high-voltage mixed-
signal CMOS IC, especially designed for the
display needs of ultra-low power hand-held
devices.
Special driver structure and gray shade
modulation scheme. Ultra-low power
consumption under all display patterns.
Fully programmable Mux Rate, partial
display window, Bias Ratio and Line Rate
allow many flexible power management
options.
This chip employs UltraChip’s unique DCC
(Direct Capacitor Coupling) driver architecture to
achieve near crosstalk free images, with well
balanced gray shades and vivid colors.
•
Software programmable frame rates up to
250Hz. Support the use of fast Liquid
Crystal material for speedy LCD response.
In addition to low power COM and SEG drivers,
UC1682 contains all necessary circuits for high-V
LCD power supply, bias voltage generation,
timing generation and graphics data memory.
•
•
•
Software programmable four temperature
compensation coefficients.
Advanced circuit design techniques are
employed to minimize external component counts
and reduce connector size while achieving
extremely low power consumption.
On-chip Power-ON Reset and Software
Reset command, make RST pin optional.
Self-configuring 10x charge pump with on-
chip pumping capacitors. Only 2/3 external
capacitors are required to operate.
MAIN APPLICATIONS
•
Cellular Phones and other battery operated
•
•
Flexible data addressing/mapping schemes
to support wide ranges of software models
and LCD layout placements.
palm top devices or portable Instruments
Very low pin count (9~10 pins with S9)
allows exceptional image quality in COG
format on conventional ITO glass.
FEATURE HIGHLIGHTS
•
Single chip controller-driver for 80x104
matrix C-STN LCD with comprehensive
support for input format and color depth:
•
•
Many on-chip and I/O pad layout features to
support optimized COG applications.
8-bit RGB:
12-bit RGB:
16-bit RGB:
24-bit RGB:
256 color
4K color
V
DD (digital) range: 1.8V ~ 3.3V
VDD (analog) range: 2.4V ~ 3.3V
LCD VOP range: 5.0V ~ 10.5V
56K color (dithering)
221K color (dithering)
•
•
One software readable ID pin to support
configurable vender identification.
•
•
Available OTP VLCD trimming option to
support precise LCD contrast matching
Partial scroll function and programmable
data update window to support flexible
manipulation of screen data.
Available in COF and gold bump dies
Bump pitch: 41.5µM
Bump gap: 17µM
Bump surface: 3,000µM2
•
Support both row ordered and column
ordered display buffer RAM access.
Revision 0.6
1
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
ORDERING INFORMATION
Part Number
Versions
Description
UC1682xHCZ
Gold Bumped Die with PI
Without OTP option
UC1682tHCZ
UC1682xFBZ
UC1682tFBZ
Gold Bumped Die with PI
With OTP option
Without OTP option
with OTP option
COF
COF
Convention note:
Grayed-out contents are functions not available yet.
2
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
General Notes
APPLICATION INFORMATION
For improved readability, the specification contains many application data points. When application information is given, it
is advisory and does not form part of the specification for the device.
BARE DIE DISCLAIMER
All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of
ninety (90) days from the date of UltraChip’s delivery. There is no post waffle saw/pack testing performed on individual die.
Although the latest processes are utilized for wafer sawing and die pick-&-place into waffle pack carriers, UltraChip has no
control of third party procedures in the handling, packing or assembly of the die. Accordingly, it is the responsibility of the
customer to test and qualify their applications in which the die is to be used. UltraChip assumes no liability for device
functionality or performance of the die or systems after handling, packing or assembly of the die.
OTP CELL LIGHT SENSITIVITY
The OTP memory cell is sensitive to photon excitation. Under extended exposure to strong ambient light, the OTP cells
can lose its content before the specified memory retention time span. The system designer is advised to provide proper
light shields to realize full OTP content retention performance.
LIFE SUPPORT APPLICATIONS
These devices are not designed for use in life support appliances, or systems where malfunction of these products can
reasonably be expected to result in personal injuries. Customer using or selling these products for use in such
applications do so at their own risk.
Revision 0.6
3
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
BLOCK DIAGRAM
COLUMN ADDRESS GENERATOR
DISPLAY DATA RAM
POWER-ON
& RESET
CONTROL
CLOCK &
TIMING
GEN.
CONTROL &
STATUS
REGISTER
DISPLAY DATA LATCHES
LEVEL SHIFTERS
VLCD & BIAS
COMMAND
CL
GENERATOR
SEG DRIVERS
HOST INTERFACE
CB1
CB0
4
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
PIN DESCRIPTION
Name
Type
Pins
Description
MAIN POWER SUPPLY
V
DD2/VDD3 is the analog power supply and it should be connected to the
same power source. VDD is the digital power supply and it should be
VDD
VDD2
VDD3
connected to a voltage source that is no higher than VDD2/VDD3
.
PWR
GND
Please maintain the following relationship:
V
DD+1V ꢀ VDD2/3 ꢀ VDD.
"Minimize the trace resistance for VDD and VDD2/VDD3
Ground. Connect VSS and VSS2 to the shared GND pin.
Minimize the trace resistance for this node.
.
VSS
VSS2
LCD POWER SUPPLY & VOLTAGE CONTROL
This is the reference voltage to generate the actual SEG driving voltage.
V
BIAS can be used to fine tune VLCD by external variable resistors.
Internal resistor network has been provided to simplify external trimming
circuit. The following network is sufficient for most applications.
330K
VDD2/ VDD3
VBIAS
1M/VR
VBIAS
I
An internal RC filter is provided to filter noise on the VBIAS pin. When not
used, it is OK to leave VBIAS open circuit. If noise starts to cause
problem, connect a small bypass capacitor between VBIAS and VSS
.
In the OTP version, this pin is disconnected from internal circuit. So,
there is no need to add bypass capacitor for this pin for OTP version.
LCD Bias Voltages. These are the voltage sources to provide SEG
driving currents. These voltages are generated internally. Connect
capacitors of CBX value between VBX+ and VBX–
.
VB1+ VB1–
VB0+ VB0–
PWR
The resistance of these traces directly affects the driving strength of
SEG electrodes and impacts the image of the LCD module. Minimize
the trace resistance is critical in achieving high quality image.
SB1+ SB1–
SB0+ SB0–
Wire to corresponding VB1/2x pin. Merge ITO traces between
corresponding SBx and VBx in COG.
I
High voltage LCD Power Supply. Connect these pins together.
VLCD-IN
PWR
By-pass capacitor CL is optional. It can be connected between VLCD and
VLCD-OUT
VSS. When CL is used, keep the trace resistance under 300 Ω.
NOTE
•
Recommended capacitor values:
CB: 150~250x LCD load capacitance or 2.2µF (2V), whichever is higher.
CL: (Optional) 5nF~50nF (16V) is appropriate for most applications.
Revision 0.6
5
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
Name
Type
Pins
Description
HOST INTERFACE
Bus mode: The interface bus mode is determined by BM[1:0] and D[7:6]
by the following relationship:
BM[1:0]
11
D[7:6]
Data
Data
0X
Mode
6800/8-bit
8080/8-bit
6800/4-bit
8080/4-bit
10
01
00
BM0
BM1
I
0X
01
10
3-wire SPI w/ 9-bit token
(S9: conventional)
00
00
10
11
4-wire SPI w/ 8-bit token
(S8: conventional)
3/4-wire SPI w/ 8-bit token
(S8uc: Ultra-Compact)
CS1
CS0
Chip Select. Chip is selected when CS1=”H” and CS0 = “L”. When the
chip is not selected, D[7:0] will be high impedance.
When RST=”L”, all control registers are re-initialized by their default states.
Since UC1682 has built-in Power-ON Reset and Software Reset
command, RST pin is not required for proper chip operation.
I
I
2
RST
An RC Filter has been included on-chip. There is no need for external RC
noise filter. When RST is not used, connect the pin to VDD
.
Select Control data or Display data for read/write operation. In S9 modes,
CD pin is not used. Connect CD to VSS when not used.
CD
ID
I
I
”L”: Control data
”H”: Display data
ID pin is for production control. The connection will affect the content of
D[7] when using Get Status command. Connect to VDD for “H” or VSS for
“L”.
WR[1:0] controls the read/write operation of the host interface. See Host
Interface section for more detail.
WR0
WR1
I
In parallel mode, WR[1:0] meaning depends on whether the interface is in
the 6800 mode or the 8080 mode. In serial interface modes, these two
pins are not used, connect them to VSS
.
Bi-directional bus for both serial and parallel host interfaces.
In serial modes, connect D[0] to SCK, D[3] to SDA,
BM=0x
BM=01
BM=1x
BM=00
(Parallel)
(Parallel)
(S8/S8uc)
(S9)
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0/D4
SCK
SCK
D1/D5
–
–
–
–
D0~D7
I/O
D2/D6
D3/D7
SDA
–
SDA
–
–
–
0
–
–
–
S8/S8uc
1
0
1
Connect unused pins to VSS
.
6
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
Name
Type
Pins
Description
HIGH VOLTAGE LCD DRIVER OUTPUT
SEG1 ~
SEG312
SEG (column) driver outputs. Support up to 104 x RGB pixels.
Leave unused drivers open-circuit.
HV
COM (row) driver outputs. Support up to 80 rows. Leave unused COM
drivers open-circuit.
COM1 ~
COM80
HV
When designing LCM, always start from COM1. If the LCM has N pixel
rows and N is less than 80, set CEN to be N-1, and leave COM drivers
[N+1 ~ 80] open-circuit.
MISC. PINS
Auxiliary VDD. These pins are connected to the main VDD bus on chip. They
are provided to facilitate chip configurations in COG and COF applications.
These pins should not be used to provide VDD power to the chip. It is not
necessary to connect VDDX to main VDD externally.
VDDX
O
Test control. This pin has on-chip pull-up/down resistor. Leave it open
during normal operation.
TST4
I/HV
TST4 is also used as one of the high voltage programming power supply
for OTP operation. For COG design with OTP options, please wire out
TST4 with an ITO trace resistance of 200 Ω or less.
TST2
TP[5:1]
I/O
I
Test I/O pins. Leave these pins open during normal use.
Test control. Leave these pins open during normal use.
Note: Several control registers will specify “0 based index” for COM and SEG electrodes. In those
situations, COMX or SEGX will correspond to index X-1, and the value ranges for those index
registers will be 0~79 for COM and 0~311 for SEG.
Revision 0.6
7
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
RECOMMENDED COG LAYOUT
Users can use either OTP control (through TST4 pin) or external circuit (through VBIAS pin) to fine tune VLCD.
Please refer to the following figures:
FIGURE 1: Example for TST4 COG layout when using OTP control to fine tune VLCD
FIGURE 2: Example for VBIAS COG layout when using external circuit to fine tune VLCD
8
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
REFERENCE COG LAYOUT
COM_pad<50>
COM_pad<52>
SEG_pad<312>
SEG_pad<311>
NC
D7
D6
COM_pad<78>
COM_pad<80>
D5
D7
VDDX
D6
D4
D3
D2
D1
D5
D4
D3
D2
D1
D0
D0
VREF
RST_
CS1
VDDX
CS0
CD
RST
CS0
CD
WR0
VDDX
WR1
BM0
WR0
WR1
TST4
VSS
VSS
VSS
VSS
VSS
VDDX
BM1
TST4
TST4
TST3
TST2
~
~
~
~
~
VSS2
VSS2
VSS2
VSS2
VSS2
TST1
PRG3
PRG2
PRG1
SEG_pad<196>
SEG_pad<195>
SEG_pad<194>
ID
VSS
VSS
VSS
VSS
VSS
VSS
VSS2
VSS2
VSS2
VSS2
VSS2
VDD3
VDD3
VDD3
VDD3
VDD ~ VDD3
VDD ~ VDD3
VDD ~ VDD3
VDD ~ VDD3
VDD ~ VDD3
VB0+ ~ SB0+
VB0+ ~ SB0+
VB0+ ~ SB0+
VB1+ ~ SB1+
VB1+ ~ SB1+
VB1+ ~ SB1+
VB1- ~ SB1-
VB1- ~ SB1-
VB1- ~ SB1-
VB1- ~ SB1-
VB0- ~ SB0-
VB0- ~ SB0-
VB0- ~ SB0-
VB0- ~ SB0-
VLCD
VDD2
VDD2
VDD2
VDD2
VDD2
VDD
VDD
VDD
VDD
VDD
VDD
VB0P
VB0P
VB0P
VB0P
VB0P
VB0P
VB0P
VB0P
VB0P
VB0P_S
VB1P
VB1P
VB1P
VB1P
VB1P
VB1P
VB1P
VB1P
VB1P
VB1P_S
VB1N
VB1N
VB1N
VB1N
VB1N
VB1N
VB1N
VB1N
VB1N
VB1N_S
SEG_pad<62>
SEG_pad<61>
VB0N
VB0N
VB0N
VB0N
VB0N
SEG_pad<60>
SEG_pad<59>
VB0N
VB0N
VB0N
VB0N
VB0N_S
VLCDIN
VLCDIN
VLCDOUT
VLCDOUT
VLCD
COM_pad<79>
COM_pad<77>
NC
COM_pad<51>
COM_pad<49>
SEG_pad<2>
SEG_pad<1>
Notes for VDD with COG:
The VDD=1.8V-typ operation condition of UC1682 should be met under all LCM formats. Unless VDD, VDD2/3
ITO trances can each be controlled to be 5 Ω or lower, otherwise VDD-VDD2/3 separation can cause the actual
on-chip VDD to drop below VDD=1.7V during high speed data write condition. Therefore, for COG, VDD-VDD2/3
separation is not suitable for pure ITO based COG designs.
Revision 0.6
9
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
CONTROL REGISTERS
UC1682 contains registers which control the chip operation. These registers can be modified by commands.
The following table is a summary of the control registers, their meanings and their default values.
Commands supported by UC1682 will be described in the next two sections. First, a summary table,
followed by a detailed instruction-by-instruction description.
Name:
The Symbolic reference of the register.
Note that, some symbol name refers to bits (flags) within another register.
Default: Numbers shown in Bold font are default values after Power-Up-Reset and System-Reset.
Name
Bits
Default
Description
SL
7
0H
Scroll Line. Scroll the displayed image up by SL rows. The valid SL value is
between 0 (for no scrolling) and (79– 2xFL). Setting SL outside of this range
causes undefined effect on the displayed image.
FL
4
0H
Fixed Lines. The first FLx2 lines of each frame are fixed and are not
affected by scrolling (SL). When FL is non-zero, the screen is effectively
separated into two regions: one scrollable, one non-scrollable.
When partial display mode is activated, the display of these 2xFL lines is
also controlled by LC[0].
CR
CA
7
7
0H
0H
Return Column Address. Useful for cursor implementation.
Display Data RAM Column Address (counted in RGB triplet)
(Used in Host to Display Data RAM access)
RA
BR
7
2
0H
3H
Display Data RAM Row Address
(Used in Host to Display Data RAM access)
Bias Ratio. The ratio between VLCD and VBIAS
.
00b: 5
10b: 8
01b:
7
11b: 9
TC
2
0H
Temperature Compensation (per oC)
00b: -0.05%
01b: -0.10%
11b: -0.20%
10b: -0.15%
PM
PMO
8
6
55H
20H
Electronic Potentiometer to fine tune VBIAS and VLCD
PM offset. The effective PM value PMV = PM+PMO-32. Make sure PMV
formula does not overflow or underflow. (Available only on OTP version).
OM
2
–
Operating Modes (Read only)
10b: Sleep
11b: Normal
00b: Reset
01b: (Not used)
ID
MSK
1
3
PIN
0H
Access the connected status of ID pin.
R/G/B Write Data mask bits MSK[2:0] = {MR, MG, MB} (Default: 000b)
0: Write
1: Block
RS
PC
1
4
Reset in progress. Host Interface not ready
Power Control.
DH
PC[1:0]: 00b: LCD: ꢁ 9nF
01b: LCD: 9~12nF
10b: LCD: 12~16nF
11b: LCD: 16~22nF
PC[3:2]: 00b: External VLCD
11b: Internal VLCD (Standard)
10
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
Name
Bits
Default
Description
DC
5
18H
Display Control:
DC[0]: PXV: Pixels Inverse. Bit-wise data inversion. (Default 0: OFF)
DC[1]: APO: All Pixels ON (Default 0: OFF)
DC[2]: Display ON/OFF (Default 0: OFF)
DC[3]: Gray-shade Modulation mode.
0: 8-shade mode
1: 32-shade Mode
DC[4]: Dither Function Control.
0: Disable Dither Function 1: Enable Dither Function
AC
5
1H
Address Control:
AC[0]: WA: Automatic column/row Wrap Around (Default 1: ON)
AC[1]: Auto-Increment order
0: Column (CA) first
1: Row (RA) first
AC[2]: RID: RA (row address) auto increment direction (L:+1 H:-1)
AC[3]: CUM: Cursor update mode, (Default 0: OFF)
when CUM=1, CA increment on write only, wrap around suspended
AC[4] : Window Program Enable
0 : Disable
1 : Enable
WPC0
WPP0
WPC1
WPP1
8
8
8
8
00H
00H
67H
4FH
Window program starting column address. Value range: 0 ~103.
Window program starting row address. Value range: 0~79.
Window program ending column address. Value range: 0~103.
Window program ending row address. Value range: 0~79.
For OTP version IC, register WPC[1:0] and WPP[1:0] are also used to
control the OTP operation (when OTPC[3]=1).
OTP operation
CEN
DST
DEN
7
7
7
4FH
COM scanning end (last COM with full line cycle, 0 based index)
Display start (first COM with active scan pulse, 0 based index)
Display end (last COM with active scan pulse, 0 based index)
00H
4FH
Please maintain the following relationship:
CEN = the actual number of pixel rows on the LCD - 1
CEN ꢀ DEN ꢀ DST+ 9
Revision 0.6
11
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
Name
Bits
Default
Description
LC
10
090H
LCD Control:
LC[0]: Enable the first FLx2 lines in partial display mode (Default OFF).
LC[1]: MX, Mirror X. SEG/Column sequence inversion (Default: OFF)
LC[2]: MY, Mirror Y. COM/Row sequence inversion (Default: OFF)
LC[4:3]: Line Rate (Klps: Kilo-Line-per-second)
00b: 10.0 Klps
01b: 12.8 Klps
11b: 20.0 Klps
10b: 16.0 Klps
(Frame-Rate = Line-Rate / Mux-Rate)
LC[5] : RGB filter order (as mapped to SEG1, SEG2, SEG3)
0 : BGR-BGR
1 : RGB-RGB
LC[7:6] : Color and input mode
for Dither-Enabled:
00b : 256 color mode.
3R-3G-2B (8-bit/RGB)
4R-4G-4B (12-bit/RGB)
01b : 4K color mode.
10b : 56K color mode. 5R-6G-5B (16-bit/RGB)
11b : 221K color mode. 6R-7G-5B (24-bit/RGB)
for Dither-Disabled:
00b : 256 color mode.
01b : 4K color mode.
10b : 4K color mode.
11b : 4K color mode.
3R-3G-2B (8-bit/RGB)
4R-5G-3B (12-bit/RGB)
5R-6G-5B (16-bit/RGB)
6R-7G-5B (24-bit/RGB)
For data over 4R-5G-3B, each redundant LSB of each color will be
truncated. (Example:
For R4R3R2R1R0 - G5G4G3G2G1G0 - B4B3B2B1B0,
R0, G0, B1, and B0 will be truncated.)
LC[9:8] : Partial Display Control
0xb: Disable
10b: Enabled
11b: Enabled
Mux-Rate = CEN+1 (DST, DEN not used)
Mux-Rate = CEN+1
Mux-Rate = DEN-DST+1+LC[0]x2xFL
APC0
APC1
OD
OS
WS
OTPC
5
8
1
1
1
6
0DH
36H
–
–
–
10H
Advanced Program Control. For UltraChip only. Please do not use.
OTP option flag 0: No OTP 1: With OTP
OTP programming in-progress
OTP Command Succeeded
OTP Programming Control:
OTP0[2:0] : OTP command
000 : Sleep
001 : Read
010 : Erase
011 : Program
1XX : For UltraChip use only
OTP[3] : OTP Enable ( auto clear after OTP command action done )
OTP[4] : Use/Ignore OTP value. 0: Ignore
OTP[5] : OTP Command enable
OTP Write Mask
1: Normal
OTPM
8
00H
12
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
COMMAND TABLE
The following is a list of host commands supported by UC1682
C/D: 0: Control,
1: Data
W/R: 0: Write Cycle,
1: Read Cycle
#
–
Useful Data bits
Don’t Care
Command
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Action
Default
1
2
3
Write Data Byte
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
Write 1 byte
Read 1 byte
Get Status
Set CA[3:0]
Set CA[6:4]
Set TC[1:0]
Set PC[1:0]
Set PC[3:2]
N/A
N/A
N/A
0
Read Data Byte
Get Status
ID MX MY WA DE WS OD OS
Set Column Address LSB
Set Column Address MSB
Set Temp. Compensation
Set Panel Loading
Set Pump Control
0
0
0
0
0
0
#
0
0
0
0
0
0
0
0
0
0
#
1
1
1
1
0
0
1
1
1
1
#
0
0
1
1
0
1
0
0
0
1
#
0
1
0
1
#
-
#
#
1
0
1
0
#
#
#
#
#
#
#
#
#
#
0
#
#
#
#
#
#
#
#
#
#
R
#
#
#
#
#
4
0
5
6
7
0
1
1
0
#
#
-
0
1
11b
Set Adv. Program Control
Set APC[R][7:0],
8
N/A
(double byte command)
R = 0, or 1
Set Scroll Line LSB
Set Scroll Line MSB
Set Row Address LSB
Set Row Address MSB
Set SL[3:0]
Set SL[6:4]
Set RA[3:0]
Set RA[6:4]
0
0
0
0
9
#
-
10
11
Set VBIAS Potentiometer
0
0
1
0
0
0
0
0
0
1
Set PM[7:0]
55H
(double-byte command)
0
0
#
#
#
#
#
#
#
#
12 Set Partial Display Control
13 Set RAM Address Control
14 Set Fixed Lines
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
1
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
1
#
0
0
0
1
0
0
0
0
0
0
0
1
#
#
0
1
1
#
#
#
0
1
0
0
1
#
#
#
#
0
1
#
#
#
0
#
1
1
#
#
#
#
#
#
#
#
#
#
#
0
1
Set LC[9:8]
Set AC[2:0]
Set FL[3:0]
Set LC[4:3]
Set DC[1]
0: Disable
001b
0
15 Set Line Rate
10b
16 Set All-Pixel-ON
17 Set Inverse Display
18 Set Display Enable
19 Set Color Mask
0
Set DC[0]
0
110b
0
Set DC[4:2]
Set MSK[2:0]
Set LC[2:0]
Set LC[5]
Set LC[7:6]
System Reset
No operation
20 Set LCD Mapping Control
21 Set Color Pattern
22 Set Color Mode
23 System Reset
0
0 (BGR)
10b (56K)
N/A
24 NOP
N/A
TT
Set Test Control
For testing only.
25
N/A
(double byte command)
Do not use.
0
0
0
0
0
0
0
0
0
0
0
0
#
1
1
1
1
-
#
1
1
1
1
#
#
1
1
1
1
#
#
0
0
0
1
#
#
1
1
1
0
#
#
0
1
1
0
#
#
#
1
1
#
#
0
1
26 Set LCD Bias Ratio
27 Reset Cursor Update Mode
28 Set Cursor Update Mode
Set BR[1:0]
AC[3]=0, CA=CR
AC[3]=1, CR=CA
11b: 9
AC[3]=0
AC[3]=1
0
1
29 Set COM End
Set CEN[6:0]
Set DST[6:0]
Set DEN[6:0]
Set WPC0[7:0]
Set WPP0[7:0]
Set WPC1[7:0]
79
#
#
0
0
1
1
1
1
0
0
1
#
0
#
30 Set Partial Display Start
31 Set Partial Display End
0
0
0
-
#
#
#
#
#
0
0
0
0
1
-
1
#
1
#
1
#
1
#
1
#
0
#
0
#
1
1
79
0
#
#
0
0
0
0
0
0
0
0
1
#
1
#
1
#
1
#
1
#
1
#
0
#
0
#
1
#
1
#
0
#
0
#
Set Window Program
32
Starting Column Address
0
1
Set Window Programming
33
0
#
#
Starting Row Address
Set Window Programming
0
0
1
1
1
1
0
1
1
#
0
#
34
103
Ending Column Address
0
0
#
#
#
#
#
#
0
0
0
0
1
#
1
#
1
1
#
1
#
0
#
1
#
1
1
Set Window Programming
35
Set WPP1[7:0]
Set AC[4]
79
#
#
Ending Row Address
36 Enable window program
0
0
1
1
1
1
0
0
#
0: Disable
* Other than commands listed above, all other bit patterns may result in undefined behavior.
Revision 0.6
13
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
OTP Command
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Action
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
#
1
#
1
#
1
#
1
#
1
#
1
#
1
#
1
#
1
#
0
#
0
#
0
#
0
#
1
#
1
#
0
#
0
#
0
#
1
#
37 Set OTP Operation control
Set OTP0[5:0]
Set OTP1[7:0]
0
0
-
-
1
#
1
#
1
#
0
#
1
#
1
#
38 Set OTP Write Mask
39 Set VOTP1 Potentiometer
40 Set VOTP2 Potentiometer
41 Set OTP Write Timer
42 Set OTP Read Timer
0
0
#
0
#
#
1
#
Shared with
Window
N/A
Programming
commands
1
1
1
1
0
1
1
0
#
#
#
1
#
#
1
#
#
0
#
#
1
#
#
#
1
#
1
#
1
#
1
#
•
Other than commands listed above, all other bit patterns may result in undefined behavior.
•
•
The OTP commands listed above should only be used with OTP version of UC1682.
Command 39~42 are shared with command 32~35, and they have exactly the same code. The
interpretation of these four commands depends on register OTPC[3]. When OTPC[3]=0, they are
interpreted as Window Programming commands. When OTPC[3]=1, they are OTP Control
commands.
•
•
OTPM and PM are actually the same register. The usage of this register is determined by OTPC[3] in
similar ways as Command 39~42.
After OTP-ERASE or OTP-PROGRAM operation (Set OTPC[3]=1) , always
a) remove TST4 power source;
b) Do a full Vdd ON-OFF cycle; before resuming normal operation.
14
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
COMMAND DESCRIPTION
(1) WRITE DATA TO DISPLAY MEMORY
Action
Write data
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
8bits data write to SRAM
1
0
UC1682 will convert input RAM data to 12-bits of RGB data. Please refer to command (22) Set Color Mode
for detail data write sequence. The format of 12 bits RGB data is as following:
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R
G
B
(2) READ DATA FROM DISPLAY MEMORY
Action
Read data
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
8bits data from SRAM
1
1
Each RGB triplet is stored as 12-bit in the display RAM. Each 12 bits RGB data takes 2 RAM read cycles.
The data read will start with the high byte D[11:4] and then low byte {D[3:0],4’b0000}. The read out RGB
data is after-dither for 56K color and 221K color mode and after-extension for 256 color mode.
R3
R2
R1
R0
G4
G3
G2
G1
G0
B2
B1
B0
0
0
0
0
1st Read
2nd Read
Write/Read Data Byte (command 1/2) operation uses internal Row Address register (RA) and Column
Address register (CA). RA and CA can be programmed by issuing Set Row Address and Set Column
Address commands. If wrap-around (WA, AC[0]) is OFF (0), CA will stop incrementing after reaching the CA
boundary, and system programmers need to set the values of RA and CA explicitly. If WA is ON (1), when
CA reaches end of column address, CA will be reset to 0 and RA will be increased or decreased, depending
on the setting of Row Increment Direction (RID, AC[2]). When RA reaches the boundary of RAM (i.e. RA = 0
or 79), RA will be wrapped around to the other end of RAM and continue.
(3) GET STATUS
Action
Get Status
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
ID MX MY WA DE WS OD OS
0
1
Status flag definitions:
ID: Provide access to ID pin connection status.
MX: Status of register LC[1], mirror X.
MY: Status of register LC[2], mirror Y.
WA: Status of register AC[0]. Automatic column/row wrap around.
DE: Display enable flag. DE=1 when display is enabled
WS : OTP Command Succeeded
OD: OTP Option (Yes/No)
OS : OTP action status
(4) SET COLUMN ADDRESS
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set Column Address LSB CA[3:0]
Set Column Address MSB CA[6:4]
0
0
0
0
0
0
0
0
0
0
0
1
CA3 CA2 CA1 CA0
-
CA6 CA5 CA4
Set SRAM column address for read/write access. CA is counted in RGB triplets, not individual SEG
electrode.
CA value range: 0~103
Revision 0.6
15
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
(5) SET TEMPERATURE COMPENSATION
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
TC1 TC0
Set Temperature Comp. TC[1:0]
0
0
0
0
1
0
0
1
Set VBIAS temperature compensation coefficient (%-per-degree-C)
Temperature compensation curve definition:
00b= -0.05%/oC
01b= -0.10%/oC
10b= -0.15%/oC
11b= -0.20%/oC
(6) SET PANEL LOADING
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set Panel Loading PC[1:0]
0
0
0
0
1
0
1
0
PC1 PC0
Set PC[1:0] according to the capacitance loading of LCD panel.
Panel loading definition: 00b ꢁ9nF
01b= 9~12nF
10b= 12~16nF
11b= 16~22nF
(7) SET PUMP CONTROL
Action
Set Pump Control PC[3:2]
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
PC3 PC2
0
0
0
0
1
0
1
1
Set PC[3:2] to program the build-in charge pump stages.
Pump control definition:
00b=External VLCD
11b= Internal VLCD (standard)
(8) SET ADVANCED PROGRAM CONTROL
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set APC[1:0]
(Double byte command)
0
0
0
0
0
0
1
1
0
0
0
R
APC register parameter
For UltraChip only. Please do NOT use.
(9) SET SCROLL LINE
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set Scroll Line LSB SL[3:0]
Set Scroll Line MSB SL[6:4]
Set the scroll line number.
0
0
0
0
0
0
1
1
0
0
0
1
SL3 SL2 SL1 SL0
-
SL6 SL5 SL4
Scroll line setting will scroll the displayed image up by SL rows. The valid value for SL is between 0 (no
scrolling) and (79-2xFL). FL is the register value programmed by Set Fixed Lines command.
Image row 0
……….
Image row N
……….
Image row N
Image row 79
Image row 0
………
……….
Image row N-1
Image row 79
SL=0
SL=N
16
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
(10) SET ROW ADDRESS
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set Row Address LSB RA [3:0]
Set Row Address MSB RA [6:4]
Set SRAM row address for read/write access.
0
0
0
0
0
0
1
1
1
1
0
1
RA3 RA2 RA1 RA0
-
RA6 RA5 RA4
Possible value = 0~79
(11) SET VBIAS POTENTIOMETER
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set VBIAS Potentiometer. PM [7:0]
0
0
0
0
1
0
0
0
0
0
0
1
(Double byte command)
PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0
Program VBIAS Potentiometer (PM[7:0]). See section LCD VOLTAGE SETTING for more detail.
Effective range: 0 ~ 255
(12) SET PARTIAL DISPLAY CONTROL
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
LC9 LC8
Set Partial Display Enable LC [9:8]
0
0
1
0
0
0
0
1
This command is used to enable partial display function.
LC[9:8] : 0Xb: Disable Partial Display, Mux-Rate = CEN+1 (DST, DEN not used.)
10b: Enable Partial Display, Mux-Rate = CEN+1
11b: Enable Partial Display, Mux-Rate = DEN-DST+1+LC[0]x2xFL
(13) SET RAM ADDRESS CONTROL
Action
Set AC [2:0]
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
AC2 AC1 AC0
0
0
1
0
0
0
1
Program registers AC[2:0] for RAM address control.
AC[0]: WA, Automatic column/row wrap around.
0: CA or RA (depends on AC[1]= 0 or 1) will stop incrementing after reaching boundary
1: CA or RA (depends on AC[1]= 0 or 1) will restart, and RA or CA will increment by one step.
AC[1]: Auto-Increment order
0 : column (CA) increment (+1) first until CA reaches CA boundary, then RA will increment by (+/-1).
1 : row (RA) increment (+/-1) first until RA reach RA boundary, then CA will increment by (+1).
AC[2]: RID, row address (RA) auto increment direction ( 0/1 = +/- 1 )
When WA=1 and CA reaches CA boundary, RID controls whether row address will be adjusted by
+1 or -1.
AC[2:0] controls the auto-increment behavior of CA and RA. When Window Program is enabled (AC[4]=ON),
see command description (32) ~ (36) for more details. If WPC[1:0] and WPP[1:0] values are the default
values, the behavior of CA, RA auto-increment will be the same, no matter what the setting of AC[4] is.
Revision 0.6
17
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
(14) SET FIXED LINES
Action
Set Fixed Lines FL [3:0]
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
FL3 FL2 FL1 FL0
0
0
1
0
0
1
The fixed line function is used to implement the partial scroll function by dividing the screen into scroll and
fixed area. Set Fixed Lines command will define the fixed area, which will not be affected by the SL scroll
function. The fixed area covers the top 2xFL rows for mirror Y (MY) is 0 and bottom 2xFL rows for MY=1.
One example of the visual effect on LCD is illustrated in the figure below.
Fixed Area
1
Scroll Area
1
Fixed Area
(2xFL)
Scroll Area
MY = 0
80
80
MY = 1
When partial display mode is activated, the display of these 2xFL lines is also controlled by LC[0]. ]. Before
turning on LC[0], please make sure
MY=0 DST >= FLx2
DEN <= CEN.
MY=1 DST >= 0
DEN <= CEN-FLx2
(15) SET LINE RATE
Action
Set Line Rate LC [4:3]
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
LC4 LC3
0
0
1
0
1
0
0
0
Program LC [4:3] for line rate setting (Frame-Rate = Line-Rate / Mux-Rate). The line rate is automatically
scaled down by 1/2 and 1/3 at Mux-Rate = 38 and 24.
The following are line rates at Mux Rate = 39 ~ 80.
00b: 10.0 Klps 01b: 12.8 klps
(Klps: Kilo-Line-per-second)
10b: 16.0 Klps 11b: 20.0 Klps
(16) SET ALL PIXEL ON
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set All Pixel ON DC [1]
0
0
1
0
1
0
0
1
0
DC1
Set DC[1] to force all SEG drivers to output ON signals. This function has no effect on the existing data
stored in display RAM.
(17) SET INVERSE DISPLAY
Action
Set Inverse Display DC [0]
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
DC0
0
0
1
0
1
0
0
1
1
Set DC[0] to force all SEG drivers to output the inverse of the data (bit-wise) stored in display RAM. This
function has no effect on the existing data stored in display RAM.
18
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
(18) SET DISPLAY ENABLE
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
DC4 DC3 DC2
Set Display Enable DC [4:2]
0
0
1
0
1
0
1
This command is for programming register DC[4:2].
When DC[2] is set to 0, the IC will put itself into Sleep mode. All drivers, voltage generation circuit and timing
circuit will be halted to conserve power. When DC[2] is set to 1, UC1682 will first exit from Sleep mode,
restore the power and then turn on COM drivers and SEG drivers. There is no other explicit user action or
timing sequence required to enter or exit the Sleep mode.
DC[3] controls the gray shade modulation modes. UC1682 has two gray shade modulation modes: an 8-
sahde mode and a 32-shade mode. The modulation curves are shown below. Horizontal axes are the gray
shade data. The vertical axes are the ON-OFF ratio. 9/9 is 100% ON for 8-shade mode, 51/51 is 100% ON
for 32-shade mode.
9
50
45
40
35
6
30
25
20
3
15
10
5
0
0
1
2
3
4
5
6
7
8
1
4
7
10 13 16 19 22 25 28 31
DC[4] enables dither function. Refer to (22) Set Color Mode for more information.
0b: Disable 1b: Enable
Revision 0.6
19
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
(19) SET COLOR MASK
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
MSK[2:0]
Set Color Mask MSK [2:0]
0
0
1
0
1
1
0
This command is used for program MSK[2:0] which will control whether the input RGB data will be blocked
from updating RGB data in the RAM. (1: Block, 0: Normal. MSK[2:0] = {MSK_R, MSK_G, MSK_B})
Example: Let color mode = 256 color, MSK[2:0] = 100b (MSK_R = 1, MSK_G = 0, MSK_B = 0). There is one
pixel to be updated, and the original data for the pixel is 11100110b (RRR-GGG-BB). Suppose the new input
RGB data is 00000000b, since R is masked, the data for the pixel would be updated as 11100000b.
(20) SET LCD MAPPING CONTROL
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
MY MX LC0
Set LCD Mapping Control LC [2:0]
0
0
1
1
0
0
0
This command is used for program LC[2:0] for COM (row) mirror (MY), SEG (column) mirror (MX).
LC[2] controls Mirror Y (MY): MY is implemented by reversing the mapping order between RAM and
COM electrodes. The data stored in RAM is not affected by MY command. MY will have immediate effect on
the display image.
LC[1] controls Mirror X (MX): MX is implemented by selecting the CA or 103-CA as write/read (from host
interface) display RAM column address so this function will only take effect after rewriting the RAM data.
LC[0] controls whether the soft icon section (0~ 2xFL) is display or not during partial display mode.
(21) SET COLOR PATTERN
Action
Set Color Pattern LC [5]
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
LC5
0
0
1
1
0
1
0
0
0
UC1682 supports on-chip swapping of RÙB data mapping to the SEG drivers.
SEG304 SEG311 SEG312
LC[5]
0
1
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6
…
…
…
B
R
G
G
R
B
B
R
G
G
R
B
B
R
G
G
R
B
The definition of R/G/B input data is determined by LC[7:6], as described in Set Color Mode below.
20
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
(22) SET COLOR MODE
Action
Set Color Mode LC [7:6]
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
LC7 LC6
0
0
1
1
0
1
0
1
Program color mode and RGB input pattern. Color mode (LC[7:6]) definition:
Dither Options:
DC[4]=1b enables dither function. Refer to (18) Set Display Enable for more information.
LC[7:6] = 00b ( RRR-GGG-BB, 256 color )
One byte of input data is extended and stored to 12 RAM bits.
Data Write Sequence
D[7:0]
R2
1st Byte Write Data
R1
R0
G2
G1
G0
B1
B0
LC[7:6] = 01b ( RRRR-GGGG-BBBB, 4K color )
1-bit extension for G, 1-bit dither for B. 12 bits of input data is stored to 12 RAM bits.
3 bytes of input data will be merged into 2 sets of RGB data.
Data Write Sequence
1st Byte Write Data
2nd Byte Write Data
3rd Byte Write Data
D[7:0]
R3
B3
R2
B2
G2
R1
B1
G1
R0
B0
G0
G3
R3
B3
G2
R2
B2
G1
R1
B1
G0
R0
B0
G3
LC[7:6] = 10b ( RRRRR-GGGGGG-BBBBB, 56K color )
1-bit dither for R/G, 2-bit dither for B. 16 bits input data dithered to 12 RAM bits.
Data Write Sequence
1st Byte Write Data
2nd Byte Write Data
D[7:0]
R4
G2
R3
G1
R2
G0
R1
B4
R0
B3
G5
B2
G4
B1
G3
B0
LC[7:6] = 11b ( RRRRRR-GGGGGGG-BBBBB, 221K color )
2-bit dither per color. 18 out of 24 bits input data is dithered to 12 RAM bits.
Data Write Sequence
1st Byte Write Data
2nd Byte Write Data
3rd Byte Write Data
D[7:0]
R5
G6
R4
G5
B3
R3
G4
B2
R2
G3
B1
R1
G2
B0
R0
G1
--
--
G0
--
--
--
--
B4
Data Read Sequence
for LC[7:6] = 0.
Data Read Sequence
D[7:0]
R2
GM1
1st Byte Read Data
2nd Byte Read Data
R1
B2
R0
B1
RM
B0
G2
0
G1
0
G0 GM2
0
0
R/G/B: the input Red/Green/Blue data.
R/GMN: the Red/Green bits mapped from RGB input data.
for LC[7:6] = 1, 2, 3.
Data Read Sequence
1st Byte Read Data
2nd Byte Read Data
D[7:0]
RD3 RD2 RD1 RD0 GD4 GD3 GD2 GD1
GD0 BD2 BD1 BD0
0
0
0
0
R/G/BDN : the N-th bit of after-dither Red/Green/Blue input data
Note:
For system designers who want to use their own dithering algorithm, please set LC[7:6] = 10b (56k
color mode) and use the following input pattern to bypass on-chip dithering algorithm:
R3-R2-R1-R0-1-G4-G3-G2-G1-G0-1-B2-B1-B0-1-0
Revision 0.6
21
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
No-Dither Options:
DC[4]=0b disables dither function. Refer to (18) Set Display Enable for more information.
LC[7:6] = 00b ( RRR-GGG-BB, 256 color )
One byte of input data is extended and stored to 12 RAM bits.
Data Write Sequence
D[7:0]
R2
1st Byte Write Data
R1
R0
G2
G1
G0
B1
B0
LC[7:6] = 01b ( RRRR-GGGGG-BBB, 4K color )
12 bits of input data is stored to 12 RAM bits. 3 bytes of input data will be merged into 2 sets of RGB
data.
Data Write Sequence
1st Byte Write Data
2nd Byte Write Data
3rd Byte Write Data
D[7:0]
R3
G0
R2
B2
G3
R1
B1
G2
R0
B0
G1
G4
R3
G0
G3
R2
B2
G2
R1
B1
G1
R0
B0
G4
LC[7:6] = 10b ( RRRRR-GGGGGG-BBBBB, 56K color )
1-bit truncation for R/G, 2-bit for B. 16 bits input data truncated to 12 RAM bits.
Data Write Sequence
1st Byte Write Data
2nd Byte Write Data
D[7:0]
R4
G2
R3
G1
R2
G0
R1
B4
R0
B3
G5
B2
G4
B1
G3
B0
LC[7:6] = 11b ( RRRRRR-GGGGGGG-BBBBB, 221K color )
2-bit truncation for per color. 18 out of 24 bits input data is truncated to 12 RAM bits.
Data Write Sequence
1st Byte Write Data
2nd Byte Write Data
3rd Byte Write Data
D[7:0]
R5
G6
R4
G5
R3
R3
G4
R2
R2
G3
R1
R1
G2
R0
R0
G1
--
--
G0
--
--
--
--
R4
Data Read Sequence
for LC[7:6] = 0.
Data Read Sequence
D[7:0]
R2
GM1
1st Byte Read Data
2nd Byte Read Data
R1
B2
R0
B1
RM
B0
G2
0
G1
0
G0 GM2
0
0
R/G/B: the input Red/Green/Blue data.
R/GMN: the Red/Green bits mapped from RGB input data.
for LC[7:6] = 1, 2, 3.
Data Read Sequence
1st Byte Read Data
2nd Byte Read Data
D[7:0]
RT3 RT2 RT1 RT0 GT4 GT3 GT2 GT1
GT0 BT2 BT1 BT0
0
0
0
0
R/G/BTN : the N-th bit of after-truncated Red/Green/Blue input data
(23) SYSTEM RESET
Action
System Reset
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
1
0
0
0
1
0
This command will activate the system reset. Control register values will be reset to their default values.
Data stored in RAM will not be affected.
22
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
(24) NOP
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
No Operation
This command is used for “no operation”.
0
0
1
1
1
0
0
0
1
1
(25) SET TEST CONTROL
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set TT
(Double byte command)
0
0
0
0
1
1
1
0
0
1
TT
Testing parameter
This command is used for UltraChip production testing. Please do not use.
(26) SET LCD BIAS RATIO
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set Bias Ratio BR [1:0]
0
0
1
1
1
0
1
0
BR1 BR0
Bias ratio definition:
00b= 5
01b=7
10b=8
11b=9
(27) RESET CURSOR UPDATE MODE
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Reset Cursor Update Mode AC[3]=0
0
0
1
1
1
0
1
1
1
0
CA=CR
This command is used to reset cursor update mode function.
(28) SET CURSOR UPDATE MODE
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set AC[3]=1 CR=CA
0
0
1
1
1
0
1
1
1
1
This command is used for set cursor update mode function. When cursor update mode is set, UC1682 will
update register CR with the value of register CA. The column address CA will increment with write RAM data
operation but the address wraps around will be suspended no matter what WA setting is. However, the
column address will not increment in read RAM data operation.
The set cursor update mode can be used to implement “write after read RAM” function. The column address
(CA) will be restored to the value, which is before the set cursor update mode command, when resetting
cursor update mode.
The purpose of this pair of commands and their features is to support “write after read” function for cursor
implementation.
(29) SET COM END
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set CEN
(Double byte command)
0
0
0
0
1
1
1
1
0
0
0
1
CEN register parameter
This command programs the ending COM electrode. CEN defines the number of used COM electrodes, and
it should correspond to the number of pixel-rows in the LCD.
Revision 0.6
23
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
(30) SET PARTIAL DISPLAY START
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set DST
(Double byte command)
0
0
0
0
1
1
1
1
0
0
1
0
DST register parameter
This command programs the starting COM electrode, which has been assigned a full scanning period and
will output an active COM scanning pulse.
(31) SET PARTIAL DISPLAY END
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set DEN
(Double byte command)
0
0
1
1
1
1
0
0
1
1
DEN register parameter
This command programs the ending COM electrode, which has been assigned a full scanning period and
will output an active COM scanning pulse.
CEN, DST, and DEN are 0-based index of COM electrodes. They control only the COM electrode activity,
and do not affect the mapping of display RAM to each COM electrodes. The image displayed by each pixel
row is therefore not affected by the setting of these three registers.
When LC[9]=1, two partial display modes are possible with UC1682:
LC[8]=1: ON-OFF only, ultra-low-power mode (if Mux-Rate ꢁ 32, set BR=5).
LC[8]=0: Full gray shade low power mode (BR and PM stays the same)
When LC[9:8]=11b, the Mux-Rate is narrowed down to just the range between DST and DEN. When Mux-
Rate is under 32, set BR=5, PC[3:2]=01b, and adjust PM to reduce VLCD and achieve the lowest power
consumption. When LC[9:8]=10b, the Mux-Rate is still CEN+1. This is achieved by suppressing only the
scanning pulses, but not the scanning time slots, for COM electrodes that is outside of DST~DEN. Under
this mode, the gray-scale quality of the display is preserved, while the power can be reduced significantly. In
either case, DST/DEN defines a small subsection of the display which will remain active while shutting down
all the rest of the display to conserve energy.
0
DST
DEN
CEN
Pulse Disable:
Pulse Enable:
Not Scanned:
79
(32) SET WINDOW PROGRAM STARTING COLUMN ADDRESS
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
1
1
0
1
0
0
Set WPC0
(Double byte command)
WPC0[7:0] register parameter
This command is to program the starting column address of RAM program window.
24
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
(33) SET WINDOW PROGRAM STARTING ROW ADDRESS
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
1
1
0
1
0
1
Set WPP0
(Double byte command)
WPP0 register parameter
This command is to program the starting row address of RAM program window.
(34) SET WINDOW PROGRAM ENDING COLUMN ADDRESS
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
1
1
0
1
1
0
Set WPC1
(Double byte command)
WPC1[7:0] register parameter
This command is to program the ending column address of RAM program window.
(35) SET WINDOW PROGRAM ENDING ROW ADDRESS
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
1
1
0
1
1
1
Set WPP1
(Double byte command)
WPP1 register parameter
This command is to program the ending row address of RAM program window.
(36) SET WINDOW PROGRAM ENABLE
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
AC4
Set Window Program Enable AC[4]
0
0
1
1
1
1
1
0
0
This command is to enable the Window Program Function. Window Program Enable should always be reset
when changing the window program boundary and then set right before starting the new boundary program.
Window Program Function can be used to refresh the RAM data in a specified window of SRAM address.
When window programming is enabled, the CA and RA increment and wrap around will be automatically
adjusted, and therefore allow effective data update within the window.
The direction of Window Program will depend on the WA (AC[0]), RID (AC[2]), auto-increment order (AC[1])
and MX (LC[1]) register setting. WA decides whether the program RAM address advances to next
row/column after reaching the specified window column / row boundary. RID controls the RAM address
incrementing from WPP0 toward WPP1 (RID=0) or reverse the direction (RID=1). Auto-increment order
directs the RAM address increment vertically (AC[1]=1) or horizontally (AC[1]=0). MX results the RAM
column address incrementing from 103-WPC0 to 103-WPC1 (MX=1) or WPC0 to WPC1 (MX=0).
Revision 0.6
25
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
Auto-increment order = 0 MX=0 RID = 0
(WPP0,WPC0)
(WPP1,WPC1)
Auto-increment order = 1 MX=0 RID = 0
(WPP0,WPC0)
(WPP1,WPC1)
Auto-increment order = 0 MX=0 RID = 1
(WPP0,WPC0)
(WPP1,WPC1)
Auto-increment order = 0 MX=1 RID = 0
(WPP0,103-WPC0)
(WPP1,103-WPC1)
26
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
Auto-increment order = 1 MX=0 RID = 1
(WPP0,WPC0)
(WPP1,WPC1)
Auto-increment order = 1 MX=1 RID = 0
(WPP0,103-WPC0)
(WPP1,103-WPC1)
(WPP1,103-WPC1)
(WPP1,103-WPC1)
Auto-increment order = 0 MX=1 RID = 1
(WPP0,103-WPC0)
Auto-increment order = 1 MX=1 RID = 1
(WPP0,103-WPC0)
Revision 0.6
27
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
(37) SET OTP CONTROL
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
0
1
1
1
0
0
0
Set OTPC
(Double byte command)
OTP0 register parameter
This command is for OTP operation control:
OTPC[2:0] : OTP command
000 : Sleep
001 : OTP Read
010 : OTP Erase
011 : OTP Program
1XX : For UltraChip use only.
OTPC[3] : OTP Enable (automatically cleared each time after OTP command is done)
OTPC[4] : OTP value valid ( ignore OTP value when L )
OTPC[5] : OTP operation mode – Set [5] before OTP external V connection
(38) SET OTP WRITE MASK
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
0
1
1
1
0
0
1
Set OTPM
(Double byte command)
OTP1 register parameter
This command is enable write to each of the 8 individual OTP bits
(39) SET VOTP1 POTENTIOMETER
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
1
1
0
1
0
0
Set OTP2
(Double byte command)
OTP2 register parameter
This command is for fine tuning VOPT1 setting (use with BR=00)
(40) SET VOTP2 POTENTIOMETER
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
1
1
0
1
0
1
Set OTP3
(Double byte command)
OTP3 register parameter
This command is for fine tuning VOTP2 PM setting (use with BR=10)
(41) SET OTP WRITE TIMER
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
1
1
0
1
1
0
Set OTP4
(Double byte command)
OTP4 register parameter
(42) SET OTP READ TIMER
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
1
1
0
1
1
1
Set OTP5
(Double byte command)
OTP5 register parameter
28
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
LCD VOLTAGE SETTING
MULTIPLEX RATES
VLCD GENERATION
VLCD may be supplied either by internal charge
pump or by external power supply. The source of
VLCD is controlled by PC[3:2]. For good product
reliability, it is recommended to keep VLCD under
12V over the entire operating range.
Multiplex Rate is completely software
programmable in UC1682 via registers CEN,
DST, DEN, and partial display control LC[9:8].
Combined with low power partial display mode
and a low bias ratio of 5, UC1682 can support
wide variety of display control options. For
example, when a system goes into stand-by
mode, a large portion of LCD screen can be
turned off to conserve power.
When VLCD is generated internally, the voltage
level of VLCD is determined by three control
registers: BR (Bias Ratio), PM (Potentiometer),
and TC (Temperature Compensation), with the
following relationship:
BIAS RATIO SELECTION
VLCD = (CV 0 + CPM × PM ) × (1+ (T − 25) × CT %)
Bias Ratio (BR) is defined as the ratio between
VLCD and VBIAS, i.e.
where
BR = VLCD /VBIAS
where VBIAS = VB1+ – VB1– = VB0+ – VB0–
The theoretical optimum Bias Ratio can be
estimated by . BR of value 15~20%
lower/higher than the optimum value calculated
above will not cause significant visible change in
image quality.
,
CV0 and CPM are two constants, whose value
depends on the setting of BR register, as
illustrated in the table on the next page,
.
Mux +1
PM is the numerical value of PM register,
T is the ambient temperature in OC, and
CT is the temperature compensation
coefficient as selected by TC register.
Due to the nature of STN operation, an LCD
designed for good gray-shade performance at
high Mux Rate (e.g. MR=80), can generally
perform very well as a black and white display, at
lower Mux Rate. However, it is also true that such
technique generally can not maintain LCD’s
quality of gray shade performance, since the
contrast of the LCD will increase as Mux Rate
decreases, and the shades near the two ends of
the spectrum will start to lose visibility.
VLCD FINE TUNING
Gray shade and color STN LCD is sensitive to
even a 1% mismatch between IC driving voltage
and the VOP of LCD. However, it is difficult for
LCD makers to guarantee such high precision
matching of parts from different venders. It is
therefore necessary to adjust VLCD to match the
actual VOP of the LCD.
UC1682 supports four BR as listed below. BR
For the best results, software or OTP based VLCD
adjustment is the recommended method for VLCD
fine tuning.
can be selected by software program.
BR
Bias Ratio
0
5
1
7
2
8
3
9
For applications where mechanical manual fine
tuning of VLCD becomes necessary, then VBIAS pin
may be used with an external trim pot to fine tune
Table 1: Bias Ratios
the VLCD
.
TEMPERATURE COMPENSATION
Four (4) different temperature compensation
coefficients can be selected via software. The
four coefficients are given below:
LOAD DRIVING STRENGTH
The power supply circuit of UC1682 is designed
to handle LCD panels with load capacitance up to
~20nF when VDD2 = 2.5V. For larger LCD panels
use higher VDD and COF packaging.
TC
0
1
2
3
% per oC
-0.05 -0.10 -0.15 -0.20
20nF is also the recommended limit for LCD
panel size for COG applications.
Table 2: Temperature Compensation
Revision 0.6
29
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
VLCD QUICK REFERENCE
14
13
12
11
10
9
8
7
6
5
4
0
32
64
96
128
160
192
224
256
PM
VLCD-PM relationship for different BR setting at 25oC.
BR
CV0 (V)
CPM (mV)
PM
0
255
0
255
0
255
0
VLCD (V)
4.47
7.66
5
7
8
9
4.474
12.50
6.21
10.67
7.07
12.17
7.93
13.67
6.206
7.070
7.931
17.50
20.00
22.50
255
Note:
1. For good product reliability, keep VLCD under 10.3V at room temperature, and keep VLCD under
10.5V under all temperature and operating conditions.
2. The integer values of BR above are for reference only and probably have slight shift.
30
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
HI-V GENERATOR AND BIAS REFERENCE CIRCUIT
VDD
VDD
VDD2/VDD3
VB0+
SB0+
CB0
VB0-
SB0-
VDD2
VDD3
VB1+
SB1+
CB1+
CB1
(OPTIONAL)
30pf for
VB1-
SB1-
applications
with VLCD
over 11v
VLCDOUT
VLCDIN
VSS
VSS2
CL
RL
(OPTIONAL)
FIGURE 3: Reference circuit using internal Hi-V generator circuit
VDD
VB0+
SB0+
VDD
VDD2/VDD3
CB0
VB0-
SB0-
VDD2
VDD3
VB1+
SB1+
CB1+
(OPTIONAL)
10~30pf for
applications
with VLCD
R1
VR
CB1
VB1-
SB1-
over 11v
VBIAS
CBIAS
VLCDOUT
VLCDIN
VSS
VSS2
CL
RL
(OPTIONAL)
FIGURE 4: Reference circuit using external Bias source
Note
Sample component values: (The illustrated circuit and component values are for reference only. Please
optimize for specific requirements of each application.)
CB:
CL:
RL:
VR:
R1:
150 ~ 250x LCD load capacitance or 2.2µF (2V), whichever is higher.
5nF ~ 50nF (16V) is appropriate for most applications.
3 ~ 10M ꢀ, RC time constant of CL x RL should be roughly 0.2~1sec
1M ꢀ
330K ꢀ
CBIAS: 10nF ~ 0.1uF is the recommended default value (not required for OTP version).
Revision 0.6
31
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
LCD DISPLAY CONTROLS
CLOCK & TIMING GENERATOR
DRIVER ENABLE (DE)
UC1682 contains a built-in system clock. All
required components for the clock oscillator are
built-in. No external parts are required.
Driver Enable is controlled by the value of DC[2]
via Set Display Enable command. When DC[2] is
set to OFF (logic “0”), both COM and SEG drivers
will become idle and UC1682 will put itself into
Sleep mode to conserve power.
Four different line rates are provided for system
design flexibility. The line rate is controlled by
register LC[4:3]. When Mux-Rate is above 38,
frame rate is calculated as:
When DC[2] is set to ON, the DE flag will become
“1”, and UC1682 will first exit from Sleep mode,
restore the power (VLCD, VD etc.) and then turn on
COM and SEG drivers.
Frame Rate = Line-Rate / Mux-Rate.
When Mux-Rate is lowered to 38 (and 24), line
rate will be scaled down by 2 (and 3) times
automatically reduce power consumption.
ALL PIXELS ON (APO)
When set, this flag will force all SEG drivers to
output ON signals, disregarding the data stored
in the display buffer.
Flicker-free frame rate is dependent on LC
material and gray-shade modulation scheme.
Frame rate 175Hz is recommended for 32-shade
mode. Choose lower frame rate for lower power,
and choose higher frame rate to improve LCD
contrast and minimize flicker.
This flag has no effect when Display Enable is
OFF and it has no effect on data stored in RAM.
INVERSE (PXV)
When switching from 32-shade modulation to 8-
shade modulation, line rate will be scaled down
automatically by ~30%. Under most situations,
flicker behavior is similar between these two
different modulation schemes.
When this flag is set to ON, SEG drivers will
output the inverse of the value it received from
the display buffer RAM (bit-wise inversion). This
flag has no impact on data stored in RAM.
When switching from 32-shade modulation to 8-
shade modulation, line rate will be scaled down
automatically by ~35%. Under most situations,
flicker behavior is similar between these two
different modulation schemes. However, it is
always recommended to test each mode to make
sure flicker behavior is acceptable
PARTIAL SCROLL
Control register FL specifies a region of rows
which are not affected by the SL register. Since
SL register can be used to implement scroll
function. The FL register can be used to
implement fixed region when the other part of the
display is scrolled by SL.
DRIVER MODES
PARTIAL DISPLAY
COM and SEG drivers can be in either Idle mode
or Active mode, controlled by Display Enable flag
(DC[2]). When SEG drivers are in Idle mode, they
will be connected together to ensure zero DC
condition on the LCD.
UC1682 provides flexible control of Mux Rate
and active display area. Please refer to command
Set COM End, Set Partial Display Start, and Set
Partial Display End for more detail.
DRIVER ARRANGEMENTS
The naming conventions are: COM(x), where
x=1~80, refers to the COM driver for the x-th row
of pixels on the LCD panel.
GRAY-SHADE MODULATION MODE
UC1682 has two gray-shade modulation modes:
32-shade and 8-shade.
The 8-shade mode will consume ~30% less
power than the 32-shade mode, and can be used
for situations where power consumption is more
critical than color fidelity.
The mapping of COM(x) to LCD pixel rows is
fixed and it is not affected by SL, CST, CEN, DST,
DEN, MX or MY settings.
Changing gray-shade modulation mode does not
affect the content of SRAM display buffer, and
the image data will remain the same after
switching back and forth between 8-shade mode
and 32-shade mode.
DISPLAY CONTROLS
There are three groups of display control flags in
the control register DC: Driver Enable (DE), All-
Pixel-ON (APO) and Inverse (PXV). DE has the
overriding effect over PXV and APO.
32
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
In addition, please make sure
INPUT COLOR FORMATS
| RCMAX – RCMIN | < 0.3 x RCMAX
UC1682 supports the following four different input
color formats.
so that the COM distortions on the top of the
screen to the bottom of the screen are uniform.
256C (8-bit/RGB): This is the most compact
color mode, and is intended to minimize the bus
cycle required to refresh the display buffer. On-
chip extension circuit will automatically expand
the input RGB data into on-chip RAM buffer
format.
LAYOUT CONSIDERATIONS FOR SEG SIGNALS
Excessive SEG signal RC decay can cause
image dependent changes of medium gray
shades and sharply increase of SEG direction
crosstalk.
4KC (12-bit/RGB): In this color mode, G will be
extended while B will be dithered, and the input
data will be converted into 4R-5G-3B format
before they are stored to display RAM.
Please limit the worst case of SEG signal RC
delay as calculated below.
(RCOL /2.7 + RSEG) x CCOL < 0.5µS
where
56KC (16-bit/RGB): On-chip dither engine will
convert the input data into internal 12-bit-per-
RGB pixel format and store it to on-chip display
RAM. This is the default mode.
CCOL
:
LCD loading capacitance of one
pixel column. It can be calculated
by CLCD / #_of column, CLCD is the
LCD panel capacitance.
221KC (24-bit/RGB): On-chip dither engine will
convert input data into 4R-5G-3B format and
store it to on-chip display RAM. This mode
provides the smoothest shades and the most
vivid color in the LCD.
RCOL
RSEG
:
ITO resistance over one column of
pixels within the active area
:
SEG routing resistance from IC to
the active area + SEG driver
output impedance
Changing color mode does not affect the content
already stored in the display buffer RAM. Users
can use several color modes together in real time.
LAYOUT CONSIDERATIONS FOR SEG SIGNALS
For example, the menu portion can be painted in
256-color mode for fast update speed, and then
switch to 221K-color mode, together with window
programming option, and take advantage of built-
in dither engine to produce smooth graphics
images.
Excessive SEG signal RC decay can cause
image dependent changes of medium gray
shades and sharply increase of SEG direction
crosstalk.
For good image quality, please limit the worst
case of SEG signal RC delay as calculated below.
LAYOUT CONSIDERATIONS FOR COM SIGNALS
(RCOL /2.7 + RSEG) x CCOL < 0.4µS
where
Since the COM scanning pulse of UC1682 can
be as short as 30µS, it is critical to control the RC
delay of COM signal to minimize distortion of
COM scanning pulse.
CCOL
:
LCD loading capacitance of one
pixel column. It can be calculated
by CLCD / #_of column, CLCD is the
LCD panel capacitance.
For the best image quality, limit the worst case of
RC delay of COM signal as calculated below.
(RROW / 2.7+ RCOM + ROUT) x CROW < 2µS
where
RCOL
:
ITO resistance over one column of
pixels within the active area
RSEG
:
SEG routing resistance from IC to the
CROW
:
LCD loading capacitance of one
row of pixels. It can be calculated
by CLCD/Mux-Rate, where CLCD is
the LCD panel capacitance.
active area + SEG driver output impedance
RROW
RCOM
:
ITO resistance over one row of
pixels within the active area
:
COM routing resistance from IC to
the active area
ROUT
:
COM output impedance
Revision 0.6
33
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
RAM
W/R
POL
COM1
COM2
COM3
SEG1
SEG2
FIGURE 5: COM and SEG Driving Waveform
34
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
HOST INTERFACE
As summarized in the table below, UC1682
supports two parallel bus protocols, in either 8-bit
or 4-bit bus width, and three serial bus protocols.
Designers can either use parallel bus to achieve
high data transfer rate, or use serial bus to create
compact LCD modules.
Bus Type
Width
Access
BM[1:0]
D[7:6]
8080
6800
S8 (4wr)
S8uc (3wr)
Serial
S9 (3wr)
8-bit
4-bit
8-bit
4-bit
Read/Write
Write Only
00
10
Data
00
0X
11
Data
01
0X
00
10
01
1X
11
CS[1:0]
CD
Chip Select
Control/Data
–
___
__
_
_
WR0
–
–
WR
R/W
EN
___ __
WR1
RD
D[5:4]
D[3:0]
Data
Data
–
Data
Data
Data
–
Data
–
D0=SCK, D3=SDA
* Connect unused control pins and data bus pins to VDD or VSS
CS
CS
CD 1<=>0
Init bus
state
CD 1=>0
init color
mapping
RESET
Init bus
state
RESET
init color
mapping
Disable
Interface
Init bus
state
8-bit
4-bit
S8 or S9
S8uc
–
–
–
9
–
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
–
9
•
•
•
•
•
CS disable bus interface – CS can be used to disable Bus Interface Write / Read Access.
CD refers to CD transitions within valid CS window. CD = 0 means write command or read status.
CS / CD Sync / RESET can be used to initialize bus state machine (like 4 bits / S8 / S9).
RESET can be pin reset / soft reset / power on reset.
CD can be used to initialize the multi-byte input RGB format to/from on-chip SRAM mapping.
Table 3: Host interfaces Summary
There is no pipeline in write interface of Display
PARALLEL INTERFACE
The timing relationship between UC1682 internal
control signal RD, WR and their associated bus
actions are shown in the figure below.
RAM. Data is transferred directly from bus buffer
to internal RAM on the rising edges of write
pulses.
8-BIT & 4-BIT BUS OPERATION
The Display RAM read interface is implemented
as a two-stage pipe-line. This architecture
requires that, every time memory address is
modified, either in 8-bit mode or 4-bit mode, by
either Set CA, or Set RA command, a dummy
read cycle needs to be performed before the
actual data can propagate through the pipe-line
and be read from data port D[7:0].
UC1682 supports both 8-bit and 4-bit bus width.
The bus width is determined by pin BM[1].
4-bit bus operation exactly doubles the clock
cycles of 8-bit bus operation, MSB followed by
LSB, including the dummy read, which also
requires two clock cycles. The bus cycle of 4-bit
mode is reset each time CD pin changes state
(when CS is active).
Revision 0.6
35
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
External
CD
___
WR
__
RD
D[7:0]
LLSB
DL
DL+K
CMSB
CLSB
Dummy
DC
DC+1
MMSB
MLSB
Internal
Write
Read
Data
DL
L+K
DL+K
Dummy
DC
C+1
DC+1
C+2
DC+2
C+3
Latch
Column
L
L+K+1
C
M
Address
FIGURE 6: 8 bit Parallel Interface & Related Internal Signals
SERIAL INTERFACE
UC1682 supports three serial modes, one 4-wire
SPI mode (S8), one compact 3/4-wire mode (S8uc)
and one 3-wire SPI mode (S9). Bus interface mode
is determined by the wiring of the BM[1:0] and
D[7:6]. See table in last page for more detail.
content of the data been transferred. During each
write cycle, 8 bits of data, MSB first, are latched on
eight rising SCK edges into an 8-bit data holder.
If CD=0, the data byte will be decoded as
command. If CD=1, this 8-bit will be treated as data
and transferred to proper address in the Display
Data RAM on the rising edge of the last SCK pulse.
Pin CD is examined when SCK is pulled low for the
LSB (D0) of each token.
S8 (4-WIRE) INTERFACE
Only write operations are supported in 4-wire serial
mode. Pin CS[1:0] are used for chip select and bus
cycle reset. Pin CD is used to determine the
CS0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
SDA
SCK
CD
FIGURE 7.a: 4-wire Serial Interface (S8)
CS0
SDA
SCK
CD
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
FIGURE 7.b: 3/4-wire Serial Interface (S8uc)
36
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
bit is CD, which determines the content of the
following 8 bits of data, MSB first. These 8
command or data bits are latched on rising SCK
edges into an 8-bit data holder. If CD=0, the data
byte will be decoded as command. If CD=1, this 8-
bit will be treated as data and transferred to proper
address in the Display Data RAM at the rising edge
of the last SCK pulse.
S8UC (3/4-WIRE) INTERFACE
Only write operations are supported in this 3/4-wire
serial mode. The data format is identical to S8.
However, in addition to CS pins, CD pin transitions
will also reset the bus cycle in this mode. So, if CS
pins are hardwired to enable chip-select, the bus
can work properly with only three signal pins.
By sending CD information explicitly in the bit
stream, control pin CD is not used, and should be
connected to either VDD or VSS. The toggle of CS0
or CS1 for each byte of data/command is
recommended but optional.
S9 (3-WIRE) INTERFACE
Only write operations are supported in this 3-wire
serial mode. Pin CS[1-0] are used for chip select
and bus cycle reset. On each write cycle, the first
CS0
CD D7
D6
D5
D4
D3
D2
D1
D0
CD D7
D6
SDA
SCK
FIGURE 7.c: 3-wire Serial Interface (S9)
Revision 0.6
37
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
HOST INTERFACE REFERENCE CIRCUIT
VDD
VCC
VDD
D7-D0
D7-D0
CD
WR
RD
CD
WR0(WR)
WR1(RD)
ADDRESS
IORQ
CS0
CS1
MPU
UC1682
DECODER
VDD
RST
ID
VDD
BM1
BM0
GND
VSS
FIGURE 8: 8080/8bit parallel mode reference circuit
VDD
VCC
VDD
D7
D3-D0
D3-D0
CD
WR
RD
CD
WR0(WR)
WR1(RD)
ADDRESS
IORQ
CS0
CS1
MPU
UC1682
DECODER
VDD
RST
ID
BM1
BM0
GND
VSS
FIGURE 9: 8080/4bit parallel mode reference circuit
38
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
VDD
VCC
VDD
D7-D0
D7-D0
CD
R/W
E
CD
WR0(R/W)
WR1(E)
ADDRESS
IORQ
CS0
CS1
MPU
UC1682
DECODER
VDD
RST
ID
VDD
BM1
BM0
GND
VSS
FIGURE 10: 6800/8bit parallel mode reference circuit
VDD
VCC
VDD
D7
D3-D0
D3-D0
CD
R/W
E
CD
WR0(R/W)
WR1(E)
ADDRESS
IORQ
CS0
CS1
MPU
UC1682
DECODER
VDD
RST
ID
VDD
BM1
BM0
GND
VSS
FIGURE 11: 6800/4bit parallel mode reference circuit
Revision 0.6
39
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
VDD
D7
D6
VCC
VDD
SCK
SDA
CD
SCK(D0)
SDA(D3)
CD
WR0
WR1
ADDRESS
IORQ
CS0
CS1
MPU
UC1682
DECODER
VDD
RST
ID
BM1
BM0
GND
VSS
FIGURE 12: 4-Wires SPI (S8) serial mode reference circuit
VDD
VDD
D7
VCC
VDD
D6
SCK
SDA
CD
SCK(D0)
SDA(D3)
CD
WR0
WR1
CS0
MPU
UC1682
VDD
RST
ID
CS1
BM1
BM0
GND
VSS
FIGURE 13: 3/4-Wires SPI (S8uc) serial mode reference circuit
40
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
VDD
VDD
VCC
VDD
D7
SCK
SDA
SCK(D0)
SDA(D3)
WR0
WR1
ADDRESS
IORQ
CS0
CS1
MPU
UC1682
DECODER
VDD
RST
ID
VDD
BM1
BM0
GND
VSS
FIGURE 14: 3-Wires SPI (S9) serial mode reference circuit
Note
•
ID pin is for production control. The connection will affect the content of D[7] when using Get Status
command. Connect to VDD for “H” or VSS for “L”.
•
RST pin is optional. When RST pin is not used, connect the pin to VDD
.
Revision 0.6
41
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
DISPLAY DATA RAM
zero value is equivalent to scrolling the LCD
DATA ORGANIZATION
The input display data (depend on color mode)
are stored to a dual port static RAM (RAM, for
Display Data RAM) organized as 80x104X12.
display up or down (depends on MY) by SL rows.
RAM ADDRESS GENERATION
The mapping of the data stored in the display
SRAM and the scanning COM electrodes can be
obtained by combining the fixed COM scanning
sequence and the following RAM address
generation formula.
After setting CA and RA, the subsequent data
write cycles will store the data for the specified
pixel to the proper memory location.
Please refer to the map in the following page
between the relation of COM, SEG, SRAM, and
various memory control registers.
When FL=0, during the display operation, the
RAM line address generation can be
mathematically represented as following:
For the 1st line period of each field
DISPLAY DATA RAM ACCESS
The Display RAM is a special purpose dual port
RAM which allows asynchronous access to both
its column and row data. Thus, RAM can be
independently accessed both for Host Interface
and for display operations.
Line = SL
Otherwise
Line = Mod(Line+1, 80)
Where Mod is the modular operator, and Line is
the bit slice line address of RAM to be outputted
to SEG drivers. Line 0 corresponds to the first bit-
slice of data in RAM.
DISPLAY DATA RAM ADDRESSING
A Host Interface (HI) memory access operation
starts with specifying Row Address (RA) and
Column Address (CA) by issuing Set Row
Address and Set Column Address commands.
The above Line generation formula produces the
“loop around” effect as it effectively resets Line to
0 when Line+1 reaches 80. Effects such as
scrolling can be emulated by changing SL
dynamically.
If wrap-around (WA, AC[0]) is OFF (0), CA will
stop incrementing after reaching the end of row
(103), and system programmers need to set the
values of RA and CA explicitly.
MY IMPLEMENTATION
If WA is ON (1), when CA reaches the end of a
row, CA will be reset to 0 and RA will increment
or decrement, depending on the setting of row
Increment Direction (RID, AC[2]). When RA
reaches the boundary of RAM (i.e. RA = 0 or 79),
RA will be wrapped around to the other end of
RAM and continue.
Row Mirroring (MY) is implemented by reversing
the mapping order between COM electrodes and
RAM, i.e. the mathematical address generation
formula becomes:
For the 1st line period of each field
Line = Mod(SL + MUX-1, 80)
where MUX = CEN + 1
MX IMPLEMENTATION
Otherwise
Column Mirroring (MX) is implemented by
selecting either (CA) or (103–CA) as the RAM
column address. Changing MX affects the data
written to the RAM.
Line = Mod(Line-1 , 80)
Visually, the effect of MY is equivalent to flipping
the display upside down. The data stored in
display RAM are not affected by MY.
Since MX has no effect on the data already
stored in RAM, changing MX does not have
immediate effect on the displayed pattern. To
refresh the display, refresh the data stored in
RAM after setting MX.
ROW MAPPING
COM electrode scanning orders are not affected
by Start Line (SL), Fixed Line (FL) or Mirror Y
(MY, LC[3]). Visually, register SL having a non-
42
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
and then set again in order to initialize another
window program.
WINDOW PROGRAM
Window program is designed for data write in a
specified window range of SRAM address. The
procedure should start with window boundary
registers setting (WPP0, WPP1, WPC0 and WPC1)
and then enable AC[4]. After AC[4] sets, data
can be written to SRAM within the window
The data write direction will be determined by
AC[2:0] and MX settings. When AC[0]=1, the
data write can be consecutive within the range of
the specified window. AC[1] will control the data
write in either column or row direction. AC[2] will
result the data write starting either from row
WPP0 or WPP1. MX is for the initial column
address either from WPC0 to WPC1 or from (MC-
WPC0 to MC-WPC1).
address range which is specified by (WPP0, WPC0)
and (WPP1, WPC1). AC[4] should be cleared after
any modification of window boundary registers
Example1:
Example 2:
AC[2:0] = 001 MX=0
column
AC[2:0] = 111 MX = 0
0
103
(WPP0, WPC0)
(WPP0, WPC0)
row
(WPP1,WPC1)
(WPP1,WPC1)
79
Revision 0.6
43
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
Row
Adderss
MY=0
SL=0 SL=16
MY=1
RAM
SL=0
SL=16
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10 COM74
COM11 COM75
COM12 COM76
COM13 COM77
COM14 COM78
COM15 COM79
COM16 COM80
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26 COM10
COM27 COM11
COM28 COM12
COM29 COM13
COM65 COM80 COM16
COM66 COM79 COM15
COM67 COM78 COM14
COM68 COM77 COM13
COM69 COM76 COM12
COM70 COM75 COM11
COM71 COM74 COM10
COM72 COM73
COM73 COM72
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM80
COM79
COM78
COM77
COM76
COM75
COM74
COM73
COM72
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM76 COM60
COM77 COM61
COM78 COM62
COM79 COM63
COM80 COM64
COM5
COM4
COM3
COM2
COM1
Example for memory mapping: let MX = 0, MY = 0, SL = 0, LC[7:6] = 10b ( RRRRR-GGGGGG-BBBBB, 56K
color ), according to the data shown in the above table (R: 11111b, G: 111111b, B: 11111b):
⇒
⇒
1st Byte write data: 11111111b
2nd Byte write data: 11111111b
44
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
RESET & POWER MANAGEMENT
TYPES OF RESET
CHANGING OPERATION MODE
UC1682 has two different types of Reset:
In addition to Power-ON-Reset, two commands will
initiate OM transitions:
Power-ON-Reset and System-Reset.
Power-ON-Reset is performed right after VDD is
connected to power. Power-On-Reset will first wait
for about 5~10mS, depending on the time required
for VDD to stabilize, and then trigger the System
Reset.
Set Display Enable, and System Reset.
When DC[2] is modified by Set Display Enable, OM
will be updated automatically. There is no other
action required to enter Sleep mode.
For maximum energy utilization, Sleep mode is
designed to retain charges stored in external
capacitors CB0, CB1, and CL. To drain these
capacitors, use Reset command to activate the on-
chip draining circuit.
System Reset can also be activated by software
command or by connecting RST pin to ground.
In the following discussions, Reset means System
Reset.
Action
Set Driver Enable to “0”
Set Driver Enable to “1”
Reset command or
RST_ pin pulled “L”
Power ON Reset
Mode
Sleep
Normal
OM
10
11
RESET STATUS
When UC1682 enters RESET sequence:
•
•
Operation mode will be “Reset”
System Status bits RS and BZ will stay as “1”
until the Reset process is completed. When
RS=1, the IC will only respond to Read Status
command. All other commands are ignored.
Reset
00
Table 5: OM changes
Even though UC1682 consumes very little energy
in Sleep mode (typically 5uA or less); however,
since all capacitors are still charged, the leakage
through COM drivers may damage the LCD over
the long term. It is therefore recommended to use
Sleep mode only for brief Display OFF operations,
such as full-frame screen updates, and to use
RESET for extended screen OFF operations.
•
All control registers are reset to default values.
Refer to Control Registers for details of their
default values.
OPERATION MODES
UC1682 has three operating modes (OM):
Reset, Normal, Sleep.
Mode
OM
Host Interface
Reset
00
Active
OFF
OFF
OFF
ON
Sleep Normal
10 11
Active Active
EXITING SLEEP MODE
UC1682 contains internal logic to check whether
V
LCD and VBIAS are ready before releasing COM
and SEG drivers from their idle states. When
exiting Sleep or Reset mode, COM and SEG
drivers will not be activated until UC1682 internal
voltage sources are restored to their proper values.
Clock
OFF
OFF
OFF
OFF
ON
ON
ON
LCD Drivers
Charge Pump
Draining Circuit
OFF
Table 4: Operating Modes
Revision 0.6
45
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
POWER-DOWN SEQUENCE
POWER-UP SEQUENCE
UC1682 power-up sequence is simplified by built-in
“Power Ready” flags and the automatic invocation
of System-Reset command after Power-ON-Reset.
To prevent the charge stored in capacitors CBX+
,
CBX–, and CL from damaging the LCD, when VDD is
switched off, use Reset mode to enable the built-in
draining circuit and discharge these capacitors.
The draining resistor is 1K ꢀ for both VLCD and VB+.
It is recommended to wait 3 x RC for VLCD and 1.5
x RC for VB+. For example, if CL is 15nF, then the
draining time required for VLCD is 0.5~1mS.
System programmers are only required to wait 5~
10 ms before the CPU starting to issue commands
to UC1682. No additional time sequences are
required between enabling the charge pump,
turning on the display drivers, writing to RAM or
any other commands. However, while turning on
When internal VLCD is not used, UC1682 will NOT
drain VLCD during RESET. System designers need
to make sure external VLCD source is properly
VDD, VDD2/3 should be started not later than VDD
.
drained off before turning off VDD
.
Delay allowance between VDD and VDD2/3 is
illustrated as Figure 15-1.
Turn on VDD
Wait 5~10 mS
Reset command
Wait ~1 mS
Set OTPC[4]
( Ignore OTP value when “L” )
Set LCD Bias Ratio (BR)
Set Potential Meter (PM)
Turn off VDD
Figure 16: Reference Power-Down Sequence
Set Display Enable
Figure 15: Reference Power-Up Sequence
T
Delay > 0 s
V
DD2/3 > 2.4V
VDD > 1.8V
DD2/3 > VDD
V
TWait > 50 mS
10μS < T1, T2 < 10 mS
Tf < 10 mS
T
T
Figure 15-1: Delay allowance and Power Off-On Sequence
46
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
SAMPLE POWER MANAGEMENT COMMAND SEQUENCES
The following tables are examples of command sequence for power-up, power-down and display ON/OFF
operations. These are only to demonstrate some “typical, generic” scenarios. Designers are encouraged to
study related sections of the datasheet and find out what the best parameters and control sequences are for
their specific design needs.
C/D
The type of the interface cycle. It can be either Command (0) or Data (1)
The direction of dataflow of the cycle. It can be either Write (0) or Read (1).
W/R
Type
Required: These items are required
Customer: These items are not necessary if customer parameters are the same as default
Advanced: We recommend new users to skip these commands and use default values.
Optional: These commands depend on what users want to do.
POWER-UP
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Chip action
Comments
R
R
–
0
0
–
0
0
–
1
0
–
0
0
–
1
0
–
1
0
–
1
0
–
0
0
–
0
0
–
0
0
Automatic Power-ON Reset. Wait 5~10ms after VDD is ON
(37) Set OTP operation
Control.
Ignore OTP value
(Double-type Command)
C
C
A
C
C
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
1
1
0
1
0
1
0
0
0
1
0
0
0
0
0
1
1
#
0
1
0
#
#
#
#
#
#
#
#
#
#
(5) Set Temp. Compensation
(20) Set LCD Mapping
(15) Set Line Rate
(22) Set Color Mode
(26) Set LCD Bias Ratio
Set up LCD format specific
parameters, MX, MY, etc.
Fine tune for power, flicker,
contrast, and shading.
LCD specific operating
voltage setting
0
0
1
0
0
0
0
0
0
1
R
(11) Set VBIAS Potentiometer
0
0
#
#
#
#
#
#
#
#
1
.
0
.
#
.
#
.
#
.
#
.
#
.
#
.
#
.
#
.
O
R
Write display RAM
Set up display image
.
.
.
.
.
.
.
.
.
.
1
0
0
0
#
1
#
0
#
1
#
0
#
1
#
1
#
1
#
1
(18) Set Display Enable
POWER-DOWN
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Chip action
(23) System Reset
Draining capacitor
Comments
R
R
0
–
0
–
1
–
1
–
1
–
0
–
0
–
0
–
1
–
0
–
Wait ~1ms before VDD OFF
BRIEF DISPLAY-OFF
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Chip action
(18) Set Display Disable
Write display RAM
Comments
R
C
0
1
.
0
0
.
1
#
.
0
#
.
1
#
.
0
#
.
1
#
.
1
#
.
1
#
.
0
#
.
Set up display image (Image
update is optional. Data in
the RAM is retained through
the SLEEP state.)
.
.
.
.
.
.
.
.
.
.
1
0
0
0
#
1
#
0
#
1
#
0
#
1
#
1
#
1
#
1
R
(18) Set Display Enable
* This is only recommended for very brief display OFF (under 10mS).
If image becomes unstable use the Extended Display OFF approach shown below.
Revision 0.6
47
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
EXTENDED DISPLAY-OFF
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Chip action
Comments
R
0
–
–
0
–
–
1
–
–
1
–
–
1
–
–
0
–
–
0
–
–
0
–
–
1
–
–
0
–
–
(23) System Reset.
CB1, CB1, CLCD discharged.
Extended display OFF
–
Z z z z . . .
–
System waking up
Repeat power up register
R
C
Repeat power-up sequence
setting sequence
1
.
0
.
#
.
#
.
#
.
#
.
#
.
#
.
#
.
#
.
Set up display image (Image
update is optional. Data in
the RAM is retained through
the RESET state.)
Write display RAM
.
.
.
.
.
.
.
.
.
.
1
0
0
0
#
1
#
0
#
1
#
0
#
1
#
1
#
1
#
1
R
(18) Set Display Enable
* The sequence is basically the same as the power up sequence, except Power-ON Reset is replaced by
System Reset command, and an extended idle time in between.
48
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
ABSOLUTE MAXIMUM RATINGS
In accordance with IEC134, note 1, 2 and 3.
Symbol
VDD
VDD2
VDD3
VLCD
VIN
Parameter
Min.
-0.3
-0.3
-0.3
-0.3
-0.4
-30
Max.
+4.0
+4.0
Unit
V
V
V
V
Logic Supply voltage
LCD Generator Supply voltage
Analog Circuit Supply voltage
LCD Driving voltage (-25OC ~ +75OC)
Digital input signal
Operating temperature range
Storage temperature
+4.0
+12.0
VDD + 0.5
+85
V
TOPR
TSTR
oC
oC
-55
+125
Notes
1. VDD based on VSS = 0V
2. Stress beyond ranges listed above may cause permanent damages to the device.
Revision 0.6
49
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
SPECIFICATIONS
DC CHARACTERISTICS
Symbol
VDD
VDD2/3
VLCD
VD
Parameter
Conditions
Min.
1.8
2.4
Typ.
Max. Unit
Supply for digital circuit
Supply for bias & pump
Charge pump output
LCD data voltage
3.3
3.3
V
V
VDD2/3 ꢀ 2.4V, 25OC
VDD2/3 ꢀ 2.4V, 25OC
9.9
10.5
1.5
V
0.9
V
VIL
Input logic LOW
0.2VDD
V
VIH
VOL
VOH
IIL
Input logic HIGH
0.8VDD
0.8VDD
V
V
V
Output logic LOW
Output logic HIGH
Input leakage current
Input capacitance
Output capacitance
0.2VDD
1.5
10
10
3.0
4.0
22.4
µA
pF
pF
kΩ
KΩ
Klps
CIN
COUT
5
5
1.5
2.0
20
R0(SEG) SEG output impedance
R0(COM) COM output impedance
VLCD = 9.9V
VLCD = 9.9V
LC[4:3] = 11b
fLINE
Average Line rate
18.4
Note: When VDD < 2.0, letting VIL = 0 and VIH = VDD is recommended.
POWER CONSUMPTION
VDD = 2.8V, Bias Ratio = 8, PM = 142, VLCD = 9.9V, Line Rate =10b, PL = 11b, MR =80, Bus mode =6800,
CL = 5nF~50nF, CB = 2µF. All SEG/COM outputs are open-circuit.
Display Pattern
All-OFF
2-pixel checker
VLCD
Conditions
Bus = idle
Bus = idle
Typ. (µA)
Max. (µA)
2000
2000
5
665
860
-
Bus = idle (standby current)
50
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
AC CHARACTERISTICS
CD
tAS80
tAH80
CS0
CS1
tCSSA80
tCY80
tCSH80
tCSSD80
tPWR80, tPWW80
tHPW80
WR0
WR1
tDS80
tDH80
Write
D[7:0]
tACC80
tOD80
Read
D[7:0]
FIGURE 17: Parallel Bus Timing Characteristics (for 8080 MCU)
(2.5V ꢁ VDD< 3.3V, Ta= –30 to +85oC)
Symbol
Signal
Description
Condition
Min.
Max.
Units
tAS80
CD
Address setup time
0
–
ns
tAH80
Address hold time
15
tCY80
System cycle time
–
ns
8 bits bus
(read)
140
80
140
80
(write)
(read)
(write)
4 bits bus
tPWR80
tPWW80
tHPW80
WR1
WR0
Pulse width 8 bits (read)
70
70
40
40
–
–
–
ns
ns
ns
4 bits
Pulse width 8 bits (write)
4 bits
WR0, WR1
High pulse width
8 bits bus
(read)
(write)
(read)
(write)
70
40
70
40
4 bits bus
tDS80
tDH80
tACC80
tOD80
tCSSA80
tCSSD80
tCSH80
D0~D7
Data setup time
Data hold time
30
–
ns
ns
ns
15
Read access time
CL = 100pF
–
80
40
Output disable time
25
10
10
20
CS1/CS0
Chip select setup time
Revision 0.6
51
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
(1.8V ꢁ VDD< 2.5V, Ta= –30 to +85oC)
Symbol
Signal
Description
Condition
Min.
Max.
Units
tAS80
Address setup time
0
30
–
ns
CD
tAH80
Address hold time
tCY80
System cycle time
–
ns
8 bits bus (read)
280
160
280
160
140
140
80
(write)
4 bits bus (read)
(write)
tPWR80
tPWW80
tHPW80
Pulse width 8 bits (read)
–
–
–
ns
ns
ns
WR1
WR0
4 bits (read)
Pulse width 8 bits (write)
4 bits (write)
High pulse width
8 bits bus (read)
(write)
80
140
80
140
80
60
30
-
50
20
20
40
WR0, WR1
D0~D7
4 bits bus (read)
(write)
tDS80
tDH80
tACC80
tOD80
tCSSA80
tCSSD80
tCSH80
Data setup time
–
ns
ns
ns
Data hold time
Read access time
Output disable time
CL = 100pF
160
80
CS1/CS0
Chip select setup time
52
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
CD
tAS68
tAH68
CS0
CS1
tCSSA68
tCY68
tCSH68
tCSSD68
tPWR68, tPWW68
tLPW68
WR1
tDS68
tDH68
Write
D[7:0]
tACC68
tOD68
Read
D[7:0]
FIGURE 18: Parallel Bus Timing Characteristics (for 6800 MCU)
(2.5V ꢁ VDD< 3.3V, Ta= –30 to +85oC)
Symbol
Signal
Description
Condition
Min.
Max.
Units
tAS68
CD
Address setup time
0
–
ns
tAH68
Address hold time
20
TCY68
System cycle time
8 bits bus
–
ns
(read)
140
80
140
80
(write)
(read)
(write)
4 bits bus
tPWR68
tPWW68
tLPW68
WR1
Pulse width 8 bits (read)
70
70
40
40
–
–
–
ns
ns
ns
4 bits
Pulse width 8 bits (write)
4 bits
Low pulse width
8 bits bus (read)
(write)
70
40
70
40
4 bits bus (read)
(write)
tDS68
tDH68
tACC68
tOD68
tCSSA68
tCSSD68
tCSH68
D0~D7
Data setup time
30
–
ns
ns
ns
Data hold time
15
Read access time
Output disable time
CL = 100pF
–
80
40
25
10
10
20
CS1/CS0
Chip select setup time
Revision 0.6
53
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
(1.8V ꢁ VDD< 2.5V, Ta= –30 to +85oC)
Symbol
Signal
Description
Condition
Min.
Max.
Units
tAS68
CD
Address setup time
0
40
–
ns
tAH68
Address hold time
TCY68
System cycle time
8 bits bus
–
ns
(read)
280
160
280
160
140
140
80
(write)
4 bits bus (read)
(write)
tPWR68
tPWW68
tLPW68
WR1
Pulse width 8 bits (read)
–
–
–
ns
ns
ns
4 bits
Pulse width 8 bits (write)
4 bits
Low pulse width
8 bits bus (read)
(write)
80
140
80
140
80
60
30
-
4 bits bus (read)
(write)
tDS68
tDH68
tACC68
tOD68
TCSSA68
TCSSD68
TCSH68
D0~D7
Data setup time
–
ns
ns
ns
Data hold time
Read access time
Output disable time
CL = 100pF
160
80
50
20
20
40
CS1/CS0
Chip select setup time
54
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
CD
tASS8
tAHS8
CS0
CS1
tCSSAS8
tCYS8
tLPWS8
tCSHS8
tCSSDS8
tHPWS8
SCK
SDA
tDSS8
tDHS8
FIGURE 19: Serial Bus Timing Characteristics (for S8)
(2.5V ꢁ VDD< 3.3V, Ta= –30 to +85oC)
Symbol
tASS8
tAHS8
Signal
Description
Address setup time
Address hold time
System cycle time
Low pulse width
Condition
Min.
0
15
80
35
35
Max.
Units
ns
ns
ns
ns
–
–
–
–
–
–
CD
tCYS8
SCK
tLPWS8
tHPWS8
tDSS8
tDHS8
High pulse width
ns
ns
Data setup time
30
SDA
Data hold time
20
tCSSAS8
tCSSDS8
tCSHS8
10
10
20
ns
CS1/CS0
Chip select setup time
(1.8V ꢁ VDD< 2.5V, Ta= –30 to +85oC)
Symbol
tASS8
tAHS8
Signal
Description
Address setup time
Address hold time
System cycle time
Low pulse width
Condition
Min.
0
30
160
70
70
Max.
Units
ns
ns
ns
ns
–
–
–
–
–
–
CD
tCYS8
SCK
SDA
tLPWS8
tHPWS8
tDSS8
tDHS8
High pulse width
ns
ns
Data setup time
60
Data hold time
40
tCSSAS8
tCSSDS8
tCSHS8
20
20
40
ns
CS1/CS0
Chip select setup time
Revision 0.6
55
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
CS0
CS1
tCSS9
tCYS9
tWLS9
tCSHS9
tCSSDS9
tWHS9
SCK
SDA
tDSS9
tDHS9
FIGURE 20: Serial Bus Timing Characteristics (for S9)
(2.5V ꢁ VDD< 3.3V, Ta= –30 to +85oC)
Symbol
tCYS9
tLPWS9
tHPWS9
tDSS9
tDHS9
tCSSAS9
tCSSDS9
tCSHS9
Signal
Description
System cycle time
Low pulse width
High pulse width
Condition
Min.
Max.
Units
ns
ns
ns
ns
80
35
35
30
20
10
10
20
–
–
–
–
SCK
Data setup time
SDA
Data hold time
ns
CS1/CS0
Chip select setup time
(1.8V ꢁ VDD< 2.5V, Ta= –30 to +85oC)
Symbol
tCYS9
tLPWS9
tHPWS9
tDSS9
tDHS9
tCSSAS9
tCSSDS9
tCSHS9
Signal
Description
System cycle time
Low pulse width
High pulse width
Condition
Min.
Max.
Units
ns
ns
ns
ns
160
70
70
60
40
20
20
40
–
–
–
–
SCK
Data setup time
SDA
Data hold time
ns
CS1/CS0
Chip select setup time
56
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
tRW
RST
FIGURE 21: Reset Characteristics
(1.8V ꢁ VDD< 3.3V, Ta= –30 to +85oC)
Symbol
Signal
Description
Condition
Min.
Max.
Units
tRW
RST
Reset low pulse width
500
–
S
µ
Revision 0.6
57
ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
PHYSICAL DIMENSIONS
PAD COORDINATES
DIE SIZE:
13.944mm x 1.494mm
DIE THICKNESS:
0.5mm
BUMP HEIGHT:
17µm ±1µm (within die)
MINIMUM BUMP PITCH:
SEG: 41.5µm (Typ.)
COM: 50.0µm (Typ.)
MINIMUM BUMP GAP:
17µm (Typ.)
COORDINATE ORIGIN:
Chip center
PAD REFERENCE:
Pad center
(Drawing and coordinates are
for the Circuit/Bump view.)
58
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
ALIGNMENT MARK INFORMATION
U-Left
Mark
U-Right
Mark
(0,0)
D-Left
Mark
D-Right
Mark
SHAPE OF THE ALIGNMENT MARK:
3
1
1
NOTE:
1
3
C
Alignment mark is on Metal3
under Passivation.
2
4
3
2
2
COORDINATES:
U-Left Mark
U-Right Mark
X Y
X
Y
1
2
3
-6887.1
-6879.1
-6846.2
615.7
606.5
598.5
6853.2
6882.4
6858.1
608.5
589.2
613.4
D-Left Mark
D-Right Mark
X
Y
X
Y
1
2
3
4
C
-5690.3
-5678.3
-5701.8
-5666.8
-5684.3
-612.1
-667.2
-633.7
-645.7
-639.7
5535.4
5547.4
5523.9
5558.9
5541.4
-612.1
-667.2
-633.7
-645.7
-639.7
TOP METAL AND PASSIVATION:
Å
Å
Å
Metal3 / 9KÅ
Metal3 / 9KÅ
FOR NON-OTP PROCESS CROSS-SECTION
FOR OTP PROCESS CROSS-SECTION
Revision 0.6
59
ULTRACHIP
High-Voltage Mixed-Signal IC
©1999~2003
PI INFORMATION
PI THICKNESS:
3.6 ± 0.4 µm
MINIMUM SEPARATION OF
BUMP TO EDGE OF POLYIMIDE
LAYER:
20 µm
60
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
PAD COORDINATES
#
Pad Name
DUMMY
COM2
COM4
COM6
COM8
COM10
COM12
COM14
COM16
COM18
COM20
COM22
COM24
COM26
COM28
COM30
COM32
COM34
COM36
COM38
COM40
COM42
COM44
COM46
COM48
DUMMY
COM50
COM52
COM54
COM56
COM58
COM60
COM62
COM64
COM66
COM68
COM70
COM72
COM74
COM76
COM78
COM80
D7
X
Y
W
H
#
Pad Name
BM0
X
Y
W
H
1
-6867.9
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.4
-6867.9
-6479.6
-6429.6
-6379.6
-6329.6
-6279.6
-6229.6
-6179.6
-6129.6
-6079.6
-6029.6
-5979.6
-5929.6
-5879.6
-5829.6
-5779.6
-5729.6
-5481.6
-5402.3
-5323.8
-5093.8
-4863.8
-4633.8
-4403.8
-4173.8
-3943.8
-3706.0
-3501.3
-3407.5
-3333.2
-3256.9
-3173.6
-3086.1
-3009.0
-2930.4
649.7
570.3
520.3
470.3
420.3
370.3
320.3
270.3
220.3
170.3
120.3
70.3
85
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
85
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
50
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
61
-2840.0
-2760.8
-2681.9
-2593.9
-2523.9
-2195.0
-2124.8
-1800.8
-1727.1
-1657.1
-1587.1
-1480.7
-1391.6
-1311.6
-1231.6
-1151.6
-1071.6
-991.5
-911.5
-831.5
-751.5
-671.5
-591.5
-511.5
-431.5
-351.5
-275.1
-97.5
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
2
62
VDDX
BM1
3
63
64
TST4
TST4
TP5
4
65
5
66
6
67
TST2
TP4
7
68
8
69
TP3
9
70
TP2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
71
TP1
72
ID
73
VSS
20.3
74
VSS
-29.8
75
VSS
-79.8
76
VSS
-129.8
-179.8
-229.8
-279.8
-329.8
-379.8
-429.8
-479.8
-529.8
-579.8
-654.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
77
VSS
78
VSS
79
VSS2
VSS2
VSS2
VSS2
VSS2
VDD3
VDD3
VDD3
VDD3
VDD2
VDD2
VDD2
VDD2
VDD2
VDD
80
81
82
83
84
85
86
87
88
89
-17.5
90
62.5
91
141.1
92
219.5
93
493.0
94
VDD
573.0
95
VDD
653.0
96
VDD
733.0
97
VDD
813.0
98
VDD
893.0
972.9
99
VB0+
VB0+
VB0+
VB0+
VB0+
VB0+
VB0+
VB0+
VB0+
SB0+
VB1+
VB1+
VB1+
VB1+
VB1+
VB1+
VB1+
VB1+
VB1+
SB1+
VB1-
VB1-
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
1042.9
1112.9
1182.9
1252.9
1475.7
1546.0
1616.0
1686.0
1756.0
1974.9
2044.9
2114.9
2184.9
2254.9
2477.7
2548.0
2618.0
2688.0
2758.0
2976.9
3046.9
VDDX
D6
D5
D4
D3
D2
D1
D0
VBIAS
RST_
CS1
VDDX
CS0
CD
WR0
VDDX
WR1
Revision 0.6
61
ULTRACHIP
High-Voltage Mixed-Signal IC
©1999~2003
#
Pad Name
VB1-
VB1-
VB1-
VB1-
VB1-
VB1-
VB1-
SB1-
VB0-
VB0-
VB0-
VB0-
VB0-
VB0-
VB0-
VB0-
VB0-
SB0-
X
Y
W
H
#
Pad Name
X
Y
W
H
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
3116.9
3186.9
3256.9
3479.7
3550.0
3620.0
3690.0
3760.0
3978.9
4048.9
4118.9
4188.9
4258.9
4481.7
4552.0
4622.0
4692.0
4762.0
5118.4
5188.7
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-645.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-642.4
-658.7
-594.9
-544.9
-494.9
-444.9
-394.9
-344.9
-294.9
-244.9
-194.9
-144.9
-94.9
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
85
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
50
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
184 DUMMY
6868.1
6538.0
6496.5
6455.0
6413.5
6372.0
6330.5
6289.0
6247.5
6206.0
6164.5
6123.0
6081.5
6040.0
5998.5
5957.0
5915.5
5874.0
5832.5
5791.0
5749.5
5708.0
5666.5
5625.0
5583.5
5542.0
5500.5
5459.0
5417.5
5376.0
5334.5
5293.0
5251.5
5210.0
5168.5
5127.0
5085.5
5044.0
5002.5
4961.0
4919.5
4878.0
4836.5
4795.0
4753.5
4712.0
4670.5
4629.0
4587.5
4546.0
4504.5
4463.0
4421.5
4380.0
4338.5
4297.0
4255.5
4214.0
4172.5
4131.0
4089.5
3962.3
3920.8
649.7
85
50
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
SEG1
SEG2
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
139 VLCDIN
140 VLCDIN
141 VLCDOUT 5258.7
142 VLCDOUT 5328.7
143 COM79
144 COM77
145 COM75
146 COM73
147 COM71
148 COM69
149 COM67
150 COM65
151 COM63
152 COM61
153 COM59
154 COM57
155 COM55
156 COM53
157 COM51
158 COM49
159 DUMMY
160 COM47
161 COM45
162 COM43
163 COM41
164 COM39
165 COM37
166 COM35
167 COM33
168 COM31
169 COM29
170 COM27
171 COM25
172 COM23
173 COM21
174 COM19
175 COM17
176 COM15
177 COM13
178 COM11
5610.6
5660.6
5710.6
5760.6
5810.6
5860.6
5910.6
5960.6
6010.6
6060.6
6110.6
6160.6
6210.6
6260.6
6310.6
6360.6
6868.1
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
6867.6
-44.9
5.1
55.1
105.1
155.1
205.1
255.1
305.1
355.1
405.1
455.1
505.1
555.1
179
180
181
182
183
COM9
COM7
COM5
COM3
COM1
62
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
#
Pad Name
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
X
Y
W
H
#
Pad Name
X
Y
W
H
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
3879.3
3837.8
3796.3
3754.8
3713.3
3671.8
3630.3
3588.8
3547.3
3505.8
3464.3
3422.8
3381.3
3339.8
3298.3
3256.8
3215.3
3173.8
3132.3
3090.8
3049.3
3007.8
2966.3
2924.8
2883.3
2841.8
2800.3
2758.8
2717.3
2675.8
2634.3
2592.8
2551.3
2509.8
2468.3
2426.8
2385.3
2343.8
2302.3
2260.8
2219.3
2177.8
2136.3
2094.8
2053.3
2011.8
1970.3
1928.8
1887.3
1845.8
1804.3
1762.8
1721.3
1679.8
1638.3
1596.8
1555.3
1513.8
1472.3
1430.8
1389.3
1347.8
1306.3
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
310 SEG126
311 SEG127
312 SEG128
313 SEG129
314 SEG130
315 SEG131
316 SEG132
317 SEG133
318 SEG134
319 SEG135
320 SEG136
321 SEG137
322 SEG138
323 SEG139
324 SEG140
325 SEG141
326 SEG142
327 SEG143
328 SEG144
329 SEG145
330 SEG146
331 SEG147
332 SEG148
333 SEG149
334 SEG150
335 SEG151
336 SEG152
337 SEG153
338 SEG154
339 SEG155
340 SEG156
341 SEG157
342 SEG158
343 SEG159
344 SEG160
345 SEG161
346 SEG162
347 SEG163
348 SEG164
349 SEG165
350 SEG166
351 SEG167
352 SEG168
353 SEG169
354 SEG170
355 SEG171
356 SEG172
357 SEG173
358 SEG174
359 SEG175
360 SEG176
361 SEG177
362 SEG178
363 SEG179
364 SEG180
365 SEG181
366 SEG182
367 SEG183
368 SEG184
369 SEG185
370 SEG186
371 SEG187
372 SEG188
1264.8
1223.3
1181.8
1140.3
1098.8
1057.3
1015.8
974.3
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
932.8
891.3
849.8
808.3
766.8
725.3
683.8
642.3
600.8
559.3
517.8
476.3
434.8
393.3
351.8
310.3
268.8
227.3
185.8
144.3
102.8
61.3
19.8
-21.7
-63.2
-104.7
-146.2
-187.7
-229.2
-270.7
-312.2
-353.7
-395.2
-436.7
-478.2
-519.7
-561.2
-602.7
-644.2
-685.7
-727.2
-768.7
-810.2
-851.7
-893.2
-934.7
-976.2
-1017.7
-1059.2
-1100.7
-1142.2
-1183.7
-1225.2
-1266.7
-1308.2
284 SEG100
285 SEG101
286 SEG102
287 SEG103
288 SEG104
289 SEG105
290 SEG106
291 SEG107
292 SEG108
293 SEG109
294 SEG110
295 SEG111
296 SEG112
297 SEG113
298 SEG114
299 SEG115
300 SEG116
301 SEG117
302 SEG118
303 SEG119
304 SEG120
305 SEG121
306 SEG122
307 SEG123
308 SEG124
309 SEG125
Revision 0.6
63
ULTRACHIP
High-Voltage Mixed-Signal IC
©1999~2003
#
Pad Name
X
Y
W
H
#
Pad Name
X
Y
W
H
373 SEG189
374 SEG190
375 SEG191
376 SEG192
377 SEG193
378 SEG194
379 SEG195
380 SEG196
381 SEG197
382 SEG198
383 SEG199
384 SEG200
385 SEG201
386 SEG202
387 SEG203
388 SEG204
389 SEG205
390 SEG206
391 SEG207
392 SEG208
393 SEG209
394 SEG210
395 SEG211
396 SEG212
397 SEG213
398 SEG214
399 SEG215
400 SEG216
401 SEG217
402 SEG218
403 SEG219
404 SEG220
405 SEG221
406 SEG222
407 SEG223
408 SEG224
409 SEG225
410 SEG226
411 SEG227
412 SEG228
413 SEG229
414 SEG230
415 SEG231
416 SEG232
417 SEG233
418 SEG234
419 SEG235
420 SEG236
421 SEG237
422 SEG238
423 SEG239
424 SEG240
425 SEG241
426 SEG242
427 SEG243
428 SEG244
429 SEG245
430 SEG246
431 SEG247
432 SEG248
433 SEG249
434 SEG250
435 SEG251
-1349.7
-1391.2
-1432.7
-1474.2
-1515.7
-1557.2
-1598.7
-1640.2
-1681.7
-1723.2
-1764.7
-1806.2
-1847.7
-1889.2
-1930.7
-1972.2
-2013.7
-2055.2
-2096.7
-2138.2
-2179.7
-2221.2
-2262.7
-2304.2
-2345.7
-2387.2
-2428.7
-2470.2
-2511.7
-2553.2
-2594.7
-2636.2
-2677.7
-2719.2
-2760.7
-2802.2
-2843.7
-2885.2
-2926.7
-2968.2
-3009.7
-3051.2
-3092.7
-3134.2
-3175.7
-3217.2
-3258.7
-3300.2
-3341.7
-3383.2
-3424.7
-3466.2
-3507.7
-3549.2
-3590.7
-3632.2
-3673.7
-3715.2
-3756.7
-3798.2
-3839.7
-3881.2
-3922.7
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
436 SEG252
437 SEG253
438 SEG254
439 SEG255
440 SEG256
441 SEG257
442 SEG258
443 SEG259
444 SEG260
445 SEG261
446 SEG262
447 SEG263
448 SEG264
449 SEG265
450 SEG266
451 SEG267
452 SEG268
453 SEG269
454 SEG270
455 SEG271
456 SEG272
457 SEG273
458 SEG274
459 SEG275
460 SEG276
461 SEG277
462 SEG278
463 SEG279
464 SEG280
465 SEG281
466 SEG282
467 SEG283
468 SEG284
469 SEG285
470 SEG286
471 SEG287
472 SEG288
473 SEG289
474 SEG290
475 SEG291
476 SEG292
477 SEG293
478 SEG294
479 SEG295
480 SEG296
481 SEG297
482 SEG298
483 SEG299
484 SEG300
485 SEG301
486 SEG302
487 SEG303
488 SEG304
489 SEG305
490 SEG306
491 SEG307
492 SEG308
493 SEG309
494 SEG310
495 SEG311
496 SEG312
-3964.2
-4005.7
-4047.2
-4088.7
-4130.2
-4171.7
-4213.2
-4254.7
-4296.2
-4337.7
-4379.2
-4420.7
-4462.2
-4503.7
-4545.2
-4586.7
-4628.2
-4669.7
-4711.2
-4752.7
-4794.2
-4835.7
-4877.2
-4918.7
-4960.2
-5001.7
-5043.2
-5084.7
-5126.2
-5167.7
-5209.2
-5250.7
-5292.2
-5333.7
-5375.2
-5416.7
-5458.2
-5499.7
-5541.2
-5582.7
-5624.2
-5665.7
-5707.2
-5748.7
-5790.2
-5831.7
-5873.2
-5914.7
-5956.2
-5997.7
-6039.2
-6080.7
-6122.2
-6163.7
-6205.2
-6246.7
-6288.2
-6329.7
-6371.2
-6412.7
-6454.2
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
628.6 24.5 123
64
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
TRAY INFORMATION
Revision 0.6
65
ULTRACHIP
High-Voltage Mixed-Signal IC
©1999~2003
COF INFORMATION
4.75 x 5 S.P. = 23.75
1.42(SQ)
7.733 (IC Center)
4.98 Max (Resin Area)
1.NC
2.VLCD
3.VBO-
4.VB1-
5.VB1+
6.VB0+
7.VDD
8.VDD2,3
9.VSS
10.ID
11.VBIAS
12.TST4
13.BM1
14.BM0
15.WR1
16.WR0
17.CD
18.CS0
19.CS1
20.RST
21.DO
22.D1
23.D2
24.D3
25.D4
26.D5
27.D6
28.D7
29.NC
0.5
2 ± 0.2
2.8
12.2± 0.2 (S/R)
2
4.5 (Alignment hole)
17 (Cut line)
66
ES Specifications
UC1682
80x104RGB CSTN Controller-Driver
0.8
0.1
1
2
3
NC
COM 79
COM 77
1
2
3
4
5
6
7
8
9
NC
VLCD
VB0-
0.8
VB1-
40
41
42
43
44
COM 3
COM 1
NC
NC
SEG 1
VB1+
VB0+
VDD
VDD2,3
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
ID
VBIAS
TST4
BM1
BM0
WR1
WR0
CD
CS0
CS1
RST
D0
D1
D2
D3
D4
D5
D6
D7
NC
349
350
351
352
353
354
355
356
357
358
359
SEG 306
SEG 307
SEG 308
SEG 309
SEG 310
SEG 311
SEG 312
NC
NC
COM 2
COM 4
396
397
398
COM 78
COM 80
NC
Input
Output
Revision 0.6
67
ULTRACHIP
High-Voltage Mixed-Signal IC
©1999~2003
REVISION HISTORY
Version
0.0
Contents
Preliminary specification
New release
Date of Rev.
Jul. 10, 2003
Jul. 24, 2003
0.1
Figure 15 “Reference Power-Up Sequence” is updated for OTP.
0.6
Aug. 11, 2003
(Section “Reset & Power Management”, page 46; “Power Up” table, page 47.)
68
ES Specifications
相关型号：
UC1701X
UC1701x is an advanced high-voltage mixed-signal CMOS IC,especially designed for the display needs of ultra-low power hand-held devices.
UTC
©2020 ICPDF网 联系我们和版权申明