UPD160903 [ETC]
UPD160903 Data Sheet | Data Sheet[06/2001] ; UPD160903数据表|数据表[ 06/2001 ]\n
| 型号： | UPD160903 |
| 厂家： | 
ETC |
| 描述： | UPD160903 Data Sheet | Data Sheet[06/2001]
|
| 文件： | 总16页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD160903
384/402-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The µ PD160903 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is
based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 262,144 colors
by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the
output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the LCD’s common
electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line
inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit
whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a
clock frequency of 45 MHz when driving at 2.7 V.
FEATURES
• CMOS level input
• 384/402 outputs
• Input of 6 bits (gray-scale data) by 6 dots
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
• Logic power supply voltage (VDD1): 2.7 to 3.6 V
• Driver power supply voltage (VDD2): 5.5 V ± 0.275 V
• High-speed data transfer: fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.7 V)
• Output dynamic range: VSS2 + 0.1 V to VDD2 – 0.1 V
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output voltage polarity inversion function (POL)
• Display data inversion function (POL21, POL22)
• Single-side mounting is possible (incorporation of slim TCP)
ORDERING INFORMATION
Part Number
Package
µ PD160903N-xxx
TCP (TAB package)
Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our
sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14578EJ1V1DS00 (1st edition)
Date Published June 2001 NS CP (K)
The mark ★ shows major revised points.
Printed in Japan
2000
©
µPD160903
1. BLOCK DIAGRAM
STHR
R,/L
STHL
V
V
DD1
67-bit bidirectional shift register
CLK
STB
SS1
O
sel
C1
C2
C66
C67
D
D
D
00 to
10 to
20 to
D
D
D
05
15
25
D30 to
D40 to
D50 to
D35
D45
D55
Data register
POL21,
POL22
POL
Latch
V
V
DD2
SS2
Level shifter
V
0 to
V
9
D/A converter
Voltage follower output
TEST
S
1
S
2
S
3
S
402
Remark /xxx indicates active low signal.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S
1
S
2
S
401
S
402
5
5
V
0
V
4
Multi-
plexer
6-bit D/A converter
V
5
V
9
POL
2
Data Sheet S14578EJ1V1DS
µPD160903
3. PIN CONFIGURATION (µPD160903N-xxx) (Copper Foil Surface, Face-up)
S402
S401
S400
S399
STHL
D55
D54
D53
D52
D51
D50
D45
D44
D43
D42
D41
D40
D35
D34
D33
D32
D31
D30
VDD1
TEST
R,/L
V9
V8
V7
V6
Copper Foil
Surface
V5
VDD2
VSS2
V4
V3
V2
V1
V0
Osel
VSS1
CLK
STB
POL
POL21
POL22
D25
D24
D23
D22
D21
D20
D15
D14
D13
D12
D11
D10
D05
D04
D03
S4
S3
S2
S1
D02
D01
D00
STHR
Remark This figure does not specify the TCP package.
3
Data Sheet S14578EJ1V1DS
µPD160903
4. PIN FUNCTIONS
(1/2)
Pin Symbol
S1 to S402
Osel
Pin Name
I/O
O
I
Description
Driver output
The D/A converted 64-gray-scale analog voltage is output.
Selection number of
outputs switching
Osel:= H or open: 384 outputs (Output pinsS193 through S210 are invalid)
Osel: = L: 402 outputs
Pulled up internally in the LSI.
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
R,/L
Display data
I
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6
dots (2 pixels).
DX0: LSB, DX5: MSB
Shift direction control
I
Refers to the shift direction control. The shift directions of the shift registers are as
follows.
R,/L = H (right shift): STHR (input), S1 → S402, STHL (output)
R,/L = L (left shift) : STHL (input), S402 → S1, STHR (output)
These refer to the start pulse I/O pins when driver ICs are connected in cascade.
Fetching of display data starts when H is read at the rising edge of CLK.
R,/L = H (right shift): STHR input, STHL output
STHR
STHL
CLK
Right shift start pulse
Left shift start pulse
Shift clock
I/O
I/O
I
R,/L = L (left shift): STHL input, STHR output
A high level should be input as the pulse of one cycle of the clock signal.
If the start pulse input is more than 2CLK, the first 1CLK of the high-level input is
valid.
Refers to the shift register’s shift clock input. The display data is incorporated into
the data register at the rising edge. At the rising edge of the 67th clock (64th clock
in 384 outputs mode) after the start pulse input, the start pulse output reaches the
high level, thus becoming the start pulse of the next-level driver. If 69th clock (66th
clock in 384 mode) pulses are input after input of the start pulse, input of display
data is halted automatically. The contents of the shift register are cleared at the
STB’s rising edge.
STB
POL
Latch
Input
I
The contents of the data register are transferred to the latch circuit at the rising edge.
And, at the falling edge, the gray scale voltage is supplied to the driver after 4CLK .
It is necessary to ensure input of one pulse per horizontal period.
POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output
uses V5 to V9 as the reference supply.
Polarity
POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output
uses V0 to V4 as the reference supply.
S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL
signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge.
Data inversion can invert when display data is loaded.
POL21,
POL22
Data inversion
I
★
POL21: Invert/not invert of display data D00 to D05, D10 to D15, D20 to D25.
POL22: Invert/not invert of display data D30 to D35, D40 to D45, D50 to D55.
POL21, POL22 = H : Display data is inverted.
POL21, POL22 = L : Display data is not inverted.
TEST
Test
I
Normally, TEST = H or open.
This pin is pulled up to the VDD1 power supply inside the IC
V0 to V9
γ -corrected power
−
Input the γ -corrected power supplies from outside by using operational amplifier.
Make sure to maintain the following relationships. During the gray scale voltage
output, be sure to keep the gray scale level power supply at a constant level.
VDD2 − 0.1 V ≥ V0 > V1 > V2 > V3 > V4 > 0.5 VDD2 > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V
supplies
4
Data Sheet S14578EJ1V1DS
µPD160903
(2/2)
Pin Symbol
VDD1
Pin Name
Logic power supply
Driver power supply
Logic ground
I/O
−
Description
2.7 to 3.6 V
5.5 V ± 0.275 V
Grounding
VDD2
−
VSS1
−
VSS2
Driver ground
−
Grounding
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order.
Reverse this sequence to shut.
2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion
of a bypass capacitor of about 0.01 µF is also recommended between the γ -corrected power
supply terminals (V0, V1, V2,....., V9) and VSS2.
5
Data Sheet S14578EJ1V1DS
µPD160903
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The µ PD160903 incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively
gray scale voltages of differing polarity with respect to the LCD’s counter electrode voltage. The D/A converter
consists of ladder resistors and switches.
The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ -compensated voltages to V0’ to V63’
and V0” to V63” is almost equivalent. For the 2 sets of five γ-compensated power supplies, V0 to V4 and V5 to V9,
respectively, input gray scale voltages of the same polarity with respect to the common voltage.
Figure 5–1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2,
common electrode potential VCOM, and γ -corrected voltages V0 to V9 and the input data. Be sure to maintain the
voltage relationships as follows:
V
DD2 – 0.1 V ≥ V
0
> V
1
> V
2
> V
3
> V
4
> 0.5 VDD2 > V
5
> V
6
> V
7
> V
8
> V ≥ VSS2 + 0.1 V
9
Figures 5–2 and 5–3 indicates the relationship between the input data and output voltage and the resistance values
of the resistor strings.
Figure 5–1. Relationship between Input Data and γ -corrected Power Supplies
V
V
DD2
0.1 V
0
16
V
V
V
1
16
16
15
2
3
V
V
4
COM
0.5 VDD2
Split interval
V
5
15
16
16
V
V
6
7
V
8
16
V
9
0.1 V
V
SS2
20
30
10
3F
00
Input data (HEX)
6
Data Sheet S14578EJ1V1DS
µPD160903
Figure 5–2. Relationship between Input Data and Output Voltage
VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 > 0.5 VDD2, POL21, POL22 = L
Resitance ratio
800
750
700
650
600
550
550
500
500
400
400
350
350
350
300
300
300
250
250
250
200
200
200
150
150
150
150
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
150
150
150
200
200
250
250
300
500
800
Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
DX5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DX2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DX1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DX0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
rn
Output voltage
V
0
V
0
'
V0'
V0
r0
r
r
r
r
0
1
2
3
V1'
V1+(V0-V1)× 7250 /
V1+(V0-V1)× 6500 /
V1+(V0-V1)× 5800 /
V1+(V0-V1)× 5150 /
V1+(V0-V1)× 4550 /
V1+(V0-V1)× 4000 /
V1+(V0-V1)× 3450 /
V1+(V0-V1)× 2950 /
V1+(V0-V1)× 2450 /
V1+(V0-V1)× 2050 /
V1+(V0-V1)× 1650 /
V1+(V0-V1)× 1300 /
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
r1
V
V
V
1
'
'
'
V2'
r2
V3'
r3
2
3
V4'
r4
V5'
r5
V6'
r6
V7'
r7
V8'
r8
V9'
r9
V10'
V11'
V12'
V13'
V14'
V15'
V16'
V17
V18'
V19'
V20'
V21'
V22'
V23'
V24'
V25'
V26'
V27'
V28'
V29'
V30'
V31'
V32'
V33'
V34'
V35'
V36'
V37'
V38'
V39'
V40'
V41'
V42'
V43'
V44'
V45'
V46'
V47'
V48'
V49'
V50'
V51'
V52'
V53'
V54'
V55'
V56'
V57'
V58'
V59'
V60'
V61'
V62'
V63'
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r32
r33
r34
r35
r36
r37
r38
r39
r40
r41
r42
r43
r44
r45
r46
r47
r48
r49
r50
r51
r52
r53
r54
r55
r56
r57
r58
r59
r60
r61
r62
r
14
15
V1+(V0-V1)×
V1+(V0-V1)×
V1+(V0-V1)×
V1
950 /
600 /
300 /
V
V
15
'
'
r
V1
16
r
16
17
V2+(V1-V2)× 2450 /
V2+(V1-V2)× 2200 /
V2+(V1-V2)× 1950 /
V2+(V1-V2)× 1700 /
V2+(V1-V2)× 1500 /
V2+(V1-V2)× 1300 /
V2+(V1-V2)× 1100 /
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
V
17
'
r
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2
950 /
800 /
650 /
500 /
400 /
300 /
200 /
100 /
V3+(V2-V3)× 1500 /
V3+(V2-V3)× 1400 /
V3+(V2-V3)× 1300 /
V3+(V2-V3)× 1200 /
V3+(V2-V3)× 1100 /
V3+(V2-V3)× 1000 /
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3
900 /
800 /
700 /
600 /
500 /
400 /
300 /
200 /
100 /
r46
r47
r48
V
V
V
47
'
'
'
V3
48
49
r49
V4+(V3-V4)× 3350 /
V4+(V3-V4)× 3250 /
V4+(V3-V4)× 3150 /
V4+(V3-V4)× 3050 /
V4+(V3-V4)× 2950 /
V4+(V3-V4)× 2800 /
V4+(V3-V4)× 2650 /
V4+(V3-V4)× 2500 /
V4+(V3-V4)× 2300 /
V4+(V3-V4)× 2100 /
V4+(V3-V4)× 1850 /
V4+(V3-V4)× 1600 /
V4+(V3-V4)× 1300 /
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
r
60
61
V
61
'
r
V62
'
r62
V
4
V63
'
V4+(V3-V4)×
V4
800 /
Caution There is no connection between V4 and V5 terminal in the chip.
7
Data Sheet S14578EJ1V1DS
µPD160903
Figure 5–3. Relationship between Input Data and Output Voltage
0.5 VDD2 > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V, POL21, POL22 = L
Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
DX5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DX2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DX1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DX0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
rn
r0
r1
r2
r3
r4
r5
r6
Resistance ratio
800
750
700
650
600
550
550
500
500
400
400
350
350
350
300
300
300
250
250
250
200
200
200
150
150
150
150
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
150
150
150
200
200
250
250
300
500
800
Output voltage
V
V
63''
62''
V
5
V0"
V1"
V2"
V3"
V4"
V5"
V6"
V7"
V9
V9+(V8-V9)×
r
62
61
800 /
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
V9+(V8-V9)× 1550 /
V9+(V8-V9)× 2250 /
V9+(V8-V9)× 2900 /
V9+(V8-V9)× 3500 /
V9+(V8-V9)× 4050 /
V9+(V8-V9)× 4600 /
V9+(V8-V9)× 5100 /
V9+(V8-V9)× 5600 /
V9+(V8-V9)× 6000 /
V9+(V8-V9)× 6400 /
V9+(V8-V9)× 6750 /
V9+(V8-V9)× 7100 /
V9+(V8-V9)× 7450 /
V9+(V8-V9)× 7750
V8
r
V
61''
60''
r
r
60
59
V
r7
r8
r9
V8"
V9"
V10"
V11"
V12"
V13"
V14"
V15"
V16"
V17"
V18"
V19"
V20"
V21"
V22"
V23"
V24"
V25"
V26"
V27"
V28"
V29"
V30"
V31"
V32"
V33"
V34"
V35"
V36"
V37"
V38"
V39"
V40"
V41"
V42"
V43"
V44"
V45"
V46"
V47"
V48"
V49"
V50"
V51"
V52"
V53"
V54"
V55"
V56"
V57"
V58"
V59"
V60"
V61"
V62"
V63"
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r32
r33
r34
r35
r36
r37
r38
r39
r40
r41
r42
r43
r44
r45
r46
r47
r48
r49
r50
r51
r52
r53
r54
r55
r56
r57
r58
r59
r60
r61
r62
r
49
V
V
V
49''
48''
47''
r
r
48
47
V
6
V8+(V7-V8)×
V8+(V7-V8)×
V8+(V7-V8)×
300 /
550 /
800 /
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
r
46
V8+(V7-V8)× 1050 /
V8+(V7-V8)× 1250 /
V8+(V7-V8)× 1450 /
V8+(V7-V8)× 1650 /
V8+(V7-V8)× 1800 /
V8+(V7-V8)× 1950 /
V8+(V7-V8)× 2100 /
V8+(V7-V8)× 2250 /
V8+(V7-V8)× 2350 /
V8+(V7-V8)× 2450 /
V8+(V7-V8)× 2550 /
V8+(V7-V8)× 2650
V7
V7+(V6-V7)×
V7+(V6-V7)×
V7+(V6-V7)×
V7+(V6-V7)×
V7+(V6-V7)×
V7+(V6-V7)×
V7+(V6-V7)×
V7+(V6-V7)×
V7+(V6-V7)×
100 /
200 /
300 /
400 /
500 /
600 /
700 /
800 /
900 /
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
r
r
r
r
17
16
15
14
V
17''
16''
V
V
8
V7+(V6-V7)× 1000 /
V7+(V6-V7)× 1100 /
V7+(V6-V7)× 1200 /
V7+(V6-V7)× 1300 /
V7+(V6-V7)× 1400 /
V7+(V6-V7)× 1500 /
V6
V
15''
V6+(V5-V6)×
V6+(V5-V6)×
V6+(V5-V6)×
V6+(V5-V6)×
V6+(V5-V6)×
V6+(V5-V6)×
V6+(V5-V6)×
V6+(V5-V6)×
100 /
200 /
300 /
400 /
500 /
650 /
800 /
950 /
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
r
2
V
2''
r
r
1
0
V
1
''
V6+(V5-V6)× 1150 /
V6+(V5-V6)× 1350 /
V6+(V5-V6)× 1600 /
V6+(V5-V6)× 1850 /
V6+(V5-V6)× 2150 /
V6+(V5-V6)× 2650 /
V5
V
0
''
V
9
Caution There is no connection between V4 and V5 terminal in the chip.
8
Data Sheet S14578EJ1V1DS
µPD160903
6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format : 6 bits x 2 RGBs (6 dots)
Input width : 36 bits (2-pixel data)
(1) R,/L = H (Right shift)
Output
Data
S1
S2
S3
S4
...
S401
S402
D00 to D05
D10 to D15
D20 to D25
D30 to D35
...
D40 to D45
D50 to D55
(2) R,/L = L (Left shift)
Output
Data
S1
S2
S3
S4
...
...
S401
S402
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
Note
Note
POL
L
S2n–1
S2n
V0 to V4
V5 to V9
V5 to V9
V0 to V4
H
Note S2n–1 (Odd output), S2n (Even output), n = 1, 2, ...... 201
7. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM
The gray-scale voltage is output 4 clocks after the start of D/A conversion in the LSI, in synchronization with the
rising edge of STB.
During this 4-clock period, Hi-Z is output.
STB
POL
S
2n-1
Selected voltage V
0
to V
4
Selected voltage V
5
to V
9
Selected voltage V
0
to V
4
S
2n
Selected voltage V
5
to V
9
Selected voltage V
0
to V
4
Selected voltage V
5
to V
9
Hi-Z
Hi-Z
Hi-Z
9
Data Sheet S14578EJ1V1DS
µPD160903
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS1 = VSS2 = 0 V)
Parameter
Logic Part Supply Voltage
Driver Part Supply Voltage
Logic Part Input Voltage
Driver Part Input Voltage
Logic Part Output Voltage
Driver Part Output Voltage
Operating Ambient Temperature
Storage Temperature
Symbol
VDD1
Rating
Unit
V
–0.5 to +4.0
VDD2
VI1
–0.5 to +10.0
–0.5 to VDD1 + 0.5
–0.5 to VDD2 + 0.5
–0.5 to VDD1 + 0.5
–0.5 to VDD2 + 0.5
–20 to +75
V
V
VI2
V
VO1
VO2
TA
V
V
°C
°C
Tstg
–55 to +125
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = –20 to +75°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
VDD1
Conditions
MIN.
2.7
TYP.
3.3
MAX.
3.6
Unit
V
Logic Part Supply Voltage
Driver Part Supply Voltage
High-Level Input Voltage
Low-Level Input Voltage
γ -Corrected Voltage
VDD2
VIH
5.225
0.7 VDD1
0
5.5
5.775
V
VDD1
V
VIL
0.3 VDD1
VDD2−0.1
0.5 VDD2
VDD2−0.1
45
V
V0 to V4
V5 to V9
VO
0.5 VDD2
0.1
V
V
Driver Part Output Voltage
Clock Frequency
0.1
V
fCLK
MHz
10
Data Sheet S14578EJ1V1DS
µPD160903
Electrical Characteristics (TA = –20 to +75°C, VDD1 = 2.7 to 3.6 V, VDD2 = 5.5 V ± 0.275 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
IIL
Condition
MIN.
VDD1 – 0.1
6.0
TYP.
MAX.
Unit
µA
V
Input Leak Current
±1.0
High-Level Output Voltage
Low-Level Output Voltage
γ -Corrected Resistance
VOH
VOL
Rγ
STHR (STHL), IOH = 0 mA
STHR (STHL), IOL = 0 mA
0.1
V
VDD2 = 5.5 V
12.0
18.0
kΩ
V0 to V4 = V5 to V9 = 2.0 V
Driver Output Current
IVOH
VDD2 = 5.5 V, VX = 5.0 V, VOUT = 4.5 V Note1
VDD2 = 5.5 V, VX = 0.5 V, VOUT = 1.0 V Note1
TA = 25°C, VSS2 + 1.0 V to VDD2 – 1.0 V
–150
250
±5
–70
µA
µA
IVOL
70
Output Voltage Deviation
Output Swing Difference
Deviation
∆VO
±20
±15
±20
±30
6.0
mV
mV
mV
mV
mA
∆VP–P1
∆VP–P2
∆VP–P3
VDD1 = 3.3 V
VDD2 = 5.5 V
TA = 25°C
VOUT = 1.2 to 4.3 V
VOUT = 0.8 to 4.7 V
VOUT = 0.1 to 5.4 V
±3
±7
±15
1.0
Logic Part Dynamic Current IDD1
Consumption Note2,3,4
VDD1
Driver Part Dynamic Current IDD2
Consumption Note2,4
VDD2, with no load
3.7
7.0
mA
Notes 1. VX refers to the output voltage of analog output pins S1 to S402.
VOUT refers to the voltage applied to analog output pins S1 to S402.
2. fSTB = 48 kHz, fCLK = 32.5 MHz
3. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured
values in the dot checkerboard input pattern.
4. Refers to the current consumption per driver when cascades are connected under the assumption of XGA
single-sided mounting (8 units).
Switching Characteristics (TA = –20 to +75°C, VDD1 = 2.7 to 3.6 V, VDD2 = 5.5 V ± 0.275 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
tPLH1
Condition
MIN.
TYP.
9
MAX.
18
Unit
ns
Start Pulse Delay Time
Driver Output Delay Time
CL = 15 pF
Note
Note
Note
Note
tPLH2
tPLH3
tPHL2
tPHL3
CI1
CL = 150 pF, RL = 4.7 kΩ
3.8
5.4
3.3
4.4
5
5.0
8.5
5.0
8.5
10
µs
µs
µs
µs
Input Capacitance
Logic input other than STHR (STHL) is
TA = 25°C
pF
CI2
STHR (STHL),TA = 25°C
8
15
pF
Note tPLH2 and tPHL2 are the time until the voltage reached its target voltage ±10% from the falling edge of STB.
tPLH2 and tPHL2 are the time until the voltage reached its target voltage ±20 mV from the falling edge of STB.
RL
Measurement point
Output
R
L
L
=
=
4.7 kΩ
CL
CL
C
75 pF
11
Data Sheet S14578EJ1V1DS
µPD160903
Timing Requirements (TA = –20 to +75°C, VDD1 = 2.7 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns)
Parameter
Clock Pulse Width
Symbol
PWCLK
Condition
MIN.
22
4
TYP.
MAX.
Unit
ns
Clock Pulse High Period
Clock Pulse Low Period
Data Setup Time
PWCLK(H)
PWCLK(L)
tSETUP1
tHOLD1
ns
4
ns
4
ns
Data Hold Time
2
ns
Start Pulse Setup Time
Start Pulse Hold Time
POL21/22 Setup Time
POL21/22 Hold Time
STB Pulse Width
tSETUP2
tHOLD2
tSETUP3
tHOLD3
4
ns
2
ns
2
ns
3
ns
PWSTB
tLDT
4
CLK
CLK
ns
Last Data Timing
2
CLK-STB Time
tCLK-STB
tSTB-CLK
CLK ↑ → STB ↑
4
STB-CLK Time
STB ↑ → CLK ↑
4
ns
Time Between STB and Start Pulse tSTB-STH
STB ↑ → STHR(STHL) ↑
POL ↑ or ↓ → STB ↑
STB ↓ → POL ↓ or ↑
2
CLK
ns
POL-STB Time
STB-POL Time
tPOL-STB
tSTB-POL
6
6
ns
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
12
Data Sheet S14578EJ1V1DS
µPD160903
Switching Characteristic Waveform(R,/L= H)
★
Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1 (the clock and display data
numbers are examples when the resolution is XGA).
13
Data Sheet S14578EJ1V1DS
µPD160903
9. RECOMMENDED MOUNTING CONDITIONS
The following conditions must be met for mounting conditions of the µPD160903.
For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E).
Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under
different conditions.
µPD160903N-xxx : TCP (TAB Package)
Mounting Condition
Thermocompression
Mounting Method
Soldering
Condition
Heating tool 300 to 350°C, heating for 2 to 3 seconds : pressure 100g
(per solder)
ACF
Temporary bonding 70 to 100°C : pressure 3 to 8 kg/cm2: time 3 to 5 sec.
Real bonding 165 to 180°C: pressure 25 to 45 kg/cm2: time 30 to 40 sec.
(When using the anisotropy conductive film SUMIZAC1003 of Sumitomo
Bakelite,Ltd).
(Adhesive
Conductive Film)
Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF
manufacturing company. Be sure to avoid using two or more mounting methods at a time.
14
Data Sheet S14578EJ1V1DS
µPD160903
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
15
Data Sheet S14578EJ1V1DS
µPD160903
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Quality Grades to NEC’s Semiconductor Devices (C11531E)
•
The information in this document is current as of June, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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