UPD16732E [ETC]
UPD16732E Data Sheet | Data Sheet[06/2002] ; UPD16732E数据表|数据表[ 06/2002 ]\n
| 型号： | UPD16732E |
| 厂家： | 
ETC |
| 描述： | UPD16732E Data Sheet | Data Sheet[06/2002]
|
| 文件： | 总20页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16732E
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The µPD16732E is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is
based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors
by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the
output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the LCD’s common
electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line
inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit
whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a
maximum clock frequency of 65 MHz when driving at 3.0 V, 45 MHz when driving at 2.3 V, this driver is applicable to
XGA-standard TFT-LCD panels and SXGA-standard TFT-LCD panels.
FEATURES
• CMOS level input (2.3 to 3.6 V)
• 384 outputs
• Input of 6 bits (gray-scale data) by 6 dots
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
• Logic power supply voltage (VDD1): 2.3 to 3.6 V
• Driver power supply voltage (VDD2): 8.0 to 9.0 V
• Output dynamic range: VSS2 + 0.1 V to VDD2 – 0.1 V
• High-speed data transfer: fCLK = 65 MHz (internal data transfer speed when operating at VDD1 = 3.0 V)
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output voltage polarity inversion function (POL)
• Display data inversion function (capable of controlling by each input port) (POL21, POL22)
• Current consumption reduction function (LPC, Bcont)
• Succession of µPD16732B driver
ORDERING INFORMATION
Part Number
Package
µPD16732EN-xxx
TCP (TAB package)
Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our
sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15187EJ2V0DS00 (2nd edition)
Date Published June 2002 NS CP (K)
The mark ★ shows major revised points.
2001
©
Printed in Japan
µPD16732E
1. BLOCK DIAGRAM
STHR
R,/L
CLK
STB
STHL
V
V
DD1
64-bit bidirectional shift register
SS1
C1
C2
C63
C64
D
D
D
D
D
D
00 to
10 to
20 to
30 to
40 to
50 to
D
D
D
D
D
D
05
15
25
Data register
35
45
55
POL21,
POL22
Latch
POL
V
V
DD2
SS2
Level shifter
V
0
to
V
9
D/A converter
Voltage follower output
LPC
Bcont
S
1
S
2
S
3
S
384
Remark /xxx indicates active low signal.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S
1
S
2
S
383
S
384
5
5
V
0
V
4
Multi-
plexer
6-bit D/A converter
V
5
V
9
POL
2
Data Sheet S15187EJ2V0DS
µPD16732E
3. PIN CONFIGURATION (Top of copper foil surface, face-up)
µPD16732EN-xxx: TCP (TAB package)
S384
S383
S382
S381
STHL
D55
D54
D53
D52
D51
D50
D45
D44
D43
D42
D41
D40
D35
D34
D33
D32
D31
D30
VDD1
R,/L
V9
V8
V7
V6
V5
VDD2
Copper foil
surface
VSS2
Bcont
V4
V3
V2
V1
V0
VSS1
LPC
CLK
STB
POL
POL21
POL22
D25
D24
D23
D22
D21
D20
D15
D14
D13
D12
D11
D10
D05
D04
S4
S3
S2
S1
D03
D02
D01
D00
STHR
Remark This figure does not specify the TCP package.
3
Data Sheet S15187EJ2V0DS
µPD16732E
4. PIN FUNCTIONS
(1/2)
Pin Symbol
S1 to S384
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
R,/L
Pin Name
I/O
Description
Driver output
Output The D/A converted 64-gray-scale analog voltage is output.
Display data input
Input The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6
dots (2 pixels).
DX0: LSB, DX5: MSB
Shift direction control Input The shift direction control pin of the shift register. The shift directions of the shift
registers are as follows.
R,/L = H (right shift): STHR (input), S1 → S384, STHL (output)
R,/L = L (left shift) : STHL (input), S384 → S1, STHR (output)
STHR
STHL
CLK
Right shift start pulse
Left shift start pulse
Shift clock
I/O
I/O
These refer to the start pulse I/O pins when the IC is connected in cascade.
Loading of display data starts when a high level is read at the rising edge of CLK.
A high level should be input as the pulse of one cycle of the clock signal.
If the start pulse input is more than 2CLK, the first 1CLK of the high-level input is valid.
R,/L = H (right shift): STHR input, STHL output
R,/L = L (left shift): STHL input, STHR output
Input This pi refers to the shift register’s shift clock input. The display data is incorporated
into the data register at the rising edge. At the rising edge of the 64th after the start
pulse input, the start pulse output reaches the high level, thus becoming the start pulse
of the next-level driver. When the 66 clock pulses are input after input of the start
pulse, input of display data is halted automatically. The contents of the shift register
are cleared at the STB’s rising edge.
STB
POL
Latch
Input The contents of the data register are transferred to the latch circuit at the rising edge.
And, at the falling edge, the gray scale voltage is supplied to the driver.
It is necessary to ensure input of one pulse per horizontal period.
Input POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output uses
V5 to V9 as the reference supply.
Polarity
POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses
V0 to V4 as the reference supply.
S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL
signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge.
Input Data inversion can invert when display data is loaded.
POL21,
POL22
Data inversion
POL21: D00 to D05, D10 to D15, D20 to D25 Data inversion or no inversion of Port1
POL22: D30 to D35, D40 to D45, D50 to D55 Data inversion or no inversion of Port2
POL21,POL22 = H: Data inversion loads display data inside the IC.
POL21,POL22 = L: Data inversion does not invert input data.
LPC
Low power control
Input The current consumption is lowered by controlling the constant current source of the
output amplifier. In low power mode (LPC = L), the VDD2 of static current consumption
can be reduced to two thirds of the normal current consumption. This pin is pulled up to
the VDD1 power supply inside the IC.
LPC = H or open: Normal power mode
LPC = L: Low power mode
Bcont
Bias control
Input This pin can be used to finely control the bias current inside the output amplifier. In
cases when fine-control is necessary, connect this pin to the stabilized ground potential
(VSS2) via an external resistor of 10 to 100 kΩ (per IC).
When this fine-control function is not required, leave this pin open.
Refer to 9. CURRENT CONSUMPTION REDUCTION FUNCTION
4
Data Sheet S15187EJ2V0DS
µPD16732E
(2/2)
Pin Symbol
V0 to V9
Pin Name
I/O
Description
γ -corrected power
−
Input the γ -corrected power supplies from outside by using operational amplifier.
supplies
Make sure to maintain the following relationships. During the gray scale voltage output,
be sure to keep the gray scale level power supply at a constant level.
VDD2 − 0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2
0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V
VDD1
VDD2
VSS1
VSS2
Logic power supply
Driver power supply
Logic ground
−
−
−
−
2.3 to 3.6 V
8.0 to 9.0 V
Grounding
Grounding
Driver ground
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order.
Reverse this sequence to shut down (Simultaneous power application to VDD2 and V0 to V9 is
possible.).
2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion
of a bypass capacitor of about 0.01 µF is also recommended between the γ -corrected power
supply terminals (V0, V1, V2,....., V9) and VSS2.
5
Data Sheet S15187EJ2V0DS
µPD16732E
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The µPD16732E incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively
gray scale voltages of differing polarity with respect to the LCD’s counter electrode voltage. The D/A converter
consists of ladder resistors and switches. The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel
γ -compensated voltages to V0’ to V63’ and V0” to V63” is almost equivalent as shown in Figure 5-2. For the 2 sets of
five γ -compensated power supplies, V0 to V4 and V5 to V9, respectively, input gray scale voltages of the same polarity
with respect to the common voltage. When fine-gray scale voltage precision is not necessary, there is no need to
connect voltage follower circuit to the γ –corrected power supplies V1 to V3 and V6 to V8.
Figure 5–1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2, VSS2 and
γ -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage relationships as follows.
V
DD2 – 0.1 V ≥ V
0
> V
1
> V
2
> V
3
> V
4
≥ 0.5 VDD2,
0.5 VDD2 ≥ V > V
5
6
> V
7
> V
8
> V
9
≥ VSS2 + 0.1 V
Figures 5–2 indicates γ -corrected voltages and ladder resistors ratio. Figures 5–3 indicates the relationship
between the input data and output voltage and the resistance values of the resistor string.
Figure 5–1. Relationship between Input Data and γ -corrected Power Supplies
VDD2
0.1 V
V0
16
V1
16
V2
16
V3
15
V4
0.5 VDD2
V5
Split interval
15
V6
16
16
V7
V8
16
V9
0.1 V
VSS2
00
10
20
30
3F
Input Data (HEX)
6
Data Sheet S15187EJ2V0DS
µPD16732E
Figure 5–2. γ -corrected Voltages and Ladder Resistor’s Ratio
★
rn
r0
r1
r2
r3
r4
r5
r6
Ratio1
11.62
4.84
3.72
3.35
2.61
2.24
1.86
1.86
1.49
1.49
1.12
1.12
1.12
1.12
1.12
1.12
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.15
1.15
1.15
1.15
1.15
1.53
1.53
1.53
1.53
1.90
2.27
2.64
2.64
3.02
5.74
Ratio2
0.1114
0.0464
0.0357
0.0321
0.0250
0.0214
0.0179
0.0179
0.0143
0.0143
0.0107
0.0107
0.0107
0.0107
0.0107
0.0107
0.0096
0.0096
0.0096
0.0096
0.0096
0.0096
0.0096
0.0096
0.0096
0.0096
0.0096
0.0096
0.0096
0.0096
0.0096
0.0096
0.0098
0.0098
0.0098
0.0098
0.0098
0.0098
0.0098
0.0098
0.0098
0.0098
0.0098
0.0098
0.0098
0.0098
0.0098
0.0098
0.0110
0.0110
0.0110
0.0110
0.0110
0.0146
0.0146
0.0146
0.0146
0.0182
0.0218
0.0254
0.0254
0.0290
0.0550
Value (Ω)
1766
736
566
509
396
340
283
283
226
226
170
170
170
170
170
170
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
175
175
175
175
175
232
232
232
232
289
345
402
402
459
872
V
0
V
0
'
V
V
V
V
63''
62''
61''
60''
V
5
r
62
r
r
r
r
0
1
2
3
V
V
V
1
'
'
'
r
61
60
2
3
r
r59
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r32
r33
r34
r35
r36
r37
r38
r39
r40
r41
r42
r43
r44
r45
r46
r47
r48
r49
r50
r51
r52
r53
r54
r55
r56
r57
r58
r59
r60
r61
r62
r
14
15
r
49
V
49''
48''
V
15
'
'
r
r48
r47
r46
V
1
V
16
V
V
6
r
16
17
V
17
'
V47''
r
r46
r47
r48
r17
r16
r15
r14
V
17''
16''
V
V
V
47
'
'
'
V
V
3
48
V8
V
15''
49
r49
r
60
61
r
2
V
61
'
V2''
r
r
1
V62
'
V
1
''
r62
r0
V
4
V9
V63
'
V0
''
Caution There is no connection between V4 and V5 terminal in the IC.
Remark The resistance ratio1 is a relative ratio in the case of setting the minimum resistance value to 1.
The resistance ratio2 is a relative ratio in the case of setting the total resistance to 1.
7
Data Sheet S15187EJ2V0DS
µPD16732E
★
Figure 5–3. Relationship between Input Data and Output Voltage (POL21, POL22 = L)
(Output Voltage 1) VDD2 – 0.1 V ≥ V5 > V6 > V7 > V8 > V9 ≥ 0.5 VDD2,
(Output Voltage 2) 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V
Input Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Output Voltage1
Output Voltage2
V0' V0
V0'' V9
V1' V1+(V0-V1)× 4585/6351
V2' V1+(V0-V1)× 3849/6351
V3' V1+(V0-V1)× 3283/6351
V4' V1+(V0-V1)× 2774/6351
V5' V1+(V0-V1)× 2378/6351
V6' V1+(V0-V1)× 2038/6351
V7' V1+(V0-V1)× 1755/6351
V8' V1+(V0-V1)× 1472/6351
V9' V1+(V0-V1)× 1246/6351
V1'' V9+(V8-V9)× 1766/6351
V2'' V9+(V8-V9)× 2502/6351
V3'' V9+(V8-V9)× 3068/6351
V4'' V9+(V8-V9)× 3577/6351
V5'' V9+(V8-V9)× 3973/6351
V6'' V9+(V8-V9)× 4313/6351
V7'' V9+(V8-V9)× 4596/6351
V8'' V9+(V8-V9)× 4879/6351
V9'' V9+(V8-V9)× 5105/6351
V10' V1+(V0-V1)× 1020/6351 V10'' V9+(V8-V9)× 5331/6351
V11' V1+(V0-V1)× 850/6351
V12' V1+(V0-V1)× 680/6351
V13' V1+(V0-V1)× 510/6351
V14' V1+(V0-V1)× 340/6351
V15' V1+(V0-V1)× 170/6351
V16' V1
V11'' V9+(V8-V9)× 5501/6351
V12'' V9+(V8-V9)× 5671/6351
V13'' V9+(V8-V9)× 5841/6351
V14'' V9+(V8-V9)× 6011/6351
V15'' V9+(V8-V9)× 6181/6351
V16'' V8
V17' V2+(V1-V2)× 2280/2432 V17'' V8+(V7-V8)× 152/2432
V18' V2+(V1-V2)× 2128/2432 V18'' V8+(V7-V8)× 304/2432
V19' V2+(V1-V2)× 1976/2432 V19'' V8+(V7-V8)× 456/2432
V20' V2+(V1-V2)× 1824/2432 V20'' V8+(V7-V8)× 608/2432
V21' V2+(V1-V2)× 1672/2432 V21'' V8+(V7-V8)× 760/2432
V22' V2+(V1-V2)× 1520/2432 V22'' V8+(V7-V8)× 912/2432
V23' V2+(V1-V2)× 1368/2432 V23'' V8+(V7-V8)× 1064/2432
V24' V2+(V1-V2)× 1216/2432 V24'' V8+(V7-V8)× 1216/2432
V25' V2+(V1-V2)× 1064/2432 V25'' V8+(V7-V8)× 1368/2432
V26' V2+(V1-V2)× 912/2432
V27' V2+(V1-V2)× 760/2432
V28' V2+(V1-V2)× 608/2432
V29' V2+(V1-V2)× 456/2432
V30' V2+(V1-V2)× 304/2432
V31' V2+(V1-V2)× 152/2432
V32' V2
V26'' V8+(V7-V8)× 1520/2432
V27'' V8+(V7-V8)× 1672/2432
V28'' V8+(V7-V8)× 1824/2432
V29'' V8+(V7-V8)× 1976/2432
V30'' V8+(V7-V8)× 2128/2432
V31'' V8+(V7-V8)× 2280/2432
V32'' V7
V33' V3+(V2-V3)× 2340/2496 V33'' V7+(V6-V7)× 156/2496
V34' V3+(V2-V3)× 2184/2496 V34'' V7+(V6-V7)× 312/2496
V35' V3+(V2-V3)× 2028/2496 V35'' V7+(V6-V7)× 468/2496
V36' V3+(V2-V3)× 1872/2496 V36'' V7+(V6-V7)× 624/2496
V37' V3+(V2-V3)× 1716/2496 V37'' V7+(V6-V7)× 780/2496
V38' V3+(V2-V3)× 1560/2496 V38'' V7+(V6-V7)× 936/2496
V39' V3+(V2-V3)× 1404/2496 V39'' V7+(V6-V7)× 1092/2496
V40' V3+(V2-V3)× 1248/2496 V40'' V7+(V6-V7)× 1248/2496
V41' V3+(V2-V3)× 1092/2496 V41'' V7+(V6-V7)× 1404/2496
V42' V3+(V2-V3)× 936/2496
V43' V3+(V2-V3)× 780/2496
V44' V3+(V2-V3)× 624/2496
V45' V3+(V2-V3)× 468/2496
V46' V3+(V2-V3)× 312/2496
V47' V3+(V2-V3)× 156/2496
V48' V3
V42'' V7+(V6-V7)× 1560/2496
V43'' V7+(V6-V7)× 1716/2496
V44'' V7+(V6-V7)× 1872/2496
V45'' V7+(V6-V7)× 2028/2496
V46'' V7+(V6-V7)× 2184/2496
V47'' V7+(V6-V7)× 2340/2496
V48'' V6
V49' V4+(V3-V4)× 4397/4572 V49'' V6+(V5-V6)× 175/4572
V50' V4+(V3-V4)× 4222/4572 V50'' V6+(V5-V6)× 350/4572
V51' V4+(V3-V4)× 4047/4572 V51'' V6+(V5-V6)× 525/4572
V52' V4+(V3-V4)× 3872/4572 V52'' V6+(V5-V6)× 700/4572
V53' V4+(V3-V4)× 3697/4572 V53'' V6+(V5-V6)× 875/4572
V54' V4+(V3-V4)× 3465/4572 V54'' V6+(V5-V6)× 1107/4572
V55' V4+(V3-V4)× 3233/4572 V55'' V6+(V5-V6)× 1339/4572
V56' V4+(V3-V4)× 3001/4572 V56'' V6+(V5-V6)× 1571/4572
V57' V4+(V3-V4)× 2769/4572 V57'' V6+(V5-V6)× 1803/4572
V58' V4+(V3-V4)× 2480/4572 V58'' V6+(V5-V6)× 2092/4572
V59' V4+(V3-V4)× 2135/4572 V59'' V6+(V5-V6)× 2437/4572
V60' V4+(V3-V4)× 1733/4572 V60'' V6+(V5-V6)× 2839/4572
V61' V4+(V3-V4)× 1331/4572 V61'' V6+(V5-V6)× 3241/4572
V62' V4+(V3-V4)× 872/4572
V63' V4
V62'' V6+(V5-V6)× 3700/4572
V63'' V5
Caution There is no connection between V4 and V5 terminal in the IC.
8
Data Sheet S15187EJ2V0DS
µPD16732E
6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format : 6 bits x 2 RGBs (6 dots)
Input width : 36 bits (2-pixel data)
(1) R,/L = H (Right shift)
Output
Data
S1
S2
S3
S4
...
S383
S384
D00 to D05
D10 to D15
D20 to D25
D30 to D35
...
D40 to D45
D50 to D55
(2) R,/L = L (Left shift)
Output
Data
S1
S2
S3
S4
...
...
S383
S384
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
Note
Note
POL
L
S2n–1
S2n
V0 to V4
V5 to V9
V5 to V9
V0 to V4
H
Note S2n–1 (Odd output), S2n (Even output)
7. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge.
STB
POL
S
2n-1
Selected voltage V
0
toV
4
Selected voltage V
5
toV
9
Selected voltage V
0
toV
4
S
2n
Selected voltage V
0
toV
4
Selected voltage V
5
toV
9
Selected voltage V
5
toV
9
Hi-Z
Hi-Z
Hi-Z
9
Data Sheet S15187EJ2V0DS
µPD16732E
8. RELATIONSHIP BETWEEN STB, CLK, AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge.
Figure 8–1. Output Circuit Block Diagram
Output Amp
-
+
DAC
SW1
Sn
(V
x
)
V
AMP(IN)
Figure 8–2. Output Circuit Block Diagram
[1]
[2]
CLK
(External Input)
STB
(External Input)
SW1 : ON
SW1 : OFF
SW1 : ON
V
AMP(IN)
S
n
(Vx
)
Output
Hi-Z
Output
Remarks 1. STB = L: SW1 = ON
STB = H: SW1 = OFF
2. STB = H is acknowledged at timing [1].
3. The display data latch is completed at timing [2] and the input voltage
(VAMP(IN): gray-scale level voltage) of the output amplifier changes.
10
Data Sheet S15187EJ2V0DS
µPD16732E
9. CURRENT CONSUMPTION REDUCTION FUNCTION
The µPD16732E has a low power control function (LPC) which can switch the bias current of the output amplifier
between two levels and a bias control function (Bcont) which can be used to finely control the bias current.
<Low power control function (LPC)>
The bias current of the output amplifier can be switched between two levels using this pin. (Bcont: open)
LPC = H or open: normal power mode
LPC = L: low power mode
The VDD2 of static current consumption can be reduced to two thirds of that in normal mode, input a stable DC
current (VDD1/VSS1) to this pin.
<Bias current control function (Bcont)>
It is possible to fine-control the current consumption by using the bias current control function (Bcont pin). When
using this function, connect this pin to the stabilized ground potential (VSS2) via an external resistor (REXT). When not
using this function, leave this pin open.
Figure 9–1. Bias Current Control Function (Bcont)
PD16732E
µ
B
cont
LPC
REXT
H/L
V
SS2
Refer to the table below for the percentage of current regulation when using the bias current control-function.
Table 9–1. Current Consumption Regulation Percentage Compared to Normal Mode
(VDD1 = 3.3 V, VDD2 = 8.7 V, LPC = 3.3 V/ 0 V)
REXT (kΩ)
Current Consumption Regulation Percentage (%)
LPC = H
100
LPC = L
65
∞ (Open)
50
20
10
110
70
115
80
120
85
Remark Be aware that the above current consumption regulation percentages are not
product-characteristic guaranteed as they are based on the results of simulation.
Caution Because the low-power and bias-current control functions control the bias current in the output
amplifier and regulate the over-all current consumption of the driver IC, when this occurs, the
characteristics of the output amplifier will simultaneously change. Therefore, when using these
functions, be sure to sufficiently evaluate the picture quality.
11
Data Sheet S15187EJ2V0DS
µPD16732E
Figure9−2. Output Wave Form (LPC = L)
Bcont = 1.0 kΩ
Bcont = Open
µs / div)
Time (4
Bcont = 10 kΩ
Bcont = 50 kΩ
[1]
[2]
<Test Condition>
[1]
R
[2]
RL
RL
L
RL
RL
R
L
L
= 1 kΩ
-
+
V
IN
C
= 15 pF
CL
CL
CL
CL
CL
12
Data Sheet S15187EJ2V0DS
µPD16732E
Figure9−3. Output Wave Form (LPC = H)
Bcont = Open
Bcont = 1.0 kΩ
µs / div)
Time (4
Bcont = 10 kΩ
Bcont = 50 kΩ
13
Data Sheet S15187EJ2V0DS
µPD16732E
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
VDD1
Rating
Unit
V
Logic Part Supply Voltage
Driver Part Supply Voltage
Logic Part Input Voltage
Driver Part Input Voltage
Logic Part Output Voltage
Driver Part Output Voltage
Operating Ambient Temperature
Storage Temperature
–0.5 to +4.0
VDD2
VI1
–0.5 to +10.0
–0.5 to VDD1 + 0.5
–0.5 to VDD2 + 0.5
–0.5 to VDD1 + 0.5
–0.5 to VDD2 + 0.5
–10 to +75
V
V
VI2
V
VO1
VO2
TA
V
V
°C
°C
Tstg
–55 to +125
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V)
Parameter
Logic Part Supply Voltage
Driver Part Supply Voltage
High-Level Input Voltage
Low-Level Input Voltage
γ -Corrected Voltage
Symbol
VDD1
Condition
MIN.
2.3
TYP.
8.5
MAX.
3.6
Unit
V
VDD2
VIH
8.0
9.0
V
0.7 VDD1
0
VDD1
V
VIL
0.3 VDD1
VDD2 – 0.1
0.5 VDD2
VDD2 – 0.1
45
V
V0 to V4
V5 to V9
VO
0.5 VDD2
VSS2 + 0.1
VSS2 + 0.1
V
V
Driver Part Output Voltage
Clock Frequency
V
fCLK
2.3 ≤ VDD1 < 3.0 V
3.0 ≤ VDD1 ≤ 3.6 V
MHz
MHz
65
14
Data Sheet S15187EJ2V0DS
µPD16732E
Electrical Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.0 to 9.0 V, VSS1 = VSS2 = 0 V,
Unless otherwise specified, LPC = H or open, Bcont = open)
Parameter
Input Leak Current
Symbol
IIL
Condition
MIN.
TYP.
MAX.
Unit
µA
V
±1.0
High-Level Output Voltage
Low-Level Output Voltage
γ -Corrected Resistance
Driver Output Current
VOH
VOL
Rγ
STHR (STHL), IOH = 0 mA
STHR (STHL), IOL = 0 mA
V0 to V4 = V5 to V9 = 4.0 V
VX = 7.0 V, VOUT = 6.5 V Note
VX = 1.0 V, VOUT = 1.5 V Note
VDD1 = 3.3 V, VDD2 = 8.5 V
VOUT = 2.0 V, 4.25 V, 6.5 V
VDD1 – 0.1
0.1
32
V
8
16
Ω
★
IVOH
IVOL
∆VO
∆VP–P
–30
µA
µA
mV
mV
30
Output Voltage Deviation
Output Swing Difference
Deviation
±7
±2
±20
±15
Output Voltage Range
Logic Part Dynamic Current
Consumption
VO
All input data
0.1
VDD2 – 0.1
6.0
V
IDD1
VDD1, with no load
3.0
1.0
2.0
mA
★
★
Driver Part Dynamic Current
Consumption
IDD21
VDD2 = 8.0 to 9.0 V, with no load,
LPC =H, Bcont = open
6.0
4.0
mA
mA
IDD22
VDD2 = 8.0 to 9.0 V, with no load,
LPC =L, Bcont = open
Note VX refers to the output voltage of analog output pins S1 to S384.
VOUT refers to the voltage applied to analog output pins S1 to S384.
Cautions 1. STB cycle is 20 µs, fCLK = 40 MHz
2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the
measured values in the dot checkerboard input pattern.
3. Refers to the current consumption per driver when cascades are connected under the
assumption of XGA single-sided mounting (8 units).
15
Data Sheet S15187EJ2V0DS
µPD16732E
Switching Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.0 to 9.0 V, VSS1 = VSS2 = 0 V,
Unless otherwise specified, LPC = H or open, Bcont = open)
Parameter
Symbol
tPLH1
Condition
CL = 10 pF, 2.3 ≤ VDD1 < 3.0 V
CL = 10 pF, 3.0 ≤ VDD1 ≤ 3.6 V
CL = 75 pF, RL = 5 kΩ
MIN.
TYP.
10
7
MAX.
17
10.5
5
Unit
ns
ns
µs
µs
µs
µs
pF
pF
Start Pulse Delay Time
Driver Output Delay Time
tPLH2
tPLH3
tPHL2
tPHL3
CI1
2.5
5
8
2.5
5
5
8
Input Capacitance
Exclude STHR (STHL), TA = 25°C
STHR (STHL),TA = 25°C
5
10
10
CI2
8
<Test Condition>
RL1
RL2
RL4
RL3
RL5
R
Ln = 1 kΩ
Ln = 15 pF
C
Output
CL5
CL4
CL2
CL3
CL1
Timing Requirements (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 8.0 ns)
Parameter
Clock Pulse Width
Symbol
PWCLK
Condition
2.3 ≤ VDD1 < 3.0 V
3.0 ≤ VDD1 ≤ 3.6 V
MIN.
22
15
4
TYP.
MAX.
Unit
ns
ns
Clock Pulse High Period
Clock Pulse Low Period
PWCLK(H)
PWCLK(L)
ns
2.3 ≤ VDD1 < 3.0 V
3.0 ≤ VDD1 ≤ 3.6 V
6
ns
4
ns
Data Setup Time
Data Hold Time
tSETUP1
tHOLD1
tSETUP2
tHOLD2
tSETUP3
tHOLD3
PWSTB
tLDT
4
ns
0
ns
Start Pulse Setup Time
Start Pulse Hold Time
POL21/22 Setup Time
POL21/22 Hold Time
STB Pulse Width
Last Data Timing
CLK-STB Time
4
ns
0
ns
4
ns
0
ns
2
CLK
CLK
ns
2
tCLK-STB
tSTB-CLK
CLK ↑ → STB ↑
6
STB-CLK Time
STB ↑ → CLK ↑,
9
ns
VDD1 = 2.3 to 3.6 V
STB ↑ → CLK ↑,
6
ns
VDD1 = 3.0 to 3.6 V
STB ↑ → STHR(STHL) ↑
POL ↑ or ↓ → STB ↑
STB ↓ → POL ↓ or ↑
Time Between STB and Start Pulse
POL-STB Time
tSTB-STH
tPOL-STB
tSTB-POL
2
–5
6
CLK
ns
STB-POL Time
ns
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
16
Data Sheet S15187EJ2V0DS
PWCLK(L) PWCLK
PWCLK(H)
t
r
t
f
1
2
V
V
DD1
SS1
90%
1
2
3
64
65
66
513
514
CLK
10%
t
SETUP2
t
HOLD2
t
STB-CLK
t
CLK-STB
V
V
DD1
SS1
STHR
(1st Dr.)
t
SETUP1
t
HOLD1
t
STB-STH
V
V
DD1
SS1
D
D
373 to
D
D
379 to
D
D
385 to
D
D
3067 to
D1
to D
6
D7 to D12
D
n0 to Dn5
INVALID
INVALID
D1
to D
6
D
7
to D12
INVALID
378
384
390
3072
t
SETUP3
t
HOLD3
V
DD1
SS1
POL21,
POL22
INVALID
V
t
PLH1
V
V
DD1
SS1
STHL
(1st Dr.)
t
LDT
PWSTB
V
V
DD1
SS1
STB
POL
t
POL-STB
t
STB-POL
V
V
DD1
SS1
t
t
PLH3
Hi-Z
PLH2
Target Voltage +0.1 VDD2
6-bit accuracy
Sn
(Vx)
µ
µ
t
t
PHL2
PHL3
µPD16732E
11. RECOMMENDED MOUNTING CONDITIONS
The following conditions must be met for mounting conditions of the µPD16732E.
For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E).
Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under
different conditions.
µPD16732EN-xxx : TCP (TAB Package)
Mounting Condition
Thermocompression
Mounting Method
Soldering
Condition
Heating tool 300 to 350°C, heating for 2 to 3 seconds : pressure 100g
(per solder)
ACF
Temporary bonding 70 to 100°C : pressure 3 to 8 kg/cm2: time 3 to 5
sec. Real bonding 165 to 180°C: pressure 25 to 45 kg/cm2: time 30 to
40 sec. (When using the anisotropy conductive film SUMIZAC1003 of
Sumitomo Bakelite,Ltd).
(Adhesive
Conductive Film)
Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF
manufacturing company. Be sure to avoid using two or more mounting methods at a time.
18
Data Sheet S15187EJ2V0DS
µPD16732E
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
19
Data Sheet S15187EJ2V0DS
µPD16732E
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Quality Grades On NEC Semiconductor Devices (C11531E)
•
The information in this document is current as of June, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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