UPD16738N-XXX [ETC]
Interface IC ; 接口IC\n
| 型号： | UPD16738N-XXX |
| 厂家： | 
ETC |
| 描述： | Interface IC
|
| 文件： | 总16页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16738
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES )
DESCRIPTION
The µPD16738 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is based
on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64
values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as
large as VSS2+0.1 V to VDD2–0.1 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also,
to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this
source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively
output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 45 MHz when driving at 2.7 V, this
driver is applicable to XGA-standard TFT-LCD panels.
FEATURES
• CMOS level input
• 384 Outputs
• Input of 6 bits (gradation data) by 6 dots
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and
a D/A converter
+0.3
–0.6
+0.5
• Logic power supply voltage (VDD1) : 3.3 V
• Driver power supply voltage (VDD2) : 8.5 V
V
V
–1.0
• High-speed data transfer : fCLK = 45 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.7 V)
• Output dynamic range : VSS2 + 0.1 V to VDD2 – 0.1 V
•
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output Voltage polarity inversion function (POL)
• Display data inversion function (POL2)
• Single bank arrangement is possible (Loaded with slim or bending TCP)
ORDERING INFORMATION
Part Number
Package
µPD16738N -×××
TCP (TAB package)
Remark The TCP’s external shape is customized. To order your TCP’s external shape, please contact a
NEC salesperson.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
•
The mark shows major revised points.
Document No. S13813EJ1V0DS00 (1st edition)
Data Published January 2000 NS CP(K)
Printed in Japan
NEC Corporation 1999
µ PD16738
BLOCK DIAGRAM
STHR
R,/L
CLK
STB
STHL
VDD1
64-bit bidirectional shift register
VSS1
C1
C2
C63
C64
D
D
D
D
D
D
00 -
D
D
D
D
D
D
05
10 -
15
20 -
25
Data register
30 -
40 -
50 -
35
45
55
POL2
Latch
POL
V
DD2
SS2
Level shifter
V
V0 -
V9
D/A converter
Voltage follower output
VSEL
S1
S2
S3
S384
Remark /xxx indicates active low signal.
RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S1
S2
S383
S384
5
5
V
0
V
4
Multi-
plexer
6-bit D/A converter
V
5
V
9
POL
2
Data Sheet S13813EJ1V0DS00
µ PD16738
PIN CONFIGURATION (µPD16738N-××× : TCP (TAB package) )
SS2
384
383
382
381
V
S
S
S
S
DD2
V
R,/L
POL
STB
55
D
54
D
53
D
52
D
51
D
50
D
45
D
44
D
43
D
42
D
41
D
40
D
35
D
34
D
33
D
Copper Foil
Surface
32
D
31
D
30
D
STHL
9
V
8
V
7
V
6
V
5
V
4
V
3
V
2
V
1
V
0
V
DD1
V
CLK
SEL
V
SS1
V
STHR
25
D
24
D
23
D
22
D
21
D
20
D
15
D
14
D
13
D
12
D
11
D
10
D
05
D
04
D
03
D
02
D
01
D
4
S
00
D
3
S
2
1
POL2
S
S
SS1
V
DD2
V
SS2
V
Remark This figure does not specify the TCP package.
3
Data Sheet S13813EJ1V0DS00
µ PD16738
1. PIN FUNCTIONS
(1/2)
Pin Symbol
Pin Name
Description
S1 to S384
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
R,/L
Driver output
The D/A converted 64-gray scale analog voltage is output.
Display data input
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits)
by 6 dots (2 pixels).
DX0 : LSB, DX5: MSB
Shift direction control
input
These refer to the start pulse input/output pins when driver ICs are connected in
cascade. The shift directions of the shift registers are as follows.
R,/L = H : STHR input, S1 → S384, STHL output
R,/L = L : STHL input, S384 → S1, STHR output
STHR
STHL
CLK
Right shift start pulse
input/output
R,/L = H : Becomes the start pulse input pin.
R,/L = L : Becomes the start pulse output pin.
Left shift start pulse
input/output
R,/L = H : Becomes the start pulse output pin.
R,/L = L : Becomes the start pulse input pin.
Shift clock input
Refers to the shift register’s shift clock input. The display data is incorporated into
the data register at the rising edge.
At the rising edge of the 64th clock after the start pulse input, the start pulse
output reaches the high level, thus becoming the start pulse of the next-level
driver.
STB
POL
Latch input
The contents of the data register are transferred to the latch circuit at the rising
edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It
is necessary to ensure input of one pulse per horizontal period.
Polarity input
POL = L : The S2n–1 output uses V0 to V4 as the reference supply. The S2n output
uses V5 to V9 as the reference supply.
POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output
uses V0 to V4 as the reference supply.
S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL
signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge.
POL2
VSEL
Data inversion
POL2 = H : Display data is inverted.
POL2 = L : Display data is not inverted
Selects driver voltage.
Driver voltage selection
VSEL = H or open : VDD2 = 8.5 V (TYP.)
VSEL = L : VDD2 = 7.5 V ± 0.5 V
•
4
Data Sheet S13813EJ1V0DS00
µ PD16738
(2/2)
Pin Symbol
V0 to V9
Pin Name
Description
γ -corrected power
Input the γ -corrected power supplies from outside by using operational amplifier.
Make sure to maintain the following relationships. During the gray scale voltage
output, be sure to keep the gray scale level power supply at a constant level.
VDD2 – 0.1 V > V0 > V1 > V2 > V3 > V4 > 0.5 VDD2
supplies
0.5 VDD2 – 0.3 V > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V
+ 0.3
VDD1
VDD2
VSS1
VSS2
Logic power supply
Driver power supply
Logic ground
3.3 V
8.5 V
V
V
− 0.6
+ 0.5
− 1.0
Grounding
Grounding
Driver ground
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order.
Reverse this sequence to shut down. (Simultaneous power application to VDD2 and V0 to V9 is
possible.)
2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of
a bypass capacitor of about 0.01 µF is also advised between the γ -corrected power supply
terminals (V
0, V1, V2, ···, V9) and VSS2.
5
Data Sheet S13813EJ1V0DS00
µ PD16738
2. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
This product incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively
gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage. The
D/A converter consists of ladder resistors and switches.
The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ -compensated voltages to V0’ to V63’
and V0” to V63” is almost equivalent. For the 2 sets of five γ -compensated power supplies, V0 to V4 and V5 to V9,
respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine-gray
scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the γ -compensated
power supplies V1 to V3 and V6 to V8.
Figure 2−1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and
VSS2, common electrode potential VCOM, and γ -corrected voltages V0 to V9 and the input data. Be sure to maintain
the voltage relationships of
VDD2 – 0.1 V > V0 > V1 > V2 > V3 > V4 > 0.5 VDD2
0.5 VDD2 – 0.3 V > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V
Figures 2−2 and 2−3 show the relationship between the input data and the output data and the resistance values
of the resistor strings.
This driver IC is designed for only single-sided mounting. Therefore, please do not use it for γ -corrected power
supply level inversion in double-sided mounting.
Figure 2−1. Relationship Between Input Data and γ - corrected Power Supply
VDD2
Split interval
0.1 V
V0
16
V
1
16
V
2
3
16
15
V
V4
0.5 VDD2
0.3 V
V5
15
16
16
V
6
V
7
8
V
16
V9
0.1 V
V
SS2
00
10
20
30
3F
Input Data (HEX)
6
Data Sheet S13813EJ1V0DS00
µ PD16738
Figure 2−2. Relationship between Input Data and Output Voltage (1/2)
VDD2 – 0.1 V > V0 > V1 > V2 > V3 > V4 > 0.5 VDD2
Output Voltage
( Ω )
500
500
500
500
500
500
500
500
500
500
500
500
450
450
400
370
330
330
330
320
300
280
270
260
250
240
230
220
210
200
190
180
175
175
170
170
165
165
165
165
170
170
170
175
175
175
180
200
210
220
230
240
250
260
270
290
300
310
320
340
340
340
340
Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
DX5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DX2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DX1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DX0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
r n
r0
V0'
V1'
V2'
V3'
V4'
V5'
V6'
V7'
V8'
V9'
V0
V0’
V1’
V2’
V3’
V0
V1+(V0-V1) ×
V1+(V0-V1) ×
V1+(V0-V1) ×
V1+(V0-V1) ×
V1+(V0-V1) ×
V1+(V0-V1) ×
V1+(V0-V1) ×
V1+(V0-V1) ×
V1+(V0-V1) ×
7170
6670
6170
5670
5170
4670
4170
3670
3170
2670
2170
1670
1220
770
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
7670
7670
7670
7670
7670
7670
7670
7670
7670
7670
7670
7670
7670
7670
7670
r1
r0
r1
r2
r3
r2
r3
r4
r5
r6
r7
r8
r9
V10' V1+(V0-V1) ×
V11' V1+(V0-V1) ×
V12' V1+(V0-V1) ×
V13' V1+(V0-V1) ×
V14' V1+(V0-V1) ×
V15' V1+(V0-V1) ×
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r32
r33
r34
r35
r36
r37
r38
r39
r40
r41
r42
r43
r44
r45
r46
r47
r48
r49
r50
r51
r52
r53
r54
r55
r56
r57
r58
r59
r60
r61
r62
r14
r15
r16
r17
V15’
V16’
V17’
370
V1
V16' V1
V17'
V2+(V1-V2) ×
3810
3480
3150
2830
2530
2250
1980
1720
1470
1230
1000
780
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
4140
4140
4140
4140
4140
4140
4140
4140
4140
4140
4140
4140
4140
4140
4140
V18' V2+(V1-V2) ×
V19' V2+(V1-V2) ×
V20'
V2+(V1-V2) ×
V21' V2+(V1-V2) ×
V22' V2+(V1-V2) ×
V23' V2+(V1-V2) ×
V24' V2+(V1-V2) ×
V25' V2+(V1-V2) ×
V26' V2+(V1-V2) ×
V27' V2+(V1-V2) ×
V28' V2+(V1-V2) ×
V29' V2+(V1-V2) ×
V30' V2+(V1-V2) ×
570
370
180
V31'
V2+(V1-V2) ×
V32' V2
V33'
V3+(V2-V3) ×
2590
2415
2245
2075
1910
1745
1580
1415
1245
1075
905
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
2765
2765
2765
2765
2765
2765
2765
2765
2765
2765
2765
2765
2765
2765
2765
V34' V3+(V2-V3) ×
r46
r47
r48
r49
V35'
V3+(V2-V3) ×
V47’
V48’
V49’
V36' V3+(V2-V3) ×
V37'
V3+(V2-V3) ×
V3
V38' V3+(V2-V3) ×
V39' V3+(V2-V3) ×
V40'
V3+(V2-V3) ×
V41' V3+(V2-V3) ×
V42' V3+(V2-V3) ×
V43' V3+(V2-V3) ×
V44' V3+(V2-V3) ×
V45' V3+(V2-V3) ×
730
555
V46'
V3+(V2-V3) ×
380
V47' V3+(V2-V3) ×
V48' V3
200
r60
r61
r62
V61’
V62’
V63’
V49' V5+(V3-V4) ×
V50' V5+(V3-V4) ×
4050
3830
3600
3360
3110
2850
2580
2290
1990
1680
1360
1020
680
/
/
/
/
/
/
/
/
/
/
/
/
/
/
4260
4260
4260
4260
4260
4260
4260
4260
4260
4260
4260
4260
4260
4260
V51'
V5+(V3-V4) ×
V52' V5+(V3-V4) ×
V53' V5+(V3-V4) ×
V54' V5+(V3-V4) ×
V55' V5+(V3-V4) ×
V56' V5+(V3-V4) ×
V4
V57'
V5+(V3-V4) ×
V58' V5+(V3-V4) ×
V59' V5+(V3-V4) ×
V60'
V5+(V3-V4) ×
V61' V5+(V3-V4) ×
V62' V5+(V3-V4) ×
V63' V4
340
r total 18835
Caution Between V4 and V5 terminal is not connected in the chip.
7
Data Sheet S13813EJ1V0DS00
µ PD16738
Figure 2−3. Relationship between Input Data and Output Voltage (2/2)
0.5 VDD2 – 0.3 V > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V
Output voltage
500
( Ω )
500
500
500
500
500
500
500
500
500
500
500
500
450
450
400
370
330
330
330
320
300
280
270
260
250
240
230
220
210
200
190
180
175
175
170
170
165
165
165
165
170
170
170
175
175
175
180
200
210
220
230
240
250
260
270
290
300
310
320
340
340
340
340
Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
DX5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DX2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DX1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DX0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
r n
r0
V0"
V9
/
7670
r1
V1"
V9+(V8-V9) ×
V9+(V8-V9) ×
V9+(V8-V9) ×
V9+(V8-V9) ×
V9+(V8-V9) ×
V9+(V8-V9) ×
V9+(V8-V9) ×
V9+(V8-V9) ×
V9+(V8-V9) ×
V9+(V8-V9) ×
V9+(V8-V9) ×
V9+(V8-V9) ×
V9+(V8-V9) ×
V9+(V8-V9) ×
V9+(V8-V9) ×
V8
V
5
V
V
V
V
63’’
62’’
61’’
60’’
r
r
r
r
62
61
60
59
1000 / 7670
1500 / 7670
2000 / 7670
2500 / 7670
3000 / 7670
3500 / 7670
4000 / 7670
4500 / 7670
5000 / 7670
5500 / 7670
6000 / 7670
6450 / 7670
6900 / 7670
r2
V2"
r3
V3"
r4
V4"
r5
V5"
r6
V6"
r7
V7"
r8
V8"
r9
V9"
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r32
r33
r34
r35
r36
r37
r38
r39
r40
r41
r42
r43
r44
r45
r46
r47
r48
r49
r50
r51
r52
r53
r54
r55
r56
r57
r58
r59
r60
r61
r62
V10"
V11"
V12"
V13"
V14"
V15"
V16"
V17"
V18"
V19"
V20"
V21"
V22"
V23"
V24"
V25"
V26"
V27"
V28"
V29"
V30"
V31"
V32"
V33"
V34"
V35"
V36"
V37"
V38"
V39"
V40"
V41"
V42"
V43"
V44"
V45"
V46"
V47"
V48"
V49"
V50"
V51"
V52"
V53"
V54"
V55"
V56"
V57"
V58"
V59"
V60"
V61"
V62"
V63"
r49
r48
r47
r46
V49’’
V48’’
V47’’
V
6
7300
7670
330
660
990
/
/
/
4140
4140
4140
V8+(V7-V8) ×
V8+(V7-V8) ×
V8+(V7-V8) ×
V8+(V7-V8) ×
V8+(V7-V8) ×
V8+(V7-V8) ×
V8+(V7-V8) ×
V8+(V7-V8) ×
V8+(V7-V8) ×
V8+(V7-V8) ×
V8+(V7-V8) ×
V8+(V7-V8) ×
V8+(V7-V8) ×
V8+(V7-V8) ×
V8+(V7-V8) ×
V7
1310 / 4140
1610 / 4140
1890 / 4140
2160 / 4140
2420 / 4140
2670 / 4140
2910 / 4140
3140 / 4140
3360 / 4140
3570 / 4140
3770 / 4140
3960
4140
175
350
520
690
855
1020 / 2765
1185 / 2765
1350 / 2765
1520 / 2765
1690 / 2765
1860 / 2765
2035 / 2765
2210 / 2765
2385 / 2765
2565 / 2765
/
/
/
/
/
2765
2765
2765
2765
2765
r17
r16
r15
r14
V7+(V6-V7) ×
V7+(V6-V7) ×
V7+(V6-V7) ×
V7+(V6-V7) ×
V7+(V6-V7) ×
V7+(V6-V7) ×
V7+(V6-V7) ×
V7+(V6-V7) ×
V7+(V6-V7) ×
V7+(V6-V7) ×
V7+(V6-V7) ×
V7+(V6-V7) ×
V7+(V6-V7) ×
V7+(V6-V7) ×
V7+(V6-V7) ×
V6
V17’’
V16’’
V15’’
V
8
r2
r1
r0
V2
V1
V0
’’
’’
’’
210
430
660
900
1150 / 4260
1410 / 4260
1680 / 4260
1970 / 4260
2270 / 4260
2580 / 4260
2900 / 4260
3240 / 4260
3580 / 4260
3920 / 4260
/
/
/
/
4260
4260
4260
4260
V6+(V5-V6) ×
V6+(V5-V6) ×
V6+(V5-V6) ×
V6+(V5-V6) ×
V6+(V5-V6) ×
V6+(V5-V6) ×
V6+(V5-V6) ×
V6+(V5-V6) ×
V6+(V5-V6) ×
V6+(V5-V6) ×
V6+(V5-V6) ×
V6+(V5-V6) ×
V6+(V5-V6) ×
V6+(V5-V6) ×
V5
V
9
r total 18835
Caution Between V4 and V5 terminal is not connected in the chip.
8
Data Sheet S13813EJ1V0DS00
µ PD16738
3. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format: 6 bits × 2 RGBs (6 dots)
Input width: 36 bits (2-pixel data)
R,/L = H (Right shift)
Output
Data
S1
S2
S3
S4
xxx
xxx
S383
S384
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
R,/L = L (Left shift)
Output
Data
S1
S2
S3
S4
xxx
xxx
S383
S384
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
S
2n–1Note
S2nNote
POL
L
V0 to V4
V5 to V9
V5 to V9
V0 to V4
H
Note S2n-1 (Odd output), S2n (Even output)
4. RELATIONSHIP BETWEEN STB, POL, AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge.
STB
POL
S
2n-1
SelectedvoltageofV
0
toV
4
SelectedvoltageofV
5
toV
9
SelectedvoltageofV
0
toV
4
S
2n
SelectedvoltageofV
5
toV
9
SelectedvoltageofV
0
toV
4
SelectedvoltageofV
5
toV
9
Hi-Z
Hi-Z
Hi-Z
9
Data Sheet S13813EJ1V0DS00
µ PD16738
5. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 °C, VSS1 = VSS2 = 0 V)
Parameter
Logic Part Supply Voltage
Driver Part Supply Voltage
Logic Part Input Voltage
Driver Part Input Voltage
Logic Part Output Voltage
Driver Part Output Voltage
Operating Ambient Temperature
Storage Temperature
Symbol
VDD1
VDD2
VI1
Ratings
Unit
V
–0.5 to +4.0
–0.5 to +10.0
–0.5 to VDD1 + 0.5
–0.5 to VDD2 + 0.5
–0.5 to VDD1 + 0.5
–0.5 to VDD2 + 0.5
–10 to +75
V
V
VI2
V
VO1
V
VO2
V
TA
°C
°C
Tstg
–55 to +125
Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily,
the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values
exceeding which the product may be physically damaged. Be sure to use the product within the
range of the absolute maximum ratings.
Recommended Operating Range (TA = –10 to +75 °C, VSS1 = VSS2 = 0 V)
Parameter
Logic Part Supply Voltage
Driver Part Supply Voltage
Symbol
VDD1
Conditions
MIN.
2.7
TYP.
3.3
MAX.
3.6
Unit
V
VSEL = H or open
VSEL = L
7.5
8.5
9.0
V
VDD2
•
7.0
7.5
8.0
V
High-Level Input Voltage
Low-Level Input Voltage
γ -Corrected Voltage
VIH
VIL
0.7 VDD1
0
VDD1
V
0.3 VDD1
VDD2 − 0.1
0.5 VDD2− 0.3
VDD2 − 0.1
45
V
V0 to V4
V5 to V9
VO
0.5 VDD2
VSS2 + 0.1
VSS2 + 0.1
V
V
Driver Part Output Voltage
Clock Frequency
V
fCLK
MHz
10
Data Sheet S13813EJ1V0DS00
µ PD16738
+0.3
–0.6
+0.5
–1.0
Electrical Characteristics (TA = –10 to +75 °C, VDD1 = 3.3 V
VSS1 = VSS2 = 0 V)
V, VDD2 = 8.5 V
V (VSEL = H or open),
Parameter
Symbol
IIL
Condition
MIN.
TYP.
MAX.
±1.0
VDD1
0.1
Unit
µA
V
Input Leak Current
High-Level Output Voltage
Low-Level Output Voltage
γ -Corrected Supply Current
VOH
VOL
Iγ
STHR (STHL), IOH = 0 mA
STHR (STHL), IOL = 0 mA
VDD1 − 0.1
0
V
V0 to V4 =
V0 pin, V5 pin
V4 pin, V9 pin
80
160
–160
–0.17
320
µA
µA
mA
•
•
V5 to V9 = 3.0 V
–320
–80
Note
Driver Output Current
IVOH
IVOL
∆VO
VX = 7.5 V, VOUT = 7.0 V
VDD2 = 8.0 V
,
–0.1
Note
VX = 0.5 V, VOUT = 1.0 V
VDD2 = 8.0 V
,
0.1
0.23
mA
mV
Output Voltage Deviation
Input
data
V0 = 0.1 V to 1.2 V,
±20
±30
±20
±30
±20
±10
V0 = VDD2 – 1.2 V to VDD2 – 0.1 V
V0 = 1.2 V to 0.5 VDD2 – 0.3 V,
V0 = 0.5 VDD2 to VDD2 – 1.2 V
V0 = 0.1 V to 0.8 V,
±10
±20
±10
± 3
mV
mV
mV
mV
Output Swing Voltage
Difference Deviation
∆Vp–p1
∆Vp–p2
∆Vp–p3
V0 = VDD2 – 0.8 V to VDD2 – 0.1 V
V0 = 0.8 V to 1.2 V,
V0 = VDD2 – 1.2 V to VDD2 – 0.8 V
V0 = 1.2 V to 0.5 VDD2 – 0.3 V ,
V0 = 0.5 VDD2 to VDD2 –1.2 V
Output Voltage Range
VO
All Input data
0.1
VDD2 – 0.1
4.5
V
•
•
Logic Part Dynamic Current
Consumption
IDD1
VDD1, with no load
0.8
5.5
mA
Driver Part Dynamic Current
Consumption
IDD2
VDD2 = 9.0 V, with no load
12
mA
Note VX refers to the output voltage of analog output pins S1 to S384. VOUT refers to the voltage applied to analog
output pins S1 to S384.
Cautions 1. The STB cycle is defined to be 20 µs at fCLK = 45 MHz.
2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the
measured values in the dot checkerboard input pattern.
3. Refers to the current consumption per driver when cascades are connected under the
assumption of XGA single-sided mounting (8 units).
11
Data Sheet S13813EJ1V0DS00
µ PD16738
+0.3
–0.6
+0.5
–1.0
Switching Characteristics (TA = –10 to +75 °C, VDD1 = 3.3 V
VSS1 = VSS2 = 0 V)
V, VDD2 = 8.5 V
V (VSEL = H or open),
Parameter
Symbol
tPLH1
tPLH2
tPLH3
tPHL2
tPHL3
CI1
Condition
CL = 25 pF
MIN.
TYP.
MAX.
20
8
Unit
ns
Start Pulse Delay Time
Driver Output Delay Time
8
4
VDD2 = 8.5 V ± 0.5 V
µs
RL = 10 kΩ ,CL = 80 pF
5.5
4
11
8
µs
µs
5.5
4.8
11
10
µs
Input Capacitance
STHR (STHL) excluded,
TA = 25°C
pF
CI2
STHR (STHL),TA = 25°C
8.6
15
pF
+0.3
–0.6
Timing Requirement (TA = –10 to +75 °C, VDD1 = 3.3 V
V, VSS1 = VSS2 = 0 V, tr = tf = 8.0 ns)
Parameter
Clock Pulse Width
Clock Pulse High Period
Clock Pulse Low Period
Data Setup Time
Symbol
PWCLK
PWCLK(H)
PWCLK(L)
tSETUP1
tHOLD1
Condition
MIN.
22
4
TYP.
MAX.
Unit
ns
ns
4
ns
0
ns
Data Hold Time
4
ns
Start Pulse Setup Time
Start Pulse Hold Time
POL2 Setup Time
POL2 Hold Time
tSETUP2
tHOLD2
tSETUP3
tHOLD3
2
ns
2
ns
0
ns
•
•
4
ns
Start Pulse Low Period
STB Pulse Width
tSPL
1
CLK
CLK
CLK
ns
PWSTB
tINV
3
Data Invalid Period
CLK-STB Time
1
tCLK-STB
tSTB-CLK
tSTB-STH
CLK ↑ → STB ↑
STB ↑ → CLK ↑
0
•
•
STB-CLK Time
10
3
ns
Time Between STB and Start
Pulse
STB ↑ → STHR(STHL) ↑
CLK
POL-STB Time
STB-POL Time
tPOL-STB
tSTB-POL
POL ↑ or ↓ → STB ↑
STB ↓ → POL ↓ or ↑
6
3
ns
CLK
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
•
12
Data Sheet S13813EJ1V0DS00
µ PD16738
6. SWITCHING CHARACTERISTICS WAVEFORM (R,/L = H)
•
Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
13
Data Sheet S13813EJ1V0DS00
µ PD16738
7. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met for soldering conditions of the µPD16738.
For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.
Type of Surface Mount Device
µ PD16738N-××× : TCP (TAB package)
Mounting Condition
Thermocompression
Mounting Method
Soldering
Condition
Heating tool 300 to 350°C, heating for 2 to 3 seconds: pressure 100g
(per solder)
ACF
Temporary bonding 70 to 100°C: pressure 3 to 8 kg/cm2 : time 3 to 5
seconds.
Real bonding 165 to 180°C: pressure 25 to 45 kg/cm2 : time 30 to 40
seconds. (When using the anisotropy conductive film SUMIZAC1003 of
Sumitomo Bakelite, Ltd.)
(Adhesive
Conductive Film)
Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF
manufacturing company. Be sure to avoid using two or more packaging methods at a time.
14
Data Sheet S13813EJ1V0DS00
µ PD16738
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
15
Data Sheet S13813EJ1V0DS00
µ PD16738
Reference Documents
NEC Semiconductor Device Reliability / Quality Control System (C10983E)
Quality Grades to NEC’s Semiconductor Devices (C11531E)
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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