UPD16750_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD16750

384-OUTPUT TFT-LCD SOURCE DRIVER

(COMPATIBLE WITH 256-GRAY SCALES)

DESCRIPTION

The µ PD16750 is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scales. Data input is

based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216

colors by output of 256 values γ -corrected by an internal D/A converter and 8-by-2 external power modules.

DD2

SS2

Because the output dynamic range is as large as V

− 0.2 V to V + 0.2 V, level inversion operation of the LCD’s

common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and

column line inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A converter

circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity.

Assuring a maximum clock frequency of 40 MHz when driving at 3.0 V, this driver is applicable to XGA-standard TFT-

LCD panels and SXGA TFT-LCD panels. This driver is applicable to SXGA TFT-LCD panels by input display signal 2

systems (Clock divide).

FEATURES

• CMOS level input

• 384 outputs

• Input of 8 bits (gradation data) by 6 dots

• Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter

DD2

SS2

• Output dynamic range: V

– 0.2 V to V

+ 0.2 V

CLK

• High-speed data transfer: f

= 40 MHz (internal data transfer speed when operating at 3.0 V)

• Apply for dot-line inversion, n-line inversion and column line inversion

• Output voltage polarity inversion function (POL)

• Display data inversion function (POL21/22)

DD1

• Logic power supply voltage (V ) : 3.3 V ± 0.3 V

DD2

• Driver power supply voltage (V ) : 9.0 V ± 0.5 V

• Low power control function (LPC)

ORDERING INFORMATION

Part Number

Package

µ PD16750N-xxx

TCP (TAB package)

Remark The TCP’s external shape is customized. To order the required shape, please contact one of our sales

representatives.

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. S13719EJ4V0DS00 (4th edition)

Date Published April 2000 NS CP (K)

The mark • shows major revised points.

1998

©

Printed in Japan

µ

PD16750

1. BLOCK DIAGRAM

STHR

R,/L

STHL

VDD1

64-bit bidirectional shift register

CLK

STB

VSS1

C1

C2

C63

C64

D00 - D07

D10 - D17

D20 - D27

D30 - D37

D40 - D47

D50 - D57

Data register

POL21

POL22

Latch

POL

V

DD2

SS2

Level shifter

V

V0

- V15

LPC

D/A converter

Voltage follower output

S1

S2

S3

S384

Remark /xxx indicates active low signal.

2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER

S1

S2

S383

S384

V0

V7

V8

8

Multi-

8-bit D/A converter

plexer

V

15

POL

2

Data Sheet S13719EJ4V0DS00

µ

PD16750

3. PIN CONFIGURATION (µPD16750N-xxx)

S³⁸⁴

S³⁸³

S³⁸²

V^SS2

V^DD2

V¹⁴

V¹²

V¹⁰

V⁸

V⁶

V⁴

V²

V⁰

R,/L

D⁵⁰

D⁵¹

D⁵²

D⁵³

D⁵⁴

D⁵⁵

D⁵⁶

D⁵⁷

D⁴⁰

D⁴¹

D⁴²

D⁴³

D⁴⁴

D⁴⁵

D⁴⁶

D⁴⁷

D³⁰

D³¹

D³²

D³³

D³⁴

D³⁵

D³⁶

D³⁷

POL21

POL22

POL

STB

STHL

V^DD1

CLK

V^SS1

LPC

STHR

D²⁰

D²¹

D²²

D²³

D²⁴

D²⁵

D²⁶

D²⁷

D¹⁰

D¹¹

D¹²

D¹³

D¹⁴

D¹⁵

D¹⁶

D¹⁷

D⁰⁰

D⁰¹

D⁰²

D⁰³

D⁰⁴

D⁰⁵

D⁰⁶

D⁰⁷

V¹

Copper Foil

Surface

V³

V⁵

V⁷

V⁹

V¹¹

V¹³

V¹⁵

V^DD2

V^SS2

S³

S²

S¹

•

Remark This figure does not specify the TCP package.

3

Data Sheet S13719EJ4V0DS00

µ

PD16750

4. PIN FUNCTIONS

Pin Symbol

S¹to S³⁸⁴

D⁰⁰to D⁰⁷

D¹⁰to D¹⁷

D²⁰to D²⁷

D³⁰to D³⁷

D⁴⁰to D⁴⁷

D⁵⁰to D⁵⁷

R,/L

Pin Name

Description

Driver output

The D/A converted 256-gray-scale analog voltage is output.

Display data input

The display data is input with a width of 48 bits, viz., the gray scale data (8 bits) by 6 dots (2

pixels).

D^X0: LSB, D^X7: MSB

Shift direction control These refer to the start pulse input/output pins when driver ICs are connected in cascade.

input

The shift directions of the shift registers are as follows.

R,/L = H : STHR input, S¹→ S³⁸⁴, STHL output

R,/L = L : STHL input, S³⁸⁴→ S¹, STHR output

STHR

STHL

CLK

Right shift start pulse R,/L = H : Becomes the start pulse input pin.

input/output R,/L = L : Becomes the start pulse output pin.

Left shift start pulse R,/L = H : Becomes the start pulse output pin.

input/output

R,/L = L : Becomes the start pulse input pin.

Shift clock input

Refers to the shift register’s shift clock input. The display data is incorporated into the data

register at the rising edge of the 64th clock after the start pulse input, the start pulse output

reaches the high level, thus becoming the start pulse of the next-level driver.

The contents of the data register are transferred to the latch circuit at the rising edge. And,

at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure

input of one pulse per horizontal period.

STB

POL

Latch input

Polarity input

POL = L : The S^2n–1output uses V⁰to V⁷as the reference supply. The S²ⁿoutput uses V⁸

to V¹⁵as the reference supply.

POL = H : The S^2n–1output uses V⁸to V¹⁵as the reference supply. The S²ⁿoutput uses V⁰

to V⁷as the reference supply.

S^2n-1indicates the odd output: and S²ⁿindicates the even output. Input of the POL signal is

allowed the setup time(t^POL-^STB) with respect to STB’s rising edge.

Data inversion can invert when display data is loaded.

POL21

POL22

Data inversion

POL21/22 = H : Data inversion loads display data after inverting it.

POL21/22 = L : Data inversion does not invert input data.

POL21: D⁰⁰to D⁰⁷, D¹⁰to D¹⁷, D²⁰to D²⁷

POL22: D³⁰to D³⁷, D⁴⁰to D⁴⁷, D⁵⁰to D⁵⁷

LPC

Low power control

input

The output buffer constant current source is blocked, reducing current consumption. In lower

power mode (LPC = L: DC-level input possible), the ordinary static current consumption can

be reduced by approx. 33 %.

V⁰to V¹⁵

γ -corrected power

Input the γ -corrected power supplies from outside by using operational amplifier. Make sure

to maintain the following relationships. During the gray scale voltage output, be sure to keep

the gray scale level power supply at a constant level.

supplies

V^DD2− 0.2 V > V⁰> V¹> V²> V³> V⁴> V⁵> V⁶> V⁷> 0.5 V^DD2

0.5 V^DD2− 0.3 V > V⁸> V⁹> V¹⁰> V¹¹> V¹²> V¹³> V¹⁴> V¹⁵> V^SS2+ 0.2 V

V^DD1

V^DD2

V^SS1

V^SS2

Logic power supply 3.3 V ± 0.3 V

Driver power supply 9.0 V ± 0.5 V

Logic ground

Driver ground

Grounding

4

Data Sheet S13719EJ4V0DS00

µ

PD16750

Cautions 1. The power start sequence must be V^DD1, logic input, and V^DD2& V⁰to V¹⁵in that order.

Reverse this sequence to shut down (Simultaneous power application to V^DD2and V⁰to V¹⁵is

possible.).

2. To stabilize the supply voltage, please be sure to insert a 0.1-µF bypass capacitor between

V^DD1-V^SS1and V^DD2-V^SS2. Furthermore, for increased precision of the D/A converter, insertion

of a bypass capacitor of about 0.01 µF is also advised between the γ -corrected power supply

terminals (V⁰, V¹, V²,....., V¹⁵) and V^SS2.

5

Data Sheet S13719EJ4V0DS00

µ

PD16750

5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE

This product incorporates a 8-bit D/A converter whose odd output pins and even output pins output respectively gray

scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage. The D/A

converter consists of ladder resistors.

DD2

SS2

Figure 5−1 shows the relationship between the driving voltages such as liquid-crystal driving voltages V

and V

,

COM

0

15

common electrode potential V

voltage relationships of

, and γ -corrected voltages V to V and the input data. Be sure to maintain the

V

^DD2− 0.2 V > V

0

> V

1

> V

2

> V

3

> V

4

> V

5

> V

6

> V

7

> 0.5 V^DD2,

0.5 V^DD2− 0.3 V > V

8

> V

9

> V¹⁰> V¹¹> V¹²> V¹³> V¹⁴> V¹⁵> V^SS2+ 0.2 V

Figures 5−2 and 5−3 show the relationship between the input data and the output voltage. This driver IC is designed

for only single-sided mounting. Therefore, please do not use it for γ -corrected power supply level inversion in

double-sided mounting.

Figure 5–1. Relationship between Input Data and γ -corrected Power Supplies

V

DD2

0.2 V

V

0

32

V

1

2

32

64

V

3

64

32

V

4

5

32

Split interval

32

V

6

7

0.5 VDD2

0.3 V

V

8

9

V

10

11

32

64

V

12

64

32

V

13

14

32

V

15

0.2 V

V

SS2

00

20

40

80

C0

E0

FEFF

Input data (HEX)

6

Data Sheet S13719EJ4V0DS00

µ

PD16750

Figure 5–2. Relationship between Input Data and Output Voltage (1/4)

V^DD2– 0.2 V > V⁰> V¹> V²> V³> V⁴> V⁵> V⁶> V⁷> 0.5 V^DD2, POL21/22 = L

D^X7

D^X6

D^X5

D^X4

D^X3

D^X2

D^X1

D^X0

(Ω)

rn

Data

Output voltage

V

0

1

2

3

’

V

0

'

V⁰

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

27H

28H

29H

2AH

2BH

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

V⁰

V¹

400.0

362.5

325.0

287.5

250.0

222.5

195.0

170.0

145.0

120.0

95.0

75.0

62.5

50.0

37.5

35.0

32.5

30.0

27.5

r0

r

0

1

2

3

V +(V -V ) X

1

0

1

3465.0

3102.5

2777.5

2490.0

2240.0

2017.5

1822.5

1652.5

1507.5

1387.5

1267.5

1147.5

1052.5

957.5

862.5

787.5

712.5

637.5

575.0

512.5

450.0

400.0

350.0

300.0

262.5

225.0

187.5

150.0

112.5

75.0

/

3865

r1

V²'

V¹+(V⁰-V¹) X

r2

V³'

1

0

1

V +(V -V ) X

r3

V⁴'

V¹+(V⁰-V¹) X

r4

V⁵'

1

0

1

V +(V -V ) X

r5

V⁶'

V¹+(V⁰-V¹) X

r6

V⁷'

1

0

1

V +(V -V ) X

r7

V⁸'

V¹+(V⁰-V¹) X

r8

V⁹'

1

0

1

V +(V -V ) X

r9

V¹⁰'

V¹¹'

V¹²'

V¹³'

V¹⁴'

V¹⁵'

V¹⁶'

V¹⁷'

V¹⁸'

V¹⁹'

V²⁰'

V²¹'

V²²'

V²³'

V²⁴'

V²⁵'

V²⁶'

V²⁷'

V²⁸'

V²⁹'

V³⁰'

V³¹'

V³²'

V³³'

V³⁴'

V³⁵'

V³⁶'

V³⁷'

V³⁸'

V³⁹'

V⁴⁰'

V⁴¹'

V⁴²'

V⁴³'

V⁴⁴'

V⁴⁵'

V⁴⁶'

V⁴⁷'

V⁴⁸'

V⁴⁹'

V⁵⁰'

V⁵¹'

V⁵²'

V⁵³'

V⁵⁴'

V⁵⁵'

V⁵⁶'

V⁵⁷'

V⁵⁸'

V⁵⁹'

V⁶⁰'

V⁶¹'

V¹+(V⁰-V¹) X

r10

r11

r12

r13

r14

r15

r16

r17

r18

r19

r20

r21

r22

r23

r24

r25

r26

r27

r28

r29

r30

r31

r32

r33

r34

r35

r36

r37

r38

r39

r40

r41

r42

r43

r44

r45

r46

r47

r48

r49

r50

r51

r52

r53

r54

r55

r56

r57

r58

r59

r60

r61

r62

r63

r30

r31

r32

r33

V +(V -V ) X

1

0

1

V

31

32

33

’

V¹+(V⁰-V¹) X

V +(V -V ) X

1

0

1

V1

V¹+(V⁰-V¹) X

V +(V -V ) X

1

0

1

V¹+(V⁰-V¹) X

V +(V -V ) X

1

0

1

V¹+(V⁰-V¹) X

V +(V -V ) X

1

0

1

V¹+(V⁰-V¹) X

V +(V -V ) X

1

0

1

V¹+(V⁰-V¹) X

V +(V -V ) X

1

0

1

V¹+(V⁰-V¹) X

V +(V -V ) X

1

0

1

V¹+(V⁰-V¹) X

V +(V -V ) X

1

0

1

V¹+(V⁰-V¹) X

V +(V -V ) X

1

0

1

V¹+(V⁰-V¹) X

V +(V -V ) X

1

0

1

37.5

V¹

V +(V -V ) X

2

1

2

965.0

930.0

895.0

860.0

825.0

790.0

755.0

720.0

687.5

655.0

622.5

590.0

557.5

525.0

492.5

460.0

430.0

400.0

370.0

340.0

310.0

280.0

250.0

220.0

192.5

165.0

137.5

110.0

82.5

/

1000

r222

r223

r224

r225

V

223

224

225

’

V²+(V¹-V²) X

V +(V -V ) X

2

1

2

V

5

V²+(V¹-V²) X

V +(V -V ) X

2

1

2

V²+(V¹-V²) X

V +(V -V ) X

2

1

2

V²+(V¹-V²) X

V +(V -V ) X

2

1

2

V²+(V¹-V²) X

V +(V -V ) X

2

1

2

V²+(V¹-V²) X

V +(V -V ) X

2

1

2

r251

r252

r253

r254

V²+(V¹-V²) X

V

252

253

254

’

V +(V -V ) X

2

1

2

V²+(V¹-V²) X

V +(V -V ) X

2

1

2

V²+(V¹-V²) X

V

6

7

V +(V -V ) X

2

1

2

V²+(V¹-V²) X

V

255

’

V +(V -V ) X

2

1

2

V²+(V¹-V²) X

V +(V -V ) X

2

1

2

V²+(V¹-V²) X

V +(V -V ) X

V²+(V¹-V²) X

2

1

2

V⁶²'

V⁶³'

55.0

27.5

Caution There is no connection between V⁷and V⁸in the chip.

7

Data Sheet S13719EJ4V0DS00

µ

PD16750

Figure 5–2. Relationship between Input Data and Output Voltage (2/4)

V^DD2– 0.2 V > V⁰> V¹> V²> V³> V⁴> V⁵> V⁶> V⁷> 0.5 V^DD2, POL21/22 = L

D^X7

D^X6

D^X5

D^X4

D^X3

D^X2

D^X1

D^X0

(Ω)

Output voltage

rn

Data

40H

41H

42H

43H

44H

45H

46H

47H

48H

49H

4AH

4BH

4CH

4DH

4EH

4FH

50H

51H

52H

53H

54H

55H

56H

57H

58H

59H

5AH

5BH

5CH

5DH

5EH

5FH

60H

61H

62H

63H

64H

65H

66H

67H

68H

69H

6AH

6BH

6CH

6DH

6EH

6FH

70H

71H

72H

73H

74H

75H

76H

77H

78H

79H

7AH

7BH

7CH

7DH

7EH

7FH

V

0

1

2

3

’

V

0

V⁶⁴'

V⁶⁵'

V⁶⁶'

V⁶⁷'

V⁶⁸'

V⁶⁹'

V⁷⁰'

V⁷¹'

V⁷²'

V⁷³'

V⁷⁴'

V⁷⁵'

V⁷⁶'

V⁷⁷'

V⁷⁸'

V⁷⁹'

V⁸⁰'

V⁸¹'

V⁸²'

V⁸³'

V⁸⁴'

V⁸⁵'

V⁸⁶'

V⁸⁷'

V⁸⁸'

V⁸⁹'

V⁹⁰'

V⁹¹'

V⁹²'

V⁹³'

V⁹⁴'

V⁹⁵'

V⁹⁶'

V⁹⁷'

V⁹⁸'

V⁹⁹'

V¹⁰⁰'

V¹⁰¹'

V¹⁰²'

V¹⁰³'

V¹⁰⁴'

V¹⁰⁵'

V¹⁰⁶'

V¹⁰⁷'

V¹⁰⁸'

V¹⁰⁹'

V¹¹⁰'

V¹¹¹'

V¹¹²'

V¹¹³'

V¹¹⁴'

V¹¹⁵'

V¹¹⁶'

V¹¹⁷'

V¹¹⁸'

V¹¹⁹'

V¹²⁰'

V¹²¹'

V¹²²'

V¹²³'

V¹²⁴'

V¹²⁵'

V²

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

r64

r65

25.0

r

0

1

2

3

V³+(V²-V³) X

1575

1550

1525

1500

1475

1450

1425

1400

1375

1350

1325

1300

1275

1250

1225

1200

1175

1150

1125

1100

1075

1050

1025

1000

975

/

1600

r66

r67

r68

r69

r70

r71

r72

r73

r74

r75

r30

r31

r32

r33

r76

V

31

32

33

’

r77

r78

V1

r79

r80

r81

r82

r83

r84

r85

r86

r87

r88

r89

950

r90

925

r91

900

r92

875

r93

850

r94

825

r95

800

r96

775

r97

750

r98

r222

r223

r224

r225

725

r99

V

223

224

225

’

700

r100

r101

r102

r103

r104

r105

r106

r107

r108

r109

r110

r111

r112

r113

r114

r115

r116

r117

r118

r119

r120

r121

r122

r123

r124

r125

r126

r127

675

V

5

650

625

600

575

550

525

500

475

450

425

400

r251

r252

r253

r254

375

V

252

253

254

’

350

325

300

275

V

6

7

250

225

V

255

’

200

175

150

125

100

75

V¹²⁶'

V¹²⁷'

V³+(V²-V³) X

50

25

Caution There is no connection between V⁷and V⁸in the chip.

8

Data Sheet S13719EJ4V0DS00

µ

PD16750

Figure 5–2. Relationship between Input Data and Output Voltage (3/4)

V^DD2– 0.2 V > V⁰> V¹> V²> V³> V⁴> V⁵> V⁶> V⁷> 0.5 V^DD2, POL21/22 = L

D^X7

D^X6

D^X5

D^X4

D^X3

D^X2

D^X1

D^X0

(Ω)

rn

Data

80H

81H

82H

83H

84H

85H

86H

87H

88H

89H

8AH

8BH

8CH

8DH

8EH

8FH

90H

91H

92H

93H

94H

95H

96H

97H

98H

99H

9AH

9BH

9CH

9DH

9EH

9FH

A0H

A1H

A2H

A3H

A4H

A5H

A6H

A7H

A8H

A9H

AAH

ABH

ACH

ADH

AEH

AFH

B0H

B1H

B2H

B3H

B4H

B5H

B6H

B7H

B8H

B9H

BAH

BBH

BCH

BDH

BEH

BFH

Output voltage

V

0

1

2

3

’

V

0

V¹²⁸'

V¹²⁹'

V¹³⁰'

V¹³¹'

V¹³²'

V¹³³'

V¹³⁴'

V¹³⁵'

V¹³⁶'

V¹³⁷'

V¹³⁸'

V¹³⁹'

V¹⁴⁰'

V¹⁴¹'

V¹⁴²'

V¹⁴³'

V¹⁴⁴'

V¹⁴⁵'

V¹⁴⁶'

V¹⁴⁷'

V¹⁴⁸'

V¹⁴⁹'

V¹⁵⁰'

V¹⁵¹'

V¹⁵²'

V¹⁵³'

V¹⁵⁴'

V¹⁵⁵'

V¹⁵⁶'

V¹⁵⁷'

V¹⁵⁸'

V¹⁵⁹'

V¹⁶⁰'

V¹⁶¹'

V¹⁶²'

V¹⁶³'

V¹⁶⁴'

V¹⁶⁵'

V¹⁶⁶'

V¹⁶⁷'

V¹⁶⁸'

V¹⁶⁹'

V¹⁷⁰'

V¹⁷¹'

V¹⁷²'

V¹⁷³'

V¹⁷⁴'

V¹⁷⁵'

V¹⁷⁶'

V¹⁷⁷'

V¹⁷⁸'

V¹⁷⁹'

V¹⁸⁰'

V¹⁸¹'

V¹⁸²'

V¹⁸³'

V¹⁸⁴'

V¹⁸⁵'

V¹⁸⁶'

V¹⁸⁷'

V¹⁸⁸'

V¹⁸⁹'

V³

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

r128

r129

r130

r131

r132

r133

r134

r135

r136

r137

r138

r139

r140

r141

r142

r143

r144

r145

r146

r147

r148

r149

r150

r151

r152

r153

r154

r155

r156

r157

r158

r159

r160

r161

r162

r163

r164

r165

r166

r167

r168

r169

r170

r171

r172

r173

r174

r175

r176

r177

r178

r179

r180

r181

r182

r183

r184

r185

r186

r187

r188

r189

r190

r191

25.0

27.5

30.0

32.5

35.0

37.5

r

0

1

2

3

V⁴+(V³-V⁴) X

1875.0

1850.0

1825.0

1800.0

1775.0

1750.0

1725.0

1700.0

1675.0

1650.0

1625.0

1600.0

1575.0

1550.0

1525.0

1500.0

1475.0

1450.0

1425.0

1400.0

1375.0

1350.0

1325.0

1300.0

1272.5

1245.0

1217.5

1190.0

1162.5

1135.0

1107.5

1080.0

1050.0

1020.0

990.0

/

1900.0

r30

r31

r32

r33

V

31

32

33

’

V1

/

r222

r223

r224

r225

V

223

224

225

’

960.0

930.0

V

5

900.0

870.0

840.0

807.5

775.0

742.5

710.0

677.5

645.0

612.5

580.0

r251

r252

r253

r254

V

252

253

254

’

545.0

510.0

475.0

440.0

405.0

V

6

7

370.0

335.0

V

255

’

300.0

262.5

225.0

187.5

150.0

112.5

V¹⁹⁰'

V¹⁹¹'

V⁴+(V³-V⁴) X

75.0

37.5

Caution There is no connection between V⁷and V⁸in the chip.

9

Data Sheet S13719EJ4V0DS00

µ

PD16750

Figure 5–2. Relationship between Input Data and Output Voltage (4/4)

V^DD2– 0.2 V > V⁰> V¹> V²> V³> V⁴> V⁵> V⁶> V⁷> 0.5 V^DD2

D^X7

D^X6

D^X5

D^X4

D^X3

D^X2

D^X1

D^X0

(Ω)

Output voltage

rn

Data

C0H

C1H

C2H

C3H

C4H

C5H

C6H

C7H

C8H

C9H

CAH

CBH

CCH

CDH

CEH

CFH

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

D8H

D9H

DAH

DBH

DCH

DDH

DEH

DFH

E0H

E1H

E2H

E3H

E4H

E5H

E6H

E7H

E8H

E9H

EAH

EBH

ECH

EDH

EEH

EFH

F0H

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

F9H

FAH

FBH

FCH

FDH

FEH

FFH

V

0

1

2

3

’

V

0

V¹⁹²'

V¹⁹³'

V¹⁹⁴'

V¹⁹⁵'

V¹⁹⁶'

V¹⁹⁷'

V¹⁹⁸'

V¹⁹⁹'

V²⁰⁰'

V²⁰¹'

V²⁰²'

V²⁰³'

V²⁰⁴'

V²⁰⁵'

V²⁰⁶'

V²⁰⁷'

V²⁰⁸'

V²⁰⁹'

V²¹⁰'

V²¹¹'

V²¹²'

V²¹³'

V²¹⁴'

V²¹⁵'

V²¹⁶'

V²¹⁷'

V²¹⁸'

V²¹⁹'

V²²⁰'

V²²¹'

V²²²'

V²²³'

V²²⁴'

V²²⁵'

V²²⁶'

V²²⁷'

V²²⁸'

V²²⁹'

V²³⁰'

V²³¹'

V²³²'

V²³³'

V²³⁴'

V²³⁵'

V²³⁶'

V²³⁷'

V²³⁸'

V²³⁹'

V²⁴⁰'

V²⁴¹'

V²⁴²'

V²⁴³'

V²⁴⁴'

V²⁴⁵'

V²⁴⁶'

V²⁴⁷'

V²⁴⁸'

V²⁴⁹'

V²⁵⁰'

V²⁵¹'

V²⁵²'

V²⁵³'

V⁴

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

r192

r193

r194

r195

r196

r197

r198

r199

r200

r201

r202

r203

r204

r205

r206

r207

r208

r209

r210

r211

r212

r213

r214

r215

r216

r217

r218

r219

r220

r221

r222

r223

r224

r225

r226

r227

r228

r229

r230

r231

r232

r233

r234

r235

r236

r237

r238

r239

r240

r241

r242

r243

r244

r245

r246

r247

r248

r249

r250

r251

r252

r253

r254

TOTAL

42.5

r

0

1

2

3

V⁵+(V⁴-V⁵) X

V⁵

1557.5

1515.0

1472.5

1430.0

1387.5

1345.0

1302.5

1260.0

1212.5

1165.0

1117.5

1070.0

1022.5

975.0

927.5

880.0

827.5

775.0

722.5

670.0

617.5

565.0

512.5

460.0

402.5

345.0

287.5

230.0

172.5

115.0

57.5

/

1600.0

42.5

47.5

r30

r31

r32

r33

47.5

V

31

32

33

’

47.5

V1

47.5

52.5

57.5

V⁶+(V⁵-V⁶) X

4630.0

4560.0

4490.0

4420.0

4337.5

4255.0

4172.5

4077.5

3982.5

3887.5

3775.0

3662.5

3550.0

3420.0

3290.0

3142.5

2995.0

2830.0

2665.0

2482.5

2300.0

2100.0

1900.0

1675.0

1450.0

1200.0

950.0

/

4687.5

70.0

r222

r223

r224

r225

70.0

V

223

224

225

’

82.5

V

5

82.5

95.0

112.5

130.0

147.5

165.0

182.5

200.0

225.0

250.0

300.0

350.0

15002.5

r251

r252

r253

r254

V

252

253

254

’

V

6

7

V

255

’

650.0

350.0

V²⁵⁴'

V²⁵⁵'

V⁶

V⁷

Caution There is no connection between V⁷and V⁸in the chip.

10

Data Sheet S13719EJ4V0DS00

µ

PD16750

Figure 5–3. Relationship between Input Data and Output Voltage (1/4)

0.5 V^DD2– 0.3 V > V⁸> V⁹> V¹⁰> V¹¹> V¹²> V¹³> V¹⁴> V¹⁵> V^SS2+ 0.2 V, POL21/22 = L

D_X7

D_X6

D_X5

D_X4

D_X3

D_X2

D_X1

D_X0

(Ω)

Output voltage

rn

Data

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

27H

28H

29H

2AH

2BH

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

V

8

9

V

255’’

V₀"

V₁"

V₂"

V₃"

V₄"

V₅"

V₆"

V₇"

V₈"

V₉"

V₁₅

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

400.0

362.5

325.0

287.5

250.0

222.5

195.0

170.0

145.0

120.0

95.0

75.0

62.5

50.0

37.5

35.0

32.5

30.0

27.5

r0

r

254

V₁₅+(V₁₄-V₁₅) X

V₁₄

400.0

762.5

/

3865

r1

r2

V

254’’

253’’

1087.5

1375.0

1625.0

1847.5

2042.5

2212.5

2357.5

2477.5

2597.5

2717.5

2812.5

2907.5

3002.5

3077.5

3152.5

3227.5

3290.0

3352.5

3415.0

3465.0

3515.0

3565.0

3602.5

3640.0

3677.5

3715.0

3752.5

3790.0

3827.5

r3

r

253

252

r4

r5

r6

V

252’’

251’’

r7

r

251

250

r8

V

r9

V₁₀

V₁₁

V₁₂

V₁₃

V₁₄

V₁₅

V₁₆

V₁₇

V₁₈

V₁₉

V₂₀

V₂₁

V₂₂

V₂₃

V₂₄

V₂₅

V₂₆

V₂₇

V₂₈

V₂₉

V₃₀

V₃₁

V₃₂

V₃₃

V₃₄

V₃₅

V₃₆

V₃₇

V₃₈

V₃₉

V₄₀

V₄₁

V₄₂

V₄₃

V₄₄

V₄₅

V₄₆

V₄₇

V₄₈

V₄₉

V₅₀

V₅₁

V₅₂

V₅₃

V₅₄

V₅₅

V₅₆

V₅₇

V₅₈

V₅₉

V₆₀

V₆₁

"

r10

r11

r12

r13

r14

r15

r16

r17

r18

r19

r20

r21

r22

r23

r24

r25

r26

r27

r28

r29

r30

r31

r32

r33

r34

r35

r36

r37

r38

r39

r40

r41

r42

r43

r44

r45

r46

r47

r48

r49

r50

r51

r52

r53

r54

r55

r56

r57

r58

r59

r60

r61

r62

r63

"

r225

V

225’’

224’’

223’’

r

224

223

V10

r

222

V₁₄+(V₁₃-V₁₄) X

35.0

70.0

/

1000

r

33

32

31

30

105.0

140.0

175.0

210.0

245.0

280.0

312.5

345.0

377.5

410.0

442.5

475.0

507.5

540.0

570.0

600.0

630.0

660.0

690.0

720.0

750.0

780.0

807.5

835.0

862.5

890.0

917.5

945.0

972.5

V

33’’

32’’

V

14

V

31’’

r

2

V

2’’

r

1

0

V

1

’’

V

0

’’

V

15

V₆₂

V₆₃

"

V₁₄+(V₁₃-V₁₄) X

Caution There is no connection between V⁷and V⁸in the chip.

11

Data Sheet S13719EJ4V0DS00

µ

PD16750

Figure 5–3. Relationship between Input Data and Output Voltage (2/4)

0.5 V^DD2– 0.3 V > V⁸> V⁹> V¹⁰> V¹¹> V¹²> V¹³> V¹⁴> V¹⁵> V^SS2+ 0.2 V, POL21/22 = L

D^X7

D^X6

D^X5

D^X4

D^X3

D^X2

D^X1

D^X0

V

8

9

V

255’’

(Ω)

Output voltage

rn

Data

40H

41H

42H

43H

44H

45H

46H

47H

48H

49H

4AH

4BH

4CH

4DH

4EH

4FH

50H

51H

52H

53H

54H

55H

56H

57H

58H

59H

5AH

5BH

5CH

5DH

5EH

5FH

60H

61H

62H

63H

64H

65H

66H

67H

68H

69H

6AH

6BH

6CH

6DH

6EH

6FH

70H

71H

72H

73H

74H

75H

76H

77H

78H

79H

7AH

7BH

7CH

7DH

7EH

7FH

V⁶⁴"

V⁶⁵"

V⁶⁶"

V⁶⁷"

V⁶⁸"

V⁶⁹"

V⁷⁰"

V⁷¹"

V⁷²"

V⁷³"

V⁷⁴"

V⁷⁵"

V⁷⁶"

V⁷⁷"

V⁷⁸"

V⁷⁹"

V⁸⁰"

V⁸¹"

V⁸²"

V⁸³"

V⁸⁴"

V⁸⁵"

V⁸⁶"

V⁸⁷"

V⁸⁸"

V⁸⁹"

V⁹⁰"

V⁹¹"

V⁹²"

V⁹³"

V⁹⁴"

V⁹⁵"

V⁹⁶"

V⁹⁷"

V⁹⁸"

V⁹⁹"

V¹⁰⁰"

V¹⁰¹"

V¹⁰²"

V¹⁰³"

V¹⁰⁴"

V¹⁰⁵"

V¹⁰⁶"

V¹⁰⁷"

V¹⁰⁸"

V¹⁰⁹"

V¹¹⁰"

V¹¹¹"

V¹¹²"

V¹¹³"

V¹¹⁴"

V¹¹⁵"

V¹¹⁶"

V¹¹⁷"

V¹¹⁸"

V¹¹⁹"

V¹²⁰"

V¹²¹"

V¹²²"

V¹²³"

V¹²⁴"

V¹²⁵"

V¹³

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

r64

r65

25.0

r

254

V¹³+(V¹²-V¹³) X

25

50

/

1600

r66

V

254’’

253’’

75

r67

r

253

252

100

r68

125

r69

150

r70

V

252’’

251’’

175

r71

r

251

250

V

200

r72

225

r73

250

r74

275

r75

300

r76

325

r77

r225

350

r78

V

225’’

224’’

223’’

375

r79

r

224

223

400

r80

V10

425

r81

450

r82

r

222

475

r83

500

r84

525

r85

550

r86

575

r87

600

r88

625

r89

650

r90

675

r91

700

r92

725

r93

750

r94

775

r95

800

r96

825

/

r97

850

r98

r

33

32

31

30

875

r99

V

33’’

32’’

900

r100

r101

r102

r103

r104

r105

r106

r107

r108

r109

r110

r111

r112

r113

r114

r115

r116

r117

r118

r119

r120

r121

r122

r123

r124

r125

r126

r127

V

925

V

14

950

V

31’’

975

1000

1025

1050

1075

1100

1125

1150

1175

1200

1225

1250

1275

1300

1325

1350

1375

1400

1425

1450

1475

1500

1525

1550

1575

r

2

V

2’’

r

1

0

V

1

’’

V

0

’’

V

15

V¹²⁶"

V¹²⁷"

V¹³+(V¹²-V¹³) X

Caution There is no connection between V⁷and V⁸in the chip.

12

Data Sheet S13719EJ4V0DS00

µ

PD16750

Figure 5–3. Relationship between Input Data and Output Voltage (3/4)

0.5 V^DD2– 0.3 V > V⁸> V⁹> V¹⁰> V¹¹> V¹²> V¹³> V¹⁴> V¹⁵> V^SS2+ 0.2 V, POL21/22 = L

D^X7

D^X6

D^X5

D^X4

D^X3

D^X2

D^X1

D^X0

(Ω)

Output voltage

rn

Data

80H

81H

82H

83H

84H

85H

86H

87H

88H

89H

8AH

8BH

8CH

8DH

8EH

8FH

90H

91H

92H

93H

94H

95H

96H

97H

98H

99H

9AH

9BH

9CH

9DH

9EH

9FH

A0H

A1H

A2H

A3H

A4H

A5H

A6H

A7H

A8H

A9H

AAH

ABH

ACH

ADH

AEH

AFH

B0H

B1H

B2H

B3H

B4H

B5H

B6H

B7H

B8H

B9H

BAH

BBH

BCH

BDH

BEH

BFH

V

8

9

V

255’’

V¹²⁸"

V¹²⁹"

V¹³⁰"

V¹³¹"

V¹³²"

V¹³³"

V¹³⁴"

V¹³⁵"

V¹³⁶"

V¹³⁷"

V¹³⁸"

V¹³⁹"

V¹⁴⁰"

V¹⁴¹"

V¹⁴²"

V¹⁴³"

V¹⁴⁴"

V¹⁴⁵"

V¹⁴⁶"

V¹⁴⁷"

V¹⁴⁸"

V¹⁴⁹"

V¹⁵⁰"

V¹⁵¹"

V¹⁵²"

V¹⁵³"

V¹⁵⁴"

V¹⁵⁵"

V¹⁵⁶"

V¹⁵⁷"

V¹⁵⁸"

V¹⁵⁹"

V¹⁶⁰"

V¹⁶¹"

V¹⁶²"

V¹⁶³"

V¹⁶⁴"

V¹⁶⁵"

V¹⁶⁶"

V¹⁶⁷"

V¹⁶⁸"

V¹⁶⁹"

V¹⁷⁰"

V¹⁷¹"

V¹⁷²"

V¹⁷³"

V¹⁷⁴"

V¹⁷⁵"

V¹⁷⁶"

V¹⁷⁷"

V¹⁷⁸"

V¹⁷⁹"

V¹⁸⁰"

V¹⁸¹"

V¹⁸²"

V¹⁸³"

V¹⁸⁴"

V¹⁸⁵"

V¹⁸⁶"

V¹⁸⁷"

V¹⁸⁸"

V¹⁸⁹"

V¹²

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

r128

r129

r130

r131

r132

r133

r134

r135

r136

r137

r138

r139

r140

r141

r142

r143

r144

r145

r146

r147

r148

r149

r150

r151

r152

r153

r154

r155

r156

r157

r158

r159

r160

r161

r162

r163

r164

r165

r166

r167

r168

r169

r170

r171

r172

r173

r174

r175

r176

r177

r178

r179

r180

r181

r182

r183

r184

r185

r186

r187

r188

r189

r190

r191

25.0

27.5

30.0

32.5

35.0

37.5

r

254

V¹²+(V¹¹-V¹²) X

25.0

50.0

/

1900.0

V

254’’

253’’

75.0

r

253

252

100.0

125.0

150.0

175.0

200.0

225.0

250.0

275.0

300.0

325.0

350.0

375.0

400.0

425.0

450.0

475.0

500.0

525.0

550.0

575.0

600.0

627.5

655.0

682.5

710.0

737.5

765.0

792.5

820.0

850.0

880.0

910.0

940.0

970.0

1000.0

1030.0

1060.0

1092.5

1125.0

1157.5

1190.0

1222.5

1255.0

1287.5

1320.0

1355.0

1390.0

1425.0

1460.0

1495.0

1530.0

1565.0

1600.0

1637.5

1675.0

1712.5

1750.0

1787.5

1825.0

1862.5

V

252’’

251’’

r

251

250

V

r225

V

225’’

224’’

223’’

r

224

223

V10

r

222

/

r

33

32

31

30

V

33’’

32’’

V

V14

V

31’’

r

2

V

2’’

r

1

0

V

1

’’

V

0

’’

V15

V¹⁹⁰"

V¹⁹¹"

V¹²+(V¹¹-V¹²) X

Caution There is no connection between V⁷and V⁸in the chip.

13

Data Sheet S13719EJ4V0DS00

µ

PD16750

Figure 5–3. Relationship between Input Data and Output Voltage (4/4)

0.5 V^DD2– 0.3 V > V⁸> V⁹> V¹⁰> V¹¹> V¹²> V¹³> V¹⁴> V¹⁵> V^SS2+ 0.2 V, POL21/22 = L

D^X7

D^X6

D^X5

D^X4

D^X3

D^X2

D^X1

D^X0

(Ω)

Output voltage

rn

V

8

9

Data

C0H

C1H

C2H

C3H

C4H

C5H

C6H

C7H

C8H

C9H

CAH

CBH

CCH

CDH

CEH

CFH

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

D8H

D9H

DAH

DBH

DCH

DDH

DEH

DFH

E0H

E1H

E2H

E3H

E4H

E5H

E6H

E7H

E8H

E9H

EAH

EBH

ECH

EDH

EEH

EFH

F0H

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

F9H

FAH

FBH

FCH

FDH

FEH

FFH

V

255’’

V¹⁹²"

V¹⁹³"

V¹⁹⁴"

V¹⁹⁵"

V¹⁹⁶"

V¹⁹⁷"

V¹⁹⁸"

V¹⁹⁹"

V²⁰⁰"

V²⁰¹"

V²⁰²"

V²⁰³"

V²⁰⁴"

V²⁰⁵"

V²⁰⁶"

V²⁰⁷"

V²⁰⁸"

V²⁰⁹"

V²¹⁰"

V²¹¹"

V²¹²"

V²¹³"

V²¹⁴"

V²¹⁵"

V²¹⁶"

V²¹⁷"

V²¹⁸"

V²¹⁹"

V²²⁰"

V²²¹"

V²²²"

V²²³"

V²²⁴"

V¹¹

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

r192

r193

r194

r195

r196

r197

r198

r199

r200

r201

r202

r203

r204

r205

r206

r207

r208

r209

r210

r211

r212

r213

r214

r215

r216

r217

r218

r219

r220

r221

r222

r223

r224

r225

r226

r227

r228

r229

r230

r231

r232

r233

r234

r235

r236

r237

r238

r239

r240

r241

r242

r243

r244

r245

r246

r247

r248

r249

r250

r251

r252

r253

r254

TOTAL

42.5

r

254

V¹¹+(V¹⁰-V¹¹) X

V¹⁰

42.5

85.0

/

1600.0

42.5

V

254’’

253’’

127.5

170.0

212.5

255.0

297.5

340.0

387.5

435.0

482.5

530.0

577.5

625.0

672.5

720.0

772.5

825.0

877.5

930.0

982.5

1035.0

1087.5

1140.0

1197.5

1255.0

1312.5

1370.0

1427.5

1485.0

1542.5

42.5

r

253

252

42.5

V

252’’

251’’

42.5

r

251

250

47.5

V

47.5

r225

47.5

V

225’’

224’’

223’’

47.5

r

224

223

52.5

V10

52.5

r

222

52.5

57.5

V²²⁵" V¹⁰+(V⁹-V¹⁰) X

V²²⁶" V¹⁰+(V⁹-V¹⁰) X

V²²⁷" V¹⁰+(V⁹-V¹⁰) X

V²²⁸" V¹⁰+(V⁹-V¹⁰) X

V²²⁹" V¹⁰+(V⁹-V¹⁰) X

V²³⁰" V¹⁰+(V⁹-V¹⁰) X

V²³¹" V¹⁰+(V⁹-V¹⁰) X

V²³²" V¹⁰+(V⁹-V¹⁰) X

V²³³" V¹⁰+(V⁹-V¹⁰) X

V²³⁴" V¹⁰+(V⁹-V¹⁰) X

V²³⁵" V¹⁰+(V⁹-V¹⁰) X

V²³⁶" V¹⁰+(V⁹-V¹⁰) X

V²³⁷" V¹⁰+(V⁹-V¹⁰) X

V²³⁸" V¹⁰+(V⁹-V¹⁰) X

V²³⁹" V¹⁰+(V⁹-V¹⁰) X

V²⁴⁰" V¹⁰+(V⁹-V¹⁰) X

V²⁴¹" V¹⁰+(V⁹-V¹⁰) X

V²⁴²" V¹⁰+(V⁹-V¹⁰) X

V²⁴³" V¹⁰+(V⁹-V¹⁰) X

V²⁴⁴" V¹⁰+(V⁹-V¹⁰) X

V²⁴⁵" V¹⁰+(V⁹-V¹⁰) X

V²⁴⁶" V¹⁰+(V⁹-V¹⁰) X

V²⁴⁷" V¹⁰+(V⁹-V¹⁰) X

V²⁴⁸" V¹⁰+(V⁹-V¹⁰) X

V²⁴⁹" V¹⁰+(V⁹-V¹⁰) X

V²⁵⁰" V¹⁰+(V⁹-V¹⁰) X

V²⁵¹" V¹⁰+(V⁹-V¹⁰) X

V²⁵²" V¹⁰+(V⁹-V¹⁰) X

V²⁵³" V¹⁰+(V⁹-V¹⁰) X

57.5

127.5

/

4687.5

70.0

r

33

32

31

30

197.5

70.0

V

33’’

32’’

267.5

82.5

350.0

82.5

V

14

432.5

82.5

V

31’’

515.0

95.0

610.0

95.0

705.0

95.0

800.0

112.5

130.0

147.5

165.0

182.5

200.0

225.0

250.0

300.0

350.0

15002.5

912.5

1025.0

1137.5

1267.5

1397.5

1545.0

1692.5

1857.5

2022.5

2205.0

2387.5

2587.5

2787.5

3012.5

3237.5

3487.5

3737.5

4037.5

4337.5

r

2

V

2’’

r

1

0

V

1

’’

V

0

’’

V

15

V²⁵⁴"

V²⁵⁵"

V⁹

V⁸

Caution There is no connection between V⁷and V⁸in the chip.

14

Data Sheet S13719EJ4V0DS00

µ

PD16750

6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN

Data format : 8 bits x 2 RGBs (6 dots)

Input width : 48 bits (2-pixel data)

(1) R,/L = H (Right shift)

Output

Data

S¹

S²

S³

S⁴

xxx

S³⁸³

S³⁸⁴

D⁰⁰to D⁰⁷

D¹⁰to D¹⁷

D²⁰to D²⁷

D³⁰to D³⁷

D⁴⁰to D⁴⁷

D⁵⁰to D⁵⁷

(2) R,/L = L (Left shift)

Output

Data

S¹

S²

S3

S4

xxx

S³⁸³

S³⁸⁴

D⁰⁰to D⁰⁷

D¹⁰to D¹⁷

D²⁰to D²⁷

D³⁰to D³⁷

D⁴⁰to D⁴⁷

D⁵⁰to D⁵⁷

Note

S^2n–1

S²ⁿ

POL

L

V⁰to V⁷

V⁸to V¹⁵

V⁰to V⁷

H

V⁸to V¹⁵

Note S^2n–1(Odd output), S²ⁿ(Even output)

7. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM

The output voltage is written to the LCD panel synchronized with the STB falling edge.

STB

POL

S2n-1

Selected voltage V

0

toV

7

Selected voltage V toV15

8

Selected voltage V

0

toV

7

S

2n

Selected voltage V

0

toV

7

Selected voltage V

8

toV15

Selected voltage V toV15

8

Hi-Z

15

Data Sheet S13719EJ4V0DS00

µ

PD16750

8. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T^A= 25°C, V^SS1= V^SS2= 0 V)

Parameter

Logic Part Supply Voltage

Driver Part Supply Voltage

Logic Part Input Voltage

Driver Part Input Voltage

Logic Part Output Voltage

Driver Part Output Voltage

Operating Ambient Temperature

Storage Temperature

Symbol

V^DD1

V^DD2

V^I1

Rating

Unit

V

–0.5 to +4.0

–0.5 to +10.0

–0.5 to V^DD1+ 0.5

–0.5 to V^DD2+ 0.5

–0.5 to V^DD1+ 0.5

–0.5 to V^DD2+ 0.5

–10 to +75

V

V^I2

V

V^O1

V

V^O2

V

T^A

°C

T^stg

–55 to +125

Caution If the absolute maximum rating of even one of the above parameters is exceeded even

momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore,

specify the values exceeding which the product may be physically damaged. Be sure to use the

product within the range of the absolute maximum ratings.

Recommended Operating Range (T^A= –10 to +75°C, V^SS1= V^SS2= 0 V)

Parameter

Logic Part Supply Voltage

Driver Part Supply Voltage

High-Level Input Voltage

Low-Level Input Voltage

γ -Corrected Voltage

Symbol

V^DD1

MIN.

3.0

TYP.

3.3

MAX.

3.6

Unit

V

V^DD2

8.5

9.0

9.5

V

V^IH

0.7 V^DD1

0

V^DD1

V

V^IL

0.3 V^DD1

V^DD2– 0.2

0.5 V^DD2– 0.3

V^DD2– 0.2

40

V

V⁰to V⁷

V⁸to V¹⁵

V^O

0.5 V^DD2

V^SS2+ 0.2

V

Driver Part Output Voltage

Clock Frequency

V

f^CLK

MHz

16

Data Sheet S13719EJ4V0DS00

µ

PD16750

Electrical Characteristics (T^A= –10 to +75°C, V^DD1= 3.3 V ± 0.3 V, V^DD2= 9.0 V ± 0.5 V, V^SS1= V^SS2= 0 V)

Parameter

Symbol

I^IL

Condition

MIN.

TYP.

MAX.

±1.0

V^DD1

0.1

Unit

µA

V

Input Leak Current

±0.1

High-Level Output Voltage

Low-Level Output Voltage

γ -Corrected Supply Current

V^OH

V^OL

I^γ

STHR (STHL), I^OH= 0 mA

STHR (STHL), I^OL= 0 mA

V^DD1– 0.1

0

V

V⁰to V⁷= V⁸to V¹⁵

= 4.0 V

V⁰pin, V⁸pin

225

450

–450

–185

238

900

µA

mV

V⁷pin, V¹⁵pin

–900

–225

–90

Note

V^X= 7.0 V, V^OUT= 6.5 V

V^X= 1.0 V, V^OUT= 1.5 V

V^O= 0.2 V to 1.2 V

Driver Output Current

I^VOH

I^VOL

∆V^O

Note

120

Output Voltage Deviation

±30

±50

±20

V^O= V^DD2– 1.2 V to V^DD2– 0.2 V

V^O= 1.2 V to 0.5 V^DD2– 0.3 V

V^O= 0.5 V^DD2to V^DD2– 1.2 V

V^O= 0.2 V to 0.8 V

±10

±20

±10

±3

mV

V

Output Swing Difference

Deviation

∆V^P–P

±40

V^O= V^DD2– 0.8 V to V^DD2– 0.2 V

V^O= 0.8 V to 1.2 V

±20

V^O= V^DD2– 1.2 V to V^DD2– 0.8 V

V^O= 1.2 V to 0.5 V^DD2– 0.3 V

V^O= 0.5 V^DD2to V^DD2– 1.2 V

V^DD2= 8.5 V, V⁰= 7.9 V, V³= 6.22 V,

V⁷= 4.0 V, V⁸= 4.0 V, V¹²= 1.78 V,

V¹²= 0.1 V, V¹, V², V⁴, V⁵, V⁶, V⁹, V¹⁰,

V¹¹, V¹³, V¹⁴: Open, T^A= 25°C,

Input data: 80 H

±10

Output Swing Average

Difference Deviation

AV^O

4.433

4.440

4.447

Output Voltage Range

Logic Part Dynamic Current

Consumption

V^O

0.2

V^DD2– 0.2

6.0

V

I^DD1

V^DD1, with no load

V^DD2, with no load

0.8

4.5

mA

Driver Part Dynamic Current

Consumption

I^DD2

11.0

mA

Note V^Xrefers to the output voltage of analog output pins S¹to S³⁸⁴.

OUT

V

1

384

refers to the voltage applied to analog output pins S to S

.

Cautions 1. The STB cycle is defined to be 20 µs at f^CLK.= 40 MHz.

2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the

measured values in the dot checkerboard input pattern.

3. Refers to the current consumption per driver when cascades are connected under the

assumption of XGA single-sided mounting (8 units).

17

Data Sheet S13719EJ4V0DS00

µ

PD16750

Switching Characteristics (T^A= –10 to +75°C, V^DD1= 3.3 V ± 0.3 V, V^DD2= 9.0 V ± 0.5 V, V^SS1= V^SS2= 0 V)

Parameter

Symbol

t^PLH1

t^PLH2

t^PLH3

t^PHL2

t^PHL3

C^I1

Condition

MIN.

TYP.

8

MAX.

20

6

Unit

ns

Start Pulse Delay Time

Driver Output Delay Time

C^L= 15 pF

C^L= 75 pF, R^L= 5 kΩ

3

µs

4

8

µs

3

6

µs

4

8

µs

Input Capacitance

OUTPUT

STHR (STHL) excluded, T^A= 25°C

STHR (STHL),T^A= 25°C

4.8

8.6

10

15

pF

C^I2

RL

R

L

RL

R

L

= 1 kΩ

= 15 pF

C

CL

18

Data Sheet S13719EJ4V0DS00

µ

PD16750

Timing Requirements (T^A= –10 to +75°C, V^DD1= 3.3 V ± 0.3 V, V^SS1= 0 V, t^r= t^f= 8.0 ns)

Parameter

Clock Pulse Width

Symbol

PW^CLK

PW^CLK(H)

PW^CLK(L)

t^SETUP1

t^HOLD1

Condition

MIN.

25

4

TYP.

MAX.

Unit

ns

Clock Pulse High Period

Clock Pulse Low Period

Data Setup Time

ns

4

ns

2

ns

Data Hold Time

2

ns

Start Pulse Setup Time

Start Pulse Hold Time

POL21/22 Setup Time

POL21/22 Hold Time

Start Pulse Low Period

STB Pulse Width

t^SETUP2

t^HOLD2

t^SETUP3

t^HOLD3

2

ns

2

ns

•

2

ns

2

ns

t^SPL

1

CLK

µs

PW^STB

t^INV

2

Data Invalid Period

Last Data Timing

1

CLK

ns

t^LDT

2

CLK-STB Time

t^CLK-STB

t^STB-CLK

t^STB-STH

t^POL-STB

t^STB-POL

CLK ↑ → STB ↑

6

STB-CLK Time

STB ↑ → CLK ↑

6

ns

Time Between STB and Start Pulse

POL-STB Time

STB ↑ → STHR(STHL) ↑

POL ↑ or ↓ → STB ↑

STB ↓ → POL ↓ or ↑

2

CLK

ns

–5

6

STB-POL Time

ns

Remark Unless otherwise specified, the input level is defined to be V^IH= 0.7 V^DD1, V^IL= 0.3 V^DD1.

19

Data Sheet S13719EJ4V0DS00

µ

PD16750

10. RECOMMENDED MOUNTING CONDITIONS

The following conditions must be met for mounting conditions of the µ PD16750.

For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E).

Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under

different conditions.

µ PD16750N-xxx : TCP (TAB Package)

Mounting Condition

Thermocompression

Mounting Method

Soldering

Condition

Heating tool 300 to 350°C, heating for 2 to 3 seconds : pressure 100g

(per solder)

ACF

Temporary bonding 70 to 100°C : pressure 3 to 8 kg/cm²: time 3 to 5

sec. Real bonding 165 to 180°C: pressure 25 to 45 kg/cm²: time 30 to

40 sec. (When using the anisotropy conductive film SUMIZAC1003 of

Sumitomo Bakelite,Ltd).

(Adhesive

Conductive Film)

Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF

manufacturing company. Be sure to avoid using two or more mounting methods at a time.

21

Data Sheet S13719EJ4V0DS00

µ

PD16750

[MEMO]

22

Data Sheet S13719EJ4V0DS00

µ

PD16750

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

23

Data Sheet S13719EJ4V0DS00

µ

PD16750

Reference Documents

NEC Semiconductor Device Reliability/Quality Control System(C10983E)

Quality Grades to NEC’s Semiconductor Devices(C11531E)

• The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these circuits,

software, and information in the design of the customer's equipment shall be done under the full responsibility

of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third

parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated "quality assurance program" for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

M7 98. 8


型号：	UPD16750
厂家：	NEC
描述：	384-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 256-GRAY SCALES 384输出TFT -LCD源极驱动器兼容256级灰度驱动器输出元件 CD
文件：	总24页 (文件大小：187K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD16750 [NEC]

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