UPD70F3003GC-25-7EA [ETC]
32-Bit Microcontroller ; 32位微控制器\n
| 型号： | UPD70F3003GC-25-7EA |
| 厂家： | 
ETC |
| 描述： | 32-Bit Microcontroller
|
| 文件： | 总44页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD70F3003
V853TM
32-/16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD70F3003 has a flash memory instead of the internal mask ROM of the µPD703003. This model is useful
for small-scale production of a variety of application sets or early start of production since the program can be written
and erased by the user even with the µPD70F3003 mounted on the board.
Functions in detail are described in the following user’s manuals. Be sure to read these manuals when
you design your systems.
V853 User’s Manual-Hardware
: U10913E
V850 FamilyTM User’s Manual-Architecture: U10243E
FEATURES
• Compatible with µPD703003
• Can be replaced with mask ROM model for mass production of application set
µPD70F3003 → µPD703003
• Internal flash memory: 128K bytes
Remark For differences among the products, refer to 1. DIFFERENCES AMONG PRODUCTS.
ORDERING INFORMATION
Part Number
Package
µPD70F3003GC-25-7EA
100-pin plastic QFP (fine pitch) (14 × 14 mm)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12036EJ3V1DS00 (3rd edition)
Date Published April 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
1997
©
µPD70F3003
PIN CONFIGURATION (Top View)
• 100-pin plastic QFP (fine pitch) (14 × 14 mm)
µPD70F3003GC-25-7EA
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P31/TO131
P32/TCLR13
P33/TI13
1
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
ANO0
2
3
P34/INTP130
P35/INTP131/SO3
P36/INTP132/SI3
P37/INTP133/SCK3
P63/A19
4
5
6
7
8
ANO1
P62/A18
9
AVREF2
AVREF3
P07/INTP113/ADTRG
P06/INTP112
P05/INTP111
P04/INTP110
P03/TI11
P02/TCLR11
P01/TO111
P00/TO110
P117/INTP143
P116/INTP142
P115/INTP141
P114/INTP140
P113/TI14
P112/TCLR14
P111/TO141
P61/A17
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P60/A16
V
SS
V
DD
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
Caution Directly connect VPP pin to VSS pin except the case that µPD70F3003 is used in flash
memory programming mode.
2
Data Sheet U12036EJ3V1DS00
µPD70F3003
PIN NAMES
P40-P47
: Port4
: Port5
: Port6
: Port7
: Port9
A16-A19
AD0-AD15
ADTRG
: Address Bus
P50-P57
: Address/Data Bus
: AD Trigger Input
: Analog Input
P60-P63
P70-P77
ANI0-ANI7
ANO0, ANO1
ASTB
P90-P96
: Analog Output
: Address Strobe
: Analog VDD
P110-P117
PWM0, PWM1
RESET
: Port11
: Pulse Width Modulation
: Reset
AVDD
AVREF1-AVREF3
AVSS
: Analog Reference Voltage
: Analog VSS
R/W
: Read/Write Status
: Receive Data
: Serial Clock
: Serial Input
RXD0, PXD1
SCK0-SCK3
SI0-SI3
CVDD
: Power Supply for Clock Generator
CVSS
: Ground for Clock Generator
: Clock Select
CKSEL
SO0-SO3
: Serial Output
: Timer Output
CLKOUT
DSTB
: Clock Output
TO110, TO111,
TO120, TO121,
TO130, TO131,
TO140, TO141
: Data Strobe
HLDAK
: Hold Acknowledge
: Hold Request
HLDRQ
INTP110-INTP113,
INTP120-INTP123,
INTP130-INTP133,
INTP140-INTP143
LBEN
: Interrupt Request from Peripherals
TCLR11-TCLR14 : Timer Clear
TI11-TI14
TXD0, TXD1
UBEN
WAIT
: Timer Input
: Transmit Data
: Upper Byte Enable
: Wait
: Lower Byte Enable
: Mode
MODE
X1, X2
VDD
: Crystal
NMI
: Non-maskable Interrupt Request
: Power Supply
P00-P07
P10-P17
P20-P27
P30-P37
: Port 0
: Port 1
: Port 2
: Port 3
VPP
:
Programming Power Supply
VSS
: Ground
Data Sheet U12036EJ3V1DS00
3
µPD70F3003
INTERNAL BLOCK DIAGRAM
Flash memory
CPU
ASTB
DSTB
R/W
NMI
Instruction
queue
PC
INTC
INTP110-INTP113
INTP120-INTP123
INTP130-INTP133
INTP140-INTP143
UBEN
LBEN
WAIT
A16-A19
AD0-AD15
128 K
bytes
32-bit
barrel shifter
Multiplier
16 × 16 → 32
BCU
TO110, TO111
TO120, TO121
System
register
TO130, TO131
TO140, TO141
RPU
HLDRQ
HLDAK
RAM
4 KB
General-
purpose
ALU
TCLR11-TCLR14
TI11-TI14
register
32 bits × 32
SIO
SO0/TXD0
SI0/RXD0
SCK0
UART0/CSI0
BRG0
SO1/TXD1
SI1/RXD1
SCK1
CKSEL
CLKOUT
X1
A/D
Converter
D/A
Converter
Ports
UART1/CSI1
BRG1
CG
X2
MODE
SO2
SI2
SCK2
RESET
CSI2
V
DD
SS
V
BRG2
CSI3
CVDD
CVSS
SO3
SI3
SCK3
VPP
PWM0, PWM1
PWM
4
Data Sheet U12036EJ3V1DS00
µPD70F3003
CONTENTS
1. DIFFERENCES AMONG PRODUCTS ······························································································ 6
2. PIN FUNCTIONS································································································································ 7
2.1 Port Pins ·····················································································································································
2.2 Pins Other Than Port Pins ························································································································
7
9
2.3 I/O Circuits of Pins and Recommended Connections of Unused Pins ················································ 11
3. PROGRAMMING FLASH MEMORY ································································································· 14
3.1 Selecting Communication Mode ·············································································································· 14
3.2 Flash Memory Programming Function ···································································································· 15
3.3 Connecting Dedicated Flash Programmer ······························································································ 15
4. ELECTRICAL SPECIFICATIONS ······································································································· 16
4.1 Normal Operation Mode ···························································································································· 16
4.2 Flash Memory Programming Mode·········································································································· 37
5. PACKAGE DRAWING ······················································································································· 39
6. RECOMMENDED SOLDERING CONDITIONS················································································· 40
Data Sheet U12036EJ3V1DS00
5
µPD70F3003
1. DIFFERENCES AMONG PRODUCTS
Parameter
µPD703003 µPD703003A µPD703004A µPD703025A µPD70F3003 µPD70F3003A µPD70F3025A
Internal ROM
Internal RAM
Mask ROM
128K bytes
4K bytes
Flash memory
96K bytes 256K bytes 128K bytes
256K bytes
8K bytes
8K bytes
4K bytes
Operation Normal
Single chip
mode
Provided
mode
operation
mode
ROM-less mode
Provided None
None
Provided None
Provided
Flash memory programming mode
VPP pin
None
Provided
CKC register value at reset
00H
MODE = 0: 03H
MODE = 1: 00H
00H
MODE = 0: 03H
MODE = 1: 00H
Electrical specifications
Others
Current consumption, etc. differs. (Refer to each product data sheets.)
Noise immunity and noise radiation differ because circuit scale and mask
layout differ.
6
Data Sheet U12036EJ3V1DS00
µPD70F3003
2. PIN FUNCTIONS
2.1 Port Pins
(1/2)
Shared with:
TO110
Pin Name
P00
I/O
Function
I/O
I/O
I/O
I/O
Port 0
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
P40-P47
8-bit I/O port.
TO111
Can be set in input or output mode in 1-bit units.
TCLR11
TI11
INTP110
INTP111
INTP112
INTP113/ADTRG
TO120
Port 1
8-bit I/O port.
TO121
Can be set in input or output mode in 1-bit units.
TCLR12
TI12
INTP120
INTP121/SO2
INTP122/SI2
I
NTP123/SCK2
Port 2
PWM0
8-bit I/O port.
PWM1
Can be set in input or output mode in 1-bit units.
TXD0/SO0
RXD0/SI0
SCK0
TXD1/SO1
RXD1/SI1
SCK1
Port 3
TO130
8-bit I/O port.
TO131
Can be set in input or output mode in 1-bit units.
TCLR13
TI13
INTP130
INTP131/SO3
INTP132/SI3
I
NTP133/SCK3
I/O
I/O
Port 4
AD0-AD7
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
P50-P57
Port 5
AD8-AD15
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
Data Sheet U12036EJ3V1DS00
7
µPD70F3003
(2/2)
Shared with:
A16-A19
Pin Name
P60-P63
I/O
I/O
Function
Port 6
4-bit I/O port.
Can be set in input or output mode in 1-bit units.
P70-P77
Input
I/O
Port 7
ANI0-ANI7
8-bit input port.
P90
Port 9
LBEN
P91
7-bit I/O port.
UBEN
P92
Can be set in input or output mode in 1-bit units.
R/W
P93
DSTB
P94
ASTB
P95
HLDAK
HLDRQ
TO140
TO141
TCLR14
TI14
P96
P110
P111
P112
P113
P114
P115
P116
P117
I/O
Port 11
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
INTP140
INTP141
INTP142
INTP143
8
Data Sheet U12036EJ3V1DS00
µPD70F3003
2.2 Pins Other Than Port Pins
(1/2)
Shared with:
P00
Pin Name
TO110
I/O
Function
Pulse signal output of timer 11-14
Output
TO111
TO120
TO121
TO130
TO131
TO140
TO141
TCLR11
TCLR12
TCLR13
TCLR14
TI11
P01
P10
P11
P30
P31
P110
P111
Input
Input
Input
Input
Input
Input
Output
Input
External clear signal of timer 11-14
External count clock of timer 11-14
P02
P12
P32
P112
P03
TI12
P13
TI13
P33
TI14
P113
INTP110
INTP111
INTP112
INTP113
INTP120
INTP121
INTP122
INTP123
INTP130
INTP131
INTP132
INTP133
INTP140
INTP141
INTP142
INTP143
SO0
External maskable interrupt reuest input and external capture
trigger input of timer 11
P04
P05
P06
P07/ADTRG
P14
External maskable interrupt reuest input and external capture
trigger input of timer 12
P15/SO2
P16/S12
P17/SCK2
P34
External maskable interrupt reuest input and external capture
trigger input of timer 13
P35/SO3
P36/SI3
P37/SCK3
P114
External maskable interrupt reuest input and external capture
trigger input of timer 14
P115
P116
P117
Serial transmit data output of CSI0-CSI3 (3-wire)
Serial receive data output of CSI0-CSI3 (3-wire)
P22/TXD0
P25/TXD1
P15/INTP121
P35/INTP131
P23/RXD0
P26/RXD1
P16/INTP122
P36/INTP132
SO1
SO2
SO3
SI0
SI1
SI2
SI3
Data Sheet U12036EJ3V1DS00
9
µPD70F3003
(2/2)
Pin Name
SCK0
I/O
I/O
Function
Serial clock I/O of CSI0-CSI3 (3-wire)
Shared with:
P24
SCK1
SCK2
SCK3
TXD0
P27
P17/INTP123
P37/INTP133
P22/SO0
P25/SO1
P23/SI0
P26/SI1
P20
Output
Input
Output
I/O
Serial transmit data output of UART0-UART1
Serial receive data input of UART0-UART1
Pulse signal output of PWM
TXD1
RXD0
RXD1
PWM0
PWM1
AD0-AD7
AD8-AD15
A16-A19
LBEN
UBEN
R/W
P21
16-bit multiplexed address/data bus when external memory is connected P40-P47
P50-P57
Output
Output
High-order address bus when external memory is connected
Low-order byte enable signal output of external data bus
High-order byte enable signal output of external data bus
External read/write status output
P60-P63
P90
P91
Output
P92
DSTB
ASTB
HLDAK
HLDRQ
ANI0-ANI7
ANO0, ANO1
NMI
External data strobe signal output
P93
External address strobe signal output
Bus hold acknowledge output
P94
Output
Input
Input
Output
Input
Output
Input
Input
Input
Input
Input
—
P95
Bus hold request input
P96
Analog input to A/D converter
P70-P77
Analog output of D/A converter
—
Non-maskable interrupt request input
System clock output
—
—
CLKOUT
CKSEL
WAIT
Input specifying operation mode of clock generator
Control signal input inserting wait state in bus cycle
Operation mode specification
CVDD
—
—
—
—
—
MODE
RESET
X1
System reset input
System clock resonator connection. Input external clock to X1 to
supply external clock.
X2
ADTRG
AVREF1
AVREF2
AVREF3
AVDD
Input
Input
Input
A/D converter external trigger input
Reference voltage input for A/D converter
Reference voltage input for D/A converter
P07/INTP113
—
—
—
—
—
—
—
—
—
—
Positive power supply for A/D converter
Ground potential for A/D converter
—
AVSS
—
CVDD
Positive power supply for internal clock generator
Ground potential for internal clock generator
Positive power supply
CKSEL
—
CVSS
VDD
—
VSS
Ground potential
—
VPP
High voltage application pin when program is written/verified
—
10
Data Sheet U12036EJ3V1DS00
µPD70F3003
2.3 I/O Circuits of Pins and Recommended Connections of Unused Pins
Table 2-1 shows the I/O circuit type of each pin, and the recommended connections of the unused pins. Figure
2-1 shows a partially simplified diagram of each circuit.
When connecting a pin to VDD or VSS via resistor, use of a resistor of 1 to 10 kΩ is recommended.
Table 2-1. I/O Circuit Types of Each Pin and Recommended Connections of Unused Pins (1/2)
Pin
P00/TO110, P01/TO111
P02/TCLR11, P03/TI11,
P04/INTP110-P07/INTP113/ADTRG
P10-TO120, P11/TO121
P12/TCLR12, P13/TI12
P14/INTP120
I/O Circuit Type
Recommended Connections
5
8
Input
:
Individually connect to VDD or VSS via resistor.
Output : Leave unconnected.
5
8
P15/INTP121/SO2
P16/INTP122/SI2
P17/INTP123/SCK2
P20/PWM0, P21/PWM1
P22/TXD0/SO0
5
P23/RXD0/SI0, P24/SCK0
P25/TXD1/SO1
8
5
8
5
8
P26/RXD1/SI1, P27/SCK1
P30/TO130, P31/TO131
P32/TCLR13, P33/TI13
P34/INTP130
P35/INTP131/SO3
P36/INTP132/SI3
10-A
P37/INTP133/SCK3
P40/AD0-P47/AD7
P50/AD8-P57/AD15
P60/A16-P63/A19
P70/ANI0-P77/ANI7
P90/LBEN
5
9
5
Directly connect to VSS.
Input: Individually connect to VDD or VSS via resistor.
Output: Leave unconnected.
P91/UBEN
P92/R/W
P93/DSTB
P94/ASTB
P95/HLDAK
P96/HLDRQ
P110/TO140, P111/TO141
P112/TCLR14, P113/TI14
P114/INTP140-P117/INTP143
8
Data Sheet U12036EJ3V1DS00
11
µPD70F3003
Table 2-1. I/O Circuit Types of Each Pin and Recommended Connections of Unused Pins (2/2)
Pin
I/O Circuit Type
Recommended Connections
Leave unconnected.
ANO0, ANO1
NMI
12
2
Directly connect to VSS.
Leave unconnected.
CLKOUT
WAIT
3
1
Directly connect to VDD.
MODE
2
—
—
RESET
CVDD/CKSEL
AVREF1-AVREF3, AVSS
—
—
—
Directly connect to VSS.
Directly connect to VDD.
Directly connect to VSS.
AVDD
VPP
12
Data Sheet U12036EJ3V1DS00
µPD70F3003
Figure 2-1. I/O Circuits of Pins
Type 1
Type 8
V
DD
Data
P-ch
VDD
IN/OUT
P-ch
Output
disable
N-ch
IN
N-ch
Type 2
Type 9
P-ch
Comparator
+
–
IN
N-ch
IN
V
REF (Threshold voltage)
Input enable
Schmitt trigger input with hysteresis characteristics
Type 3
Type 10-A
V
DD
Pullup
enable
P-ch
V
DD
V
DD
Data
P-ch
P-ch
OUT
IN/OUT
Open drain
Output disable
N-ch
N-ch
Type 12
Type 5
V
DD
Data
P-ch
IN/OUT
P-ch
N-ch
Analog output voltage
OUT
Output
disable
N-ch
Input
enable
Data Sheet U12036EJ3V1DS00
13
µPD70F3003
3. PROGRAMMING FLASH MEMORY
There are the following two methods for writing a program to the flash memory.
(1) On-board programming
Write a program to the flash memory using a dedicated flash programmer after the µPD70F3003 has been
mounted on the target board. Also mount a connector, etc. on the target board to communicate with the dedicated
flash programmer.
(2) Off-board programming
Write a program using a dedicated adapter before the µPD70F3003 has been mounted on the target board.
3.1 Selecting Communication Mode
To write the flash memory, use a dedicated flash programmer and serial communication. Select a serial
communication mode from those listed in Table 3-1 in the format shown in Figure 3-1. Each communication
mode is selected by the number of VPP pulses shown in Table 3-1.
Table 3-1. Communication Modes
Communication Mode
CSI
Pins Used
Number of VPP Pulses
0
SCK0 (serial clock input)
SO0 (serial data output)
SI0 (serial data input)
UART
TXD0 (serial data output)
RXD0 (serial data input)
8
Figure 3-1. Communication Mode Selecting Format
10 V
VPP
V
DD
VSS
VDD
RESET
VSS
14
Data Sheet U12036EJ3V1DS00
µPD70F3003
3.2 Flash Memory Programming Function
The flash memory is written by transferring or receiving commands and data in a selected communication
mode. The major functions of flush memory programming are listed in Table 3-2.
Table 3-2. Major Functions of Flash Memory Programming
Function
Batch erasure
Batch blank check
Data write
Description
Erases all contents of memory.
Checks erased status of entire memory.
Writes flash memory based on write start address and number of data to be
written (in bytes).
Batch verify
Compares all contents of memory with input data.
3.3 Connecting Dedicated Flash Programmer
The dedicated flash programmer and µPD70F3003 are connected differently depending on the selected
communication mode. Figures 3-2 through 3-3 show the connections in the respective communication modes.
Figure 3-2. Connection of Dedicated Flash Programmer in UART Mode
µ
Dedicated flash programmer
CLK
PD70F3003
CLK
V
PP
V
PP
DD
VDD
V
RESET
TxD
RESET
RXD0
TXD0
RxD
VSS
VSS
Figure 3-3. Connection of Dedicated Flash Programmer in CSI Mode
µ
Dedicated flash programmer
CLK
PD70F3003
CLK
V
PP
V
PP
DD
VDD
V
RESET
SCK
SO
RESET
SCK0
SI0
SI
SO0
VSS
VSS
Data Sheet U12036EJ3V1DS00
15
µPD70F3003
4. ELECTRICAL SPECIFICATIONS
4.1 Normal Operation Mode
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Supply voltage
Symbol
VDD
Condition
Ratings
Unit
V
VDD pin
–0.5 to +7.0
CVDD
CVSS
AVDD
AVSS
VI1
CVDD pin
CVSS pin
AVDD pin
AVSS pin
–0.5 to VDD + 0.3
–0.5 to +0.5
V
V
V
V
V
V
–0.5 to VDD + 0.3
–0.5 to +0.5
Input voltage
Note, VDD = 5.0 V ± 10 %
VPP pin in flash memory programming mode,
VDD = 5.0 V ± 10 %
X1 pin, VDD = 5.0 V ± 10 %
1 pin
–0.5 to VDD + 0.3
–0.5 to +11.0
VI2
Clock input voltage
Output current, low
VK
ICL
–0.5 to VDD + 1.0
4.0
V
mA
mA
mA
mA
V
Total of all pins
100
Output current, high
ICH
1 pin
–4.0
Total of all pins
–100
Output voltage
VO
VDD = 5.0 V ± 10 %
–0.5 to VDD + 0.3
–0.5 to VDD + 0.3
–0.5 to AVDD + 0.3
–0.5 to VDD + 0.3
–0.5 to AVDD + 0.3
–40 to +70
Analog input voltage
VIAN
P70/ANI0-P77/ANI7
AVDD > VDD
VDD ≥ AVDD
AVDD > VDD
VDD ≥ AVDD
V
V
Analog reference input voltage
AVREF
AVREF1-AVREF3
V
V
Operating ambient temperature
Storage temperature
TA
°C
°C
Tstg
–40 to +100
Note Except X1, P70/AN0-P77/AN7, AVREF1-AVREF3
Cautions 1. Do not directly connect the output (or I/O) pins of two or more IC products, and do not directly
connect them to VDD, VCC, or GND pin. Open-drain pins and open-collector pins may be directly
connected to one another however. Moreover, an external circuit that is designed to prevent
contention of output can be connected to pins that go into a high-impedance state.
2. Should the absolute maximum rating of even one of the above parameters be exceeded even
momentarily, the quality of the program may be degraded. The absolute maximum ratings
are, therefore, the values exceeding which the product may be physically damaged. Use the
product so that these values are never exceeded.
The normal operating ranges of ratings and conditions in which the quality of the product
is guaranteed are specified in the following DC Characteristics and AC Characteristics.
16
Data Sheet U12036EJ3V1DS00
µPD70F3003
Capacitance (TA = 25 °C, VDD = VSS = 0 V)
Parameter
Input capacitance
Symbol
CI
Condition
MIN.
TYP.
MAX.
15
Unit
pF
fc = 1 MHz
Pins other than tested pin: 0 V
I/O capacitance
CIO
15
pF
Output capacitance
CO
15
pF
Operating Conditions
Operation Mode
Direct mode
PLL mode
Internal Operating Clock Frequency (φ)
20 to 25 MHz
Operating Temperature (TA)
–40 to +70 °C
Supply Voltage (VDD)
5.0 V ± 5 %
Self oscillation frequency to 25 MHz
–40 to +70 °C
5.0 V ± 5 %
Remark The internal operating clock frequency range in the PLL mode means the range in which the functional
operation is guaranteed, and the frequency in the PLL lock status is specified by tCYX.
Data Sheet U12036EJ3V1DS00
17
µPD70F3003
Recommended Oscillation Circuit
(a) Ceramic resonator connection (TDK, Murata Mfg.: TA = –40 to +85 °C, Kyocera: TA = –20 to +80 °C)
X1
X2
R
d
C1
C2
Manufacturer
TDK Corp.
Part Number
Oscillation
Frequency
fXX (MHz)
Recommended Circuit
Constants
Oscillation
Voltage Range
Oscillation Stabilization
Time (MAX.)
C1(pF)
C2 (pF)
Provided Provided
Provided Provided
Rd (Ω)
MIN. (V) MAX. (V)
TOST (ms)
CCR5.0MC3
5.0
5.0
5.0
5.0
5.0
–
–
4.5
4.5
4.5
4.5
4.5
5.5
5.5
5.5
5.5
5.5
0.42
0.38
0.51
0.51
0.20
FCR5.0MC5
Murata Mfg.
Co. Ltd.
CSA5.00MG040
CST5.00MGW040
100
100
–
Provided Provided
Provided Provided
–
Kyocera Corp. KBR-5.0MKS
680
Cautions 1. Connect the oscillation circuit as closely to X1 and X2 pins as possible.
2. Do not route any other signal lines in the range indicated by the broken line in the above figure.
3. Thoroughly evaluate the matching between the µPD70F3003 and resonator.
(b) External clock input
X1
X2
Open
High-speed CMOS inverter
External clock
Cautions 1. Connect the high-speed CMOS inverter as closely to X1 pin as possible.
2. Thoroughly evaluate the matching between the µPD70F3003 and high-speed CMOS inverter.
18
Data Sheet U12036EJ3V1DS00
µPD70F3003
DC Characteristics (TA = –40 to +70 °C, VDD = 5.0 V ± 5 %, VSS = 0 V)
Parameter
Input voltage, high
Symbol
Condition
Except X1 and Note
Note
MIN.
2.2
TYP.
MAX.
VDD + 0.3
VDD + 0.3
+0.8
Unit
V
VIH
0.8 VDD
–0.5
V
Input voltage, low
VIL
Except X1 and Note
Note
V
–0.5
0.2 VDD
VDD + 0.5
+0.6
V
Clock input voltage, high
Clock input voltage, low
VXH
X1
0.8 VDD
–0.5
V
VXL
+
X1
V
Schmitt trigger input threshold voltage VT
VT
Note, rising
Note, falling
Note
3.0
2.0
V
–
V
–
Schmitt trigger input hysteresis width
Output voltage, high
VT+ – VT
VOH
0.5
V
IOH = –2.5 mA
IOH = –100 µA
IOC = 2.5 mA
VI = VDD
0.7 VDD
VDD – 0.5
V
V
Output voltage, low
VOL
ILIH
ILIL
0.45
10
V
Input leakage current, high
Input leakage current, low
Output leakage current, high
Output leakage current, low
Software pull-up resistor
µA
µA
µA
µA
kΩ
VI = 0 V
–10
10
ILOH
ILOL
R
VO = VDD
VO = 0 V
–10
90
P35/INTP131/SO3,
P36/INTP132/SI3,
P37/INTP133/SCK3
15
40
Supply current
Operating
IDD1
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
2.6 × φ + 7.5 2.9 × φ + 22
2.7 × φ + 9.5 3.0 × φ + 25
1.4 × φ + 7.5 1.5 × φ + 18
1.5 × φ + 9.5 1.6 × φ + 20
18.6 × φ + 100 22 × φ + 200
0.05 × φ + 4 0.1 × φ + 8
mA
mA
mA
mA
µA
In HALT mode IDD2
In IDLE mode
IDD3
mA
µA
In STOP mode IDD4
–40 °C ≤ T
A
≤ +50 °C
2
2
50
50 °C < TA ≤ 70 °C
200
µA
Note P02/TCLR11,P03/TI11,P04/INTP110-P07/INTP113,P12/TCLR12,P13/TI12,P14/INTP120,P15/INTP121/
SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1,
P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/
TCLR14, P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE
Remarks 1. TYP. value is a value for your reference at TA = 25 °C and VDD = 5.0 V. The supply current does
not include AVREF1-AVREF3 and the current running through the software pull-up resistor.
2. φ : Internal system clock frequency
Data Sheet U12036EJ3V1DS00
19
µPD70F3003
Data Retention Characteristics (TA = –40 to +70 °C)
Parameter
Data hold voltage
Symbol
VDDDR
IDDDR
Condition
STOP mode
MIN.
1.5
TYP.
MAX.
Unit
V
5.5
50
Data hold current
VDD = VDDDR –40 °C ≤ TA ≤ +50 °C
50 °C < TA ≤ 70 °C
0.2 VDDDR
0.2 VDDDR
µA
µA
µs
200
Supply voltage rise time
Supply voltage fall time
tRVD
tFVD
tHVD
200
200
0
µs
Supply voltage hold time
(vs. STOP mode setting)
ms
STOP mode release signal input time
Data hold input voltage, high
Data hold input voltage, low
tDREL
VIHDR
VILDR
0
0.9 VDDDR
0
ns
V
Note
Note
VDDDR
0.1 VDDDR
V
Note P02/TCLR11,P03/TI11,P04/INTP110-P07/INTP113,P12/TCLR12,P13/TI12,P14/INTP120,P15/INTP121/
SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/
TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/
TCLR14, P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE, X1
Remark TYP. value is a value for your reference at TA = 25 °C and VDD = 5.0 V.
STOP mode is set (at fifth clock after PSC register has been set).
VDD
V
DD
V
DD
V
DDDR
t
DREL
t
HVD
t
FVD
t
RVD
RESET (input)
V
V
IHDR
NMI (input)
(Release by falling edge)
IHDR
NMI (input)
(Release by rising edge)
V
ILDR
20
Data Sheet U12036EJ3V1DS00
µPD70F3003
AC Characteristics (TA = –40 to +70 °C, VDD = 5.0 V ± 5 %, VSS = 0 V)
AC test input wave
(a) P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/
SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/
TCLR32,P33/TI13,P34/INTP130,P35/INTP131/SO3,P36/INTP132/SI3,P37/INTP133/SCK3,P112,TCLR14,
P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE, X1
V
DD
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test point
0 V
(b) Other than (a)
2.4 V
2.2 V
0.8 V
2.2 V
0.8 V
Test point
0.4 V
AC test output test point
2.2 V
0.8 V
2.2 V
0.8 V
Test point
Load condition
DUT
(tested device)
CL
= 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration,
decrease the load capacitance of this device to less then 50 pF by using a buffer.
Data Sheet U12036EJ3V1DS00
21
µPD70F3003
(1) Clock timing
Parameter
Symbol
Condition
Direct mode
MIN.
20
200
7
MAX.
Unit
ns
X1 input cycle
<1>
tCYX
tWXH
tWXL
tXR
25
PLL mode (PLL lock status)
Direct mode
PLL mode
227
ns
X1 input width, high
X1 input width, low
X1 input rise time
X1 input fall time
<2>
<3>
<4>
<5>
—
ns
80
7
ns
Direct mode
PLL mode
ns
80
ns
Direct mode
PLL mode
7
ns
15
7
ns
tXF
Direct mode
PLL mode
ns
15
25
25
50
ns
CPU operating frequency
φ
Direct mode
PLL mode
20
Note
MHz
MHz
ns
CLKOUT output cycle
CLKOUT width, high
CLKOUT width, low
CLKOUT rise time
<6>
<7>
<8>
<9>
tCYK
tWKH
tWKL
tXR
40
0.5 T – 5
0.5 T – 5
ns
ns
5
5
ns
CLKOUT fall time
<10> tXF
ns
X1 ↓→ CLKOUT delay time
<11> tDXK
Direct mode
3
17
ns
Note Self oscillation frequency.
Remark T = tCYK
Parameter
Symbol
Condition
PLL mode
TYP.
5
Unit
Self oscillation frequency
—
φP
MHz
<1>
<2>
<3>
X1 (input)
<4>
<11>
<5>
<6>
<11>
<7>
<8>
CLKOUT (output)
<9>
<10>
22
Data Sheet U12036EJ3V1DS00
µPD70F3003
(2) Input wave
(a) P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/
SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/
TCLR32,P33/TI13,P34/INTP130,P35/INTP131/SO3,P36/INTP132/SI3,P37/INTP133/SCK3,P112/TCLR14,
P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE
Parameter
Input rise time
Input fall time
Symbol
<12> tIR2
<13> tIF2
Condition
MIN.
MAX.
20
Unit
ns
20
ns
VDD
0.8 VDD
0.8 VDD
Input signal
0.2 VDD
0.2 VDD
0 V
< 13 >
< 12 >
(b) Other than (a)
Parameter
Input rise time
Symbol
Condition
MIN.
MAX.
10
Unit
ns
<14> tIR1
<15> tIF1
Input fall time
10
ns
2.4 V
Input signal
0.4 V
2.2 V
2.2 V
0.8 V
0.8 V
< 15 >
< 14 >
Data Sheet U12036EJ3V1DS00
23
µPD70F3003
(3) Output wave (other than CLKOUT)
Parameter
Output rise time
Output fall time
Symbol
Condition
MIN.
MAX.
12
Unit
ns
<16> tOR
<17> tOF
12
ns
2.2 V
2.2 V
Output signal
0.8 V
0.8 V
< 16 >
< 17 >
(4) Reset timing
Parameter
Symbol
<18> tWRSH
<19> tWRSL
Condition
MIN.
500
MAX.
Unit
ns
RESET width, high
RESET width, low
On power appli-
cation, or on
releasing STOP
mode
500 + TOST
ns
Except on power
application, or
500
ns
except on releas-
ing STOP mode
Remark TOST: oscillation stabilization time
< 18 >
< 19 >
RESET (input)
24
Data Sheet U12036EJ3V1DS00
µPD70F3003
(5) Read timing (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT ↑→ address delay time
<20> tDKA
3
CLKOUT ↑→ R/W, UBEN, LBEN, delay time <78> tDKA2
CLKOUT ↑→ address float delay time <21> tFKA
–2
+13
15
3
CLKOUT ↓→ ASTB delay time
CLKOUT ↓→ DSTB delay time
<22> tDKST
<23> tDKD
–2
+13
+13
–2
Data input setup time (vs. CLKOUT ↑) <24> tSIDK
Data input hold time (vs. CLKOUT ↑)
WAIT setup time (vs. CLKOUT ↓) <26> tSWTK
WAIT hold time (vs. CLKOUT ↓) <27> tHKWT
Address hold time (vs. CLKOUT ↑) <28> tHKA
7
<25> tHKID
5
8
5
0
Address setup time (vs. ASTB ↓)
Address hold time (vs. ASTB ↓)
<29> tSAST
<30> tHSTA
0.5 T – 10
0.5 T – 10
DSTB ↓→ address float delay time <31> tFDA
0
Data input setup time (vs. address)
Data input setup time (vs. DSTB ↓)
ASTB ↓→ DSTB ↓ delay time
<32> tSAID
<33> tSDID
<34> tDSTD
(2 + n) T – 20
(1 + n) T – 20
0.5 T – 10
0
Data input hold time (vs. DSTB ↑) <35> tHDID
DSTB ↑→ address output delay time
DSTB ↑→ ASTB ↑ delay time
DSTB ↑→ ASTB ↓ delay time
DSTB width, low
<36> tDDA
(1 + i) T – 3
0.5 T – 10
(1.5 + i) T – 10
(1 + n) T – 10
T – 10
<37> tDDSTH
<38> tDDSTL
<39> tWDL
ASTB width, high
<40> tWSTH
<41> tSAWT1
<42> tSAWT2
<43> tHAWT1
<44> tHAWT2
<45> tSSTWT1
<46> tSSTWT2
<47> tHSTWT1
<48> tHSTWT2
WAIT setup time (vs. address)
n ≥ 1
1.5 T – 20
(1.5 + n) T – 20
WAIT hold time (vs. address)
WAIT setup time (vs. ASTB ↓)
WAIT hold time (vs. ASTB ↓)
n ≥ 1
n ≥ 1
n ≥ 1
(0.5 + n) T
(1.5 + n) T
T – 15
(1 + n) T – 15
nT
(1 + n) T
Remarks 1. T = tCYK
2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when
the programmable wait state is inserted.
3. i indicates the number of idle states (0 or 1) t be inserted in the read cycle.
4. Be sure to observe at least one of data input hold times tHKID (<25>) and tHDID (<35>).
Data Sheet U12036EJ3V1DS00
25
µPD70F3003
(5) Read Timing (2/2): 1 wait
T1
T2
TW
T3
CLKOUT (output)
< 78 >
< 20 >
< 28 >
A16-A19 (output)
Note
< 32 >
< 21 >
< 24 >
< 25 >
AD0-AD15 (I/O)
ASTB (output)
A0-A15 (output)
D0-D15 (input)
< 22 >
< 35 >
< 29 >
< 30 >
< 22 >
< 37 >
< 36 >
< 40>
< 34 > < 31 >
< 23 >
< 23 >
< 33 >
DSTB (output)
< 38 >
< 39 >
< 45 > < 26 >
< 27 >
< 26 >
< 27 >
< 47 >
< 46 >
< 48 >
WAIT (input)
< 41 >
< 43 >
< 42 >
< 44 >
Note R/W (output), UBEN (output), LBEN (output)
Remark The broken line indicates the high-impedance state.
26
Data Sheet U12036EJ3V1DS00
µPD70F3003
(6) Write timing (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT ↑→ address delay time
<20> tDKA
3
CLKOUT ↑→ R/W, UBEN, LBEN delay time <78> tDKA2
–2
+13
+13
+13
CLKOUT ↓→ ASTB delay time
CLKOUT ↑→ DSTB delay time
<22> tDKST
<23> tDKD
–2
–2
WAIT setup time (vs. CLKOUT ↓) <26> tSWTK
WAIT hold time (vs. CLKOUT ↓) <27> tHKWT
Address hold time (vs. CLKOUT ↑) <28> tHKA
8
5
0
Address setup time (vs. ASTB ↓)
Address hold time (vs. ASTB ↓)
ASTB ↓→ DSTB ↓ delay time
DSTB ↑→ ASTB ↑ delay time
DSTB width, low
<29> tSAST
<30> tHSTA
<34> tDSTD
<37> tDDSTH
<39> tWDL
0.5 T – 10
0.5 T – 10
0.5 T – 10
0.5 T – 10
(1 + n) T – 10
T – 10
ASTB width, high
<40> tWSTH
<41> tSAWT1
<42> tSAWT2
<43> tHAWT1
<44> tHAWT2
<45> tSSTWT1
<46> tSSTWT2
<47> tHSTWT1
<48> tHSTWT2
WAIT setup time (vs. address)
n ≥ 1
1.5 T – 20
(1.5 + n) T – 20
WAIT hold time (vs. address)
WAIT setup time (vs. ASTB ↓)
WAIT hold time (vs. ASTB ↓)
n ≥ 1
n ≥ 1
n ≥ 1
(0.5 + n) T
(1.5 + n) T
T – 15
(1 + n) T – 15
nT
(1 + n) T
CLKOUT ↑→ data output delay time <49> tDKOD
DSTB ↓→ data output delay time
Data output hold time (vs. CLKOUT ↑) <51> tHKOD
Data output setup time (vs. DSTB ↑)
20
10
<50> tDDOD
0
<52> tSODD
(1 + n) T – 15
T – 10
Data output hold time (vs. DSTB ↑) <53> tHDOD
Remarks 1. T = tCYK
2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when
the programmable wait state is inserted.
Data Sheet U12036EJ3V1DS00
27
µPD70F3003
(6) Write timing (2/2): 1 wait
T1
T2
TW
T3
CLKOUT (output)
< 78 >
< 20 >
< 28 >
A16-A19 (output)
Note
< 49 >
< 51 >
AD0-AD15 (I/O)
A0-A15 (output)
D0-D15 (output)
< 22 >
< 29 >
< 30 >
< 22 >
ASTB (output)
DSTB (output)
< 23 >
< 37 >
< 53 >
< 23 >
< 34 >
< 40 >
< 50 >
< 52 >
< 39 >
< 45 > < 26 >
< 47 >
< 46 >
< 48 >
< 27 >
< 26 >
< 27 >
WAIT (input)
< 41 >
< 43 >
< 42 >
< 44 >
Note R/W (output), UBEN (output), LBEN (output)
Remark The broken line indicates the high-impedance state.
28
Data Sheet U12036EJ3V1DS00
µPD70F3003
(7) Bus hold timing (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
HLDRQ setup time (vs. CLKOUT ↓) <54> tSHOK
HLDRQ hold time (vs. CLKOUT ↓) <55> tHKHQ
8
5
CLKOUT ↑→ HLDAK delay time
HLDRQ width, high
<56> tDKHA
<57> tWHQH
<58> tWHAL
T + 10
T – 10
HLDAK width, low
CLKOUT↑ → Bus float delay time <59> tDKF
HLDAK ↑→ bus output delay time <60> tDHAC
20
–3
HLDRQ ↓→ HLDAK ↓ delay time
HLDRQ ↑→ HLDAK ↑ delay time
<61> tDHQHA1
<62> tDHQHA2
(2 n + 7.5) T + 20
1.5 T + 20
0.5 T
Remarks 1. T = tCYK
2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when
the programmable wait state is inserted.
Data Sheet U12036EJ3V1DS00
29
µPD70F3003
(7) Bus hold timing (2/2)
TH
TH
TH
TH
TI
CLKOUT (output)
< 54 >
< 54 > < 55 >
< 57 >
HLDRQ (input)
< 56 >
< 56 >
< 61 >
< 62 >
HLDAK (output)
< 58 >
< 60 >
< 59 >
A16-A19 (output)
Note
D0-D15
(input or output)
AD0-AD15 (I/O)
ASTB (output)
DSTB (output)
R/W (output)
Note UBEN (output), LBEN (output)
Remark The broken line indicates the high-impedance state.
30
Data Sheet U12036EJ3V1DS00
µPD70F3003
(8) Interrupt timing
Parameter
NMI width, high
Symbol
<63> tWNIH
<64> tWNIL
<65> tWITH
Condition
MIN.
500
MAX.
Unit
ns
NMI width, low
500
ns
INTPn width, high
n = 110-113,
120-123,
130-133,
140-143
3 T + 10
ns
INTPn width, low
Remark T = tCYK
NMI (input)
<66> tWITL
n = 110-113,
120-123,
130-133,
140-143
3 T + 10
ns
< 63 >
< 64 >
< 65 >
< 66>
INTPn (input)
Remark n = 110-113, 120-123, 130-133, 140-143
Data Sheet U12036EJ3V1DS00
31
µPD70F3003
(9) CSI timing (1/2)
(a) Master mode
(i) CSI0-CSI2 timing
Parameter
Symbol
Condition
Output
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCKn cycle
<67> tCYSK1
<68> tWSKH1
<69> tWSKL1
<70> tSSISK1
<71> tHSKSI1
160
SCKn width, high
Output
Output
0.5 tCYSK1 – 20
SCKn width, low
0.5 tCYSK1 – 20
SIn setup time (vs. SCKn ↑)
SIn hold time (vs. SCKn ↑)
50
0
SOn output delay time (vs. SCKn ↓) <72> tDSKSO1
SOn output hold time (vs. SCKn ↑) <73> tHSKSO1
18
0.5 tCYSK1 – 5
Remark n = 0-2
(ii) CSI3 timing
Parameter
Symbol
Condition
MIN.
MAX.
Unit
RL = 1.5
SCK3 cycle
<67> tCYSK3
<68> tWSKH3
Output
Output
Output
500
ns
ns
kΩ
SCK3 width, high
0.5 tCYSK3 – 150
CL = 50
pF
SCK3 width, low
<69> tWSKL3
<70> tSSISK3
0.5 tCYSK3 – 70
100
ns
ns
SI3 setup time (vs. SCK3 ↑)
SI3 hold time (vs. SCK3 ↑)
<71> tHSKSI3
50
ns
ns
SO3 output delay time (vs. SCK3 ↓) <72> tDSKSO3
RL = 1.5 KΩ
150
CL = 50 pF
SO3 output hold time (vs. SCK3 ↑) <73> tHSKSO3
tWSKH3
ns
Remark RL and CL are the load resistance and load capacitance respectively of the SCK3 and SO3 output
lines.
(b) Slave mode
(i) CSI0-CSI2 timing
Parameter
Symbol
Condition
Input
MIN.
160
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCKn cycle
<67> tCYSK2
<68> tWSKH2
<69> tWSKL2
<70> tSSISK2
<71> tHSKSI2
SCKn width, high
Input
Input
SCKn width, low
50
SIn setup time (vs. SCKn ↑)
SIn hold time (vs. SCKn ↑)
10
10
SOn output delay time (vs. SCKn ↓) <72> tDSKSO2
SOn output hold time (vs. SCKn ↑) <73> tHSKSO2
45
tWSKH2
Remark n = 0-2
32
Data Sheet U12036EJ3V1DS00
µPD70F3003
(9) CSI timing (2/2)
(ii) CSI3 timing
Parameter
Symbol
Condition
Input
MIN.
500
100
180
100
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCK3 cycle
<67> tCYSK4
<68> tWSKH4
<69> tWSKL4
<70> tSSISK4
<71> tHSKSI4
SCK3 width, high
Input
Input
SCK3 width, low
SI3 setup time (vs. SCK3 ↑)
SI3 hold time (vs. SCK3 ↑)
SO3 output delay time (vs. SCK3 ↓) <72> tDSKSO4
SO3 output hold time (vs. SCK3 ↑) <73> tHSKSO4
RL = 1.5 kΩ
150
CL = 50 pF
tWSKH4
Remark RL and CL are the load resistance and load capacitance respectively of the SCK3 and SO3 output
lines.
< 67 >
< 69 >
< 68 >
SCKn (I/O)
< 70 >
< 71 >
SIn (input)
Input data
< 72 >
< 73 >
SOn (output)
Output data
Remark 1. The broken line indicates the high-impedance state.
2. n = 0-3
Data Sheet U12036EJ3V1DS00
33
µPD70F3003
(10) RPU timing
Parameter
Symbol
<74> tWTIH
<75> tWTIL
<76> tWTCH
<77> tWTCL
Condition
MIN.
MAX.
Unit
ns
TI1n width, high
TI1n width, low
3 T + 10
3 T + 10
3 T + 10
3 T + 10
ns
TCLR1n width, high
TCLR1n width, low
ns
ns
Remark T = tCYK
<74>
<75>
TI1n (input)
<76>
<77>
TCLR1n (input)
Remark n = 1-4
34
Data Sheet U12036EJ3V1DS00
µPD70F3003
A/D Converter Characteristics (TA = –40 to +70 °C, VDD = AVDD = 5 V ±5 %, VSS = VSS = 0 V)
Parameter
Resolution
Symbol
—
Conditions
MIN.
10
TYP.
MAX.
Unit
bit
Overall errorNote 1
—
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
±0.55
±0.7
±1/2
%FSR
%FSR
LSB
tCYK
—
Quantize error
—
Conversion time
tCONV
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
48
48
8
tCYK
Sampling time
tSAMP
—
tCYK
8
tCYK
Zero-scale errorNote 1
Full-scale errorNote 1
Non-linear errorNote 1
—
±3.0
±3.0
±1.5
±1.5
±1.5
±1.5
±4.5
±5.5
±2.5
±4.5
±3.5
±4.5
LSB
LSB
LSB
LSB
LSB
LSB
V
—
—
—
—
—
Analog input
voltageNote 2
VIAN
–0.3
3.5
AVDD
+0.3
Reference voltage
AVREF1 current
AVREF1
AIREF1
AIDD
AVDD
3.0
V
1.2
2.3
mA
mA
AVDD supply current
6.0
Notes 1. Except quantize error
2. The conversion result is 000H when VIAN = 0.
Converted with 10-bit resolution when 0 < VIAN < AVREF1.
The conversion result is 3FFH when AVREF1 ≤ VIAN ≤ AVDD.
Data Sheet U12036EJ3V1DS00
35
µPD70F3003
D/A Converter Characteristics (TA = –40 to + 70 °C, VDD = AVDD = 5 V ±5 %, VSS = AVSS = 0 V)
Parameter
Resolution
Symbol
—
Conditions
MIN.
TYP.
MAX.
Unit
bit
8
Overall error
—
Load conditions: 2 MΩ, 30 pF
AVREF2 = VDD
0.8
%
AVREF3 = 0
—
—
—
Load conditions: 2 MΩ, 30 pF
AVREF2 = 0.75 VDD
1.0
0.6
0.8
10
%
%
%
AVREF3 = 0.25 VDD
Load conditions: 4 MΩ, 30 pF
AVREF2 = VDD
AVREF3 = 0
Load conditions: 4 MΩ, 30 pF
AVREF2 = 0.75 VDD
AVREF3 = 0.25 VDD
Settling time
—
Load conditions: 2 MΩ, 30 pF
µs
kΩ
V
Output resistance
AVREF2 input voltage
AVREF3 input voltage
RO
10
5
AVREF2
AVREF3
RAIREF
0.75 VDD
VDD
0
2
0.25 VDD
V
AVREF2-AVREF3
DACS0, DACS1 = 55H
kΩ
resistance value
36
Data Sheet U12036EJ3V1DS00
µPD70F3003
4.2 Flash Memory Programming Mode
Basic Characteristics (TA = 10 to 40 °C (When overwritten), TA = –40 to +70 °C (When not overwritten), VDD
= 5 V ±5 %, VSS = 0 V, VPP = 10 V ± 0.3 V)
Parameter
Operating frequency
Symbol
fX
Conditions
MIN.
20
TYP.
MAX.
25
Unit
MHz
V
Supply voltage
VDD
4.75
–0.5
0.8 VDD
9.7
5.25
VPPL
VPPM
VPPH
IDO
VPP low level detection
VPP, VDD level detection
VPP high voltage detection
0.2 VDD
1.2 VDD
10.3
V
V
V
VDD supply current
VPP supply current
Number of rewrite
Write time
3.0 × φ + 25
100
mA
mA
times
µs
IPP
VPP = 10 V
CWRT
tWRT
tERASE
5
Note 1
Note 2
200
20
500
Erasure time
40
s
Notes 1. When retried 10 times with 50 µs write time.
2. When retried 20 times with 2 s erasure time.
Remark φ: Internal system clock frequency.
Data Sheet U12036EJ3V1DS00
37
µPD70F3003
Serial Write Operation Characteristics
Parameter
Symbol
Conditions
MIN.
10
TYP.
MAX.
Unit
ms
µs
VDD ↑→ RESET ↑ setup time
VPP ↑→ RESET ↑ setup time
RESET ↑→ VPP count start time
Count end time
<101>
<102>
<103>
<104>
<105>
<106>
tDRRR
tPSRR
tRRCF
tCOUNT
tCH
1.0
5T + 500
ns
10
ms
µs
VPP counter width, high
VPP counter width, low
1.0
1.0
tCL
µs
Remark
T = tCYK
V
DD
V
DD
<104>
0 V
<105>
<103>
VPPH
V
PP
V
PPM
<106>
VPPL
<102>
V
DD
RESET (input)
0 V
<101>
38
Data Sheet U12036EJ3V1DS00
µPD70F3003
5. PACKAGE DRAWING
100 PIN PLASTIC QFP (FINE PITCH) ( 14)
A
B
75
76
51
50
detail of lead end
S
C
D
R
Q
100
1
26
25
F
J
M
G
H
I
K
P
L
N
S
S
M
NOTE
1. Controlling dimension
ITEM MILLIMETERS
INCHES
millimeter.
A
B
16.0±0.2
14.0±0.2
0.630±0.008
+0.009
0.551
–0.008
2. Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
+0.009
0.551
C
14.0±0.2
–0.008
D
F
16.0±0.2
1.0
0.630±0.008
0.039
G
1.0
0.039
+0.05
0.22
H
0.009±0.002
–0.04
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
+0.009
0.039
K
L
1.0±0.2
0.5±0.2
–0.008
+0.008
0.020
–0.009
+0.03
0.17
+0.001
0.007
M
–0.07
–0.003
N
P
0.10
0.004
+0.003
0.057
1.45±0.05
–0.002
Q
R
S
0.125±0.075
5°±5°
0.005±0.003
5°±5°
1.7 MAX.
0.067 MAX.
P100GC-50-7EA-3
Data Sheet U12036EJ3V1DS00
39
µPD70F3003
6. RECOMMENDED SOLDERING CONDITIONS
Solder this product under the following recommended conditions.
For details of the recommended soldering conditions, refer to information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended, consult NEC.
Table 6-1. Soldering Conditions of Surface Mount Type
Soldering Method(s)
Infrared reflow
Soldering Conditions
Recommended
Conditions Symbol
Package peak temperature: 235 °C, Time: 30 secs. max. (210 °C min.),
Number of times: twice max., Number of days: 7Note (after that,
prebaking is necessary at 125 °C for 10 hours)
IR35-107-2
VP15-107-2
—
<Precaution>
Products other than in heat-resistance trays (such as those packaged
in a magazine, taping, or non-heat-resistance tray) cannot be baked
while they are in their package.
VPS
Package peak temperature: 215 °C, Time: 40 secs. max. (200 °C min.),
Number of times: twice max., Number of days: 7Note (after that,
prebaking is necessary at 125 °C for 10 hours)
<Precaution>
Products other than in heat-resistance trays (such as those packaged
in a magazine, taping, or non-heat-resistance tray) cannot be baked
while they are in their package.
Partial pin heating
Pin temperature: 300 °C max., Time: 3 seconds max. (per device side)
Note Number of days in storage after the dry pack has been opened. The storage conditions are at 25 °C, 65%
RH MAX.
Caution Do not use two or more soldering methods in combination. (except partial heating).
40
Data Sheet U12036EJ3V1DS00
µPD70F3003
[MEMO]
Data Sheet U12036EJ3V1DS00
41
µPD70F3003
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
42
Data Sheet U12036EJ3V1DS00
µPD70F3003
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 91-504-2787
Fax: 01908-670-290
Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
NEC Electronics (Germany) GmbH
Scandinavia Office
Tel: 02-66 75 41
Fax: 02-2719-5951
Taeby, Sweden
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Fax: 08-63 80 388
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U12036EJ3V1DS00
43
µPD70F3003
Related document : µPD703003 Data Sheet (U12261E)
µPD703003A, 703004A, 703025A Data Sheet (U13188J) (Japanese version)
µPD70F3003A, 70F3025A Data Sheet (U13189E)
V850 Family Instruction Table (U10229E)
Reference document: Concept of Electrical Characteristics - Microcomputers (IEI-601) (Japanese version)
Some of the related documents are preliminary editions but are not so specified here.
V850 Family and V853 are trademarks of NEC Corporation.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98.8
相关型号：
UPD70F3015BYGC-8EU-A
Microcontroller, 32-Bit, FLASH, 20MHz, CMOS, PQFP100, 14 X 14 MM, LEAD FREE, PLASTIC, LQFP-100
NEC
©2020 ICPDF网 联系我们和版权申明