UPD78F9136AMC-5A4 [ETC]
Microcontroller ; 微控制器\n
| 型号： | UPD78F9136AMC-5A4 |
| 厂家： | 
ETC |
| 描述： | Microcontroller
|
| 文件： | 总48页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUITS
µPD78F9136A
8-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD78F9136A is a µPD789134A Subseries product of the 78K/0S Series.
The µPD78F9136A replaces the internal masked ROM of the µPD789131A,789132A and 789134A with flash
memory, which enables the writing/erasing of a program while the device is mounted on the board.
Because the device can be programmed by the user, it is ideally suited to the evaluation stages of system
development, the manufacture of small batches of multiple products, and the rapid development of new products.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD789104A, 789114A, 789124A, 789134A Subseries User’s Manual: To be prepared
78K/0S Series User's Manual Instruction: U11047E
FEATURES
• Pin-compatible with masked ROM version (excluding VPP pin)
•
•
•
•
•
Flash memory: 16K bytes
Internal High-Speed RAM: 256 bytes
Built-in RC oscillator
On-chip multiplier: 8 bits × 8 bits = 16 bits
Minimum instruction execution time can be changed from high-speed (0.5 µs) to low-speed (2.0 µs) (@ 4.0-MHz
operation with system clock)
•
•
•
•
I/O ports: 20
Serial interface: 1 channel: Switchable between 3-wire serial I/O and UART modes
10-bit resolution A/D converter: 4 channels
Timers: 3 channels
•
•
•
16-bit timer: 1 channel
8-bit timer/event counter: 1 channel
Watchdog timer: 1 channel
•
Power supply voltage: VDD = 1.8 to 5.5 V
APPLICATIONS
Cleaners, washing machines, refrigerators and battery-charger
ORDERING INFORMATION
Part number
Package
30-pin plastic SSOP (7.62mm (300))
µ PD78F9136AMC-5A4
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14690EJ1V0DS00 (1st edition)
Date Published February 2000 NS CP(K)
Printed in Japan
2000
©
µPD78F9136A
78K/0S SERIES LINEUP
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products under mass production
Products under development
Y subseries supports SMB.
Small, general-purpose
µ
µ
µ
PD789046
PD789026 with subsystem clock added
44 pins
42/44 pins
28 pins
PD789014 with timer reinforced and ROM and RAM expanded
µ
µ
PD789026
PD789014
UART. Low-voltage (1.8-V) operation
Small, general-purpose + A/D
µ
PD789177
44 pins
44 pins
30 pins
30 pins
30 pins
30 pins
30 pins
30 pins
µ
µ
µ
µ
µ
PD789167 with improved A/D
PD789104A with improved timer
PD789146 with improved A/D
PD789104A with EEPROM added
PD789124A with improved A/D
PD789177Y
PD789167Y
µ
µ
µ
µ
µ
µ
µ
µ
µ
PD789167
PD789156
PD789146
PD789134A
PD789124A
PD789114A
PD789104A
RC oscillation model of PD789104A
µ
µ
µ
PD789104A with improved A/D
PD789026 with A/D and multiplier added
For inverter control
µ
PD789842
Internal inverter control circuit and UART
44 pins
78K/0S
series
For driving LCD
80 pins
80 pins
64 pins
64 pins
64 pins
64 pins
64 pins
64 pins
µ
µ
µ
µ
µ
µ
PD789407A with improved A/D
PD789456 with improved I/O
PD789446 with improved A/D
PD789426 with improved display output
PD789426 with improved A/D
PD789306 with A/D added
µ
µ
PD789417A
PD789407A
µ
µ
µ
µ
µ
µ
PD789456
PD789446
PD789436
PD789426
PD789316
PD789306
RC oscillation model ofµPD789306
Basic subseries for driving LCD
For driving Dot LCD
µ
µ
PD789835
Segment/common output: 96 pins
Segment: 40 pins, common: 16 pins
144 pins
88 pins
PD789830
For ASSP
µ
PD789327 with A/D added
52 pins
52 pins
44 pins
44 pins
20 pins
20 pins
µ
µ
µ
PD789467
PD789327
PD789800
For remote controller. Internal LCD controller/driver
For PC keyboard. Internal USB function
For key pad. Internal POC
µ
µ
µ
PD789840
PD789861
PD789860
µ
RC oscillation model of PD789860
For keyless entry. Internal POC and key return circuit
2
Data Sheet U14690EJ1V0DS00
µPD78F9136A
The major differences between subseries are shown below.
VDD
Timer
Function
Subseries Name
ROM
8-bit 10-bit
MIN
Serial Interface
I/O
Remark
Capacity
A/D
A/D
8-bit
1 ch
16-bit Watch WDT
Value
Small,
µPD789046 16 K
1 ch
1 ch
1 ch
−
−
1 ch (UART:1 ch) 34 pins 1.8 V
−
general-
purpose
µPD789026 4 K-16 K
µPD789014 2 K-4 K
−
2 ch
−
22 pins
Small,
µPD789177 16 K-24 K 3 ch
µPD789167
1 ch
1 ch
1 ch
−
8 ch 1 ch (UART: 1 ch) 31 pins 1.8 V
−
general-
purpose
+ A/D
8 ch
−
−
µPD789156 8 K-16 K
µPD789146
1 ch
−
4 ch
−
20 pins
Internal
EEPROM
4 ch
µ
µ
µ
µ
PD789134A 2 K-8 K
PD789124A
4 ch
−
RC oscillation
version
4 ch
−
PD789114A
4 ch
−
−
−
PD789104A
4 ch
8 ch
For
µPD789842 8 K-16 K
3 ch Note 1 ch
1 ch
1 ch
−
1 ch (UART: 1 ch) 30 pins 4.0 V
inverter
control
µ
µ
PD789417A
PD789407A
For LCD
driving
12 K-24 K 3 ch
1 ch
1 ch
7 ch 1 ch (UART: 1 ch) 43 pins 1.8 V
−
7 ch
−
−
µPD789456 12 K-16 K 2 ch
µPD789446
6 ch
−
30 pins
40 pins
6 ch
−
µPD789436
6 ch
−
µPD789426
6 ch
−
µPD789316 8 K to
2 ch (UART: 1 ch) 23 pins
RC oscillation
version
16K
µPD789306
−
−
For Dot µPD789835 24 K-60 K 6 ch
−
1 ch
1 ch
2 ch
−
−
1 ch
27 pins 1.8 V
LCD
µPD789830 24 K
1 ch
2 ch
1 ch
−
1 ch (UART: 1 ch) 30 pins 2.7 V
driving
ASSP
µPD789467 4 K-24 K
µPD789327
−
1 ch
1 ch
1 ch
1 ch
−
−
18 pins 1.8 V Internal
LCD
1 ch
2 ch (USB: 1 ch) 31 pins 4.0 V
1 ch 29 pins 2.8 V
21 pins
µPD789800 8 K
µPD789840
2 ch
1 ch
−
−
−
4 ch
−
µPD789861 4 K
−
−
14 pins 1.8 V RC oscillation
version,
Internal
EEPROM
µPD789860
Internal
EEPROM
Note 10-bit timer: 1 channel
3
Data Sheet U14690EJ1V0DS00
µPD78F9136A
OVERVIEW OF FUNCTIONS
Item
function
Internal memory
Oscillator
Flash memory
16 Kbytes
256 bytes
High-speed RAM
RC Oscillator
Minimum instruction execution time
General-purpose registers
Instruction set
0.5/2.0 µs (@ 4.0-MHz operation with system clock)
8 bits × 8 registers
•
•
16-bit operations
Bit manipulations (set, reset, and test)
8 bits × 8 bits = 16 bits
Multiplier
I/O ports
Total:
20
•
•
•
CMOS input:
4
CMOS I/O:
12
4
N-ch open-drain (12-V withstand voltage):
A/D converters
Serial interface
Timer
10-bit resolution × 4 channels
Switchable between 3-wire serial I/O and UART modes
•
•
•
16-bit timer: 1 channel
8-bit timer/event counter: 1 channel
Watchdog timer: 1 channel
Timer output
1 output (16-bit/8-bit timer alternate function)
Internal: 6, External: 3
Vectored interrupt
sources
Maskable
Non-maskable
Internal: 1
Power supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
Package
TA = –40 to +85°C
30-pin plastic SSOP (7.62 mm (300))
4
Data Sheet U14690EJ1V0DS00
µPD78F9136A
CONTENTS
1. PIN CONFIGURATION (TOP VIEW)..............................................................................................
6
7
8
2. BLOCK DIAGRAM ...........................................................................................................................
3. DIFFERENCES BETWEEN µPD78F9136A AND MASKED ROM VERSION..................................
4. PIN FUNCTIONS ..............................................................................................................................
4.1 Port Pins..................................................................................................................................................
9
9
4.2 Non-Port Pins.......................................................................................................................................... 10
4.3 Pin I/O Circuits and Recommended Connection of Unused Pins...................................................... 11
5. MEMORY SPACE............................................................................................................................. 13
6. FLASH MEMORY PROGRAMMING................................................................................................. 14
6.1 Selecting Communication Mode........................................................................................................... 14
6.2 Function of Flash Memory Programming ............................................................................................ 15
6.3 Flashpro III Connection.......................................................................................................................... 15
6.4 Example of Settings for Flashpro III (PG-FP3)..................................................................................... 17
7. INSTRUCTION SET OVERVIEW .................................................................................................... 18
7.1 Conventions............................................................................................................................................ 18
7.2 Operations .............................................................................................................................................. 20
8. ELECTRICAL SPECIFICATIONS .................................................................................................... 25
9. EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS
(REFERENCE VALUES)................................................................................................................. 37
10. PACKAGE DRAWING...................................................................................................................... 39
11. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 40
APPENDIX A DEVELOPMENT TOOLS .............................................................................................. 41
APPENDIX B RELATED DOCUMENTS.............................................................................................. 43
5
Data Sheet U14690EJ1V0DS00
µPD78F9136A
1. PIN CONFIGURATION (TOP VIEW)
•
30-pin plastic SSOP (7.62 mm (300))
µPD78F9136AMC-5A4
P23/INTP0/CPT20/SS20
1
P22/SI20/R
X
D20
D20
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P24/INTP1/TO80/TO20
2
P21/SO20/T
X
P25/INTP2/TI80
AVDD
3
P20/SCK20/ASCK20
4
P11
P10
P60/ANI0
P61/ANI1
P62/ANI2
P63/ANI3
AVSS
5
6
VDD
7
VSS
8
CL1
CL2
IC0
9
IC0
10
11
12
13
14
15
P50
VPP
P51
RESET
P03
P52
P53
P02
P00
P01
Cautions 1. Connect the IC0 (Internally Connected) pin directly to VSS.
2. Connect the VPP pin directry to VSS in normal operation mode.
3. Connect the AVDD pin to VDD.
4. Connect the AVSS pin to VSS.
ANI0 to ANI3:
ASCK20:
AVDD:
Analog Input
RESET:
RXD20:
SCK20:
SI20:
Reset
Asynchronous Serial Input
Analog Power Supply
Analog Ground
RC oscillator
Receive Data
Serial Clock Input/Output
Serial Data Input
Serial Data Output
Chip Select Input
Timer Input
AVSS:
CL1,CL2:
CPT20:
SO20:
SS20:
TI80:
Capture Trigger Input
Internally Connected
Interrupt from Peripherals
Port0
IC0:
INTP0 to INTP2:
P00 to P03:
P10, P11:
P20 to P25:
P50 to P53:
P60 to P63:
TO20, TO80:
TXD20:
VDD:
Timer Output
Transmit Data
Port1
Power Supply
Port2
VPP:
Programing Power Supply
Ground
Port5
VSS:
Port6
6
Data Sheet U14690EJ1V0DS00
µPD78F9136A
2. BLOCK DIAGRAM
TI80/INTP2/P25
8-BIT TIMER/
EVENT COUNTER 80
P00 to P03
P10, P11
PORT 0
PORT 1
PORT 2
PORT 5
PORT 6
TO80/TO20
/INTP1/P24
TO20/TO80
/INTP1/P24
16-BIT TIMER 20
WATCHDOG TIMER
CPT20/INTP0
/SS20/P23
P20 to P25
P50 to P53
P60 to P63
78K/0S
CPU CORE
FLASH
MEMORY
SCK20/ASCK20
/P20
SERIAL
INTERFACE 20
SO20/TxD20/P21
SI20/RxD20/P22
SS20/INTP0
/CPT20/P23
RAM
ANI0/P60 to
ANI3/P63
RESET
CL1
A/D CONVERTER
SYSTEM
CONTROL
AVDD
AVSS
CL2
INTP0/CPT20
/P23/SS20
INTERRUPT
CONTROL
INTP1/TO80
/TO20/P24
VDD
V
SS
IC0
VPP
INTP2/TI80/P25
7
Data Sheet U14690EJ1V0DS00
µPD78F9136A
3. DIFFERENCES BETWEEN µPD78F9136A AND MASKED ROM VERSION
The µPD78F9136A is a product that substitutes flash memory for the internal ROM of the masked ROM version.
The differences between the µPD78F9136A and the masked ROM versions are shown in Table 3-1.
Table 3-1. Types of Pin Input/Output Circuits
Flash memory version
µ PD78F9136A
Masked ROM version
µ PD789132A
4 Kbytes
Item
µ PD789131A
µ PD789134A
Internal
memory
ROM
16Kbytes (Flash memory)
256 bytes
2 Kbytes
8 Kbytes
High-speed RAM
Pull-up resistor
VPP pin
12 (softwarecontrol only )
Provided
16 ( software control : 12, mask option specification : 4 )
Not provided
Electric characteristics
See the relevant data sheet
Caution
There are differences in the amount of noise tolerance and noise radiation between flash
memory versions and masked ROM versions. When considering changing from a flash
memory version to
a masked ROM version during process from experimental
manufacturing to mass production, make sure to sufficiently evaluate the masked ROM
versions using commercial samples (CS) (not engineering samples (ES)).
8
Data Sheet U14690EJ1V0DS00
µPD78F9136A
4. PIN FUNCTIONS
4.1 Port Pins
Pin Name
I/O
I/O
Function
After Reset
Alternate Function
–
P00 to
P03
Input
Input
Input
Port 0
4-bit input/output port
Input/output can be specified in 1-bit units
When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
P10, P11
I/O
I/O
–
Port 1
2-bit input/output port
Input/output can be specified in 1-bit units
When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
P20
P21
P22
P23
SCK20/ASCK20
SO20/TxD20
SI20/RxD20
Port 2
6-bit input/output port
Input/output can be specified in 1-bit units
When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
INTP0/CPT20
/SS20
P24
P25
INTP1/TO80/TO20
INTP2/TI80
–
P50 to
P53
I/O
Input
Input
Port 5
4-bit N-ch open-drain input/output port
Input/output can be specified in 1-bit units
An on-chip pull-up resistor can be specified by the mask option.
P60 to
P63
Input
Port 6
ANI0 to ANI3
4-bit input-only port
9
Data Sheet U14690EJ1V0DS00
µPD78F9136A
4.2 Non-Port Pins
Pin Name
INTP0
I/O
Function
After Reset
Input
Alternate Function
Input
P23/CPT20/SS20
External interrupt request input for which the valid edge
(rising edge, falling edge, or both rising and falling edges) can
be specified
INTP1
INTP2
SI20
P24/TO80/TO20
P25/TI80
Input
Output
I/O
Serial interface serial data input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
–
P22/RxD20
SO20
SCK20
ASCK20
SS20
RxD20
TxD20
TI80
Serial interface serial data output
P21/TxD20
Serial interface serial clock input/output
Serial clock input for asynchronous serial interface
Chip select input for serial interface
Serial data input for asynchronous serial interface
Serial data output for asynchronous serial interface
External count clock input to 8-bit timer/event counter 80
8-bit timer/event counter 80 output
16-bit timer 20 output
P20/ASCK20
Input
Input
Input
Output
Input
Output
Output
Input
Input
-
P20/SCK20
P23/CPT20/INTP0
P22/SI20
P21/SO20
P25/INTP2
TO80
TO20
CPT20
ANI0 to ANI3
AVDD
P24/INTP1/TO20
P24/INTP1/TO80
Capture edge input
P23/INTP0/SS20
A/D converter analog input
P60 to P63
A/D converter analog power supply
A/D converter ground potential
–
–
–
–
–
–
–
–
AVSS
-
–
CL1
Input
-
Connected to resistor (R) or capacitor (C)
–
CL2
–
RESET
VDD
Input
-
System reset input
Positive power supply
Ground potential
Input
–
VSS
-
–
VPP
-
Sets flash memory programming mode. Applies high voltage
when a program is written or verified. Connect directly to VSS
in normal operation mode.
–
IC0
-
Internally connected. Connect directly to VSS.
–
–
10
Data Sheet U14690EJ1V0DS00
µPD78F9136A
4.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 4-1.
For the input/output circuit configuration of each type, refer to Figure 4-1.
Table 4-1. Types of Pin Input/Output Circuits
Pin Name
Input/Output
Circuit Type
I/O
I/O
Recommended Connection of Unused Pins
P00 to P03
5-A
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open
P10, P11
P20/SCK20/ASCK20
P21/SO20/TXD20
P22/SI20/RXD20
P23/INTP0/CPT20/SS20
P24/INTP1/TO80/TO20
P25/INTP2/TI80
P50 to P53
8-A
Input:
Independently connect to VSS via a resistor.
Output: Leave open
13-V
Input:
Independently connect to VDD via a resistor.
Output: Leave open
P60/ANI0 to P63/ANI3
9-C
–
Input
–
Connect directly to VDD or VSS.
Connect to VDD.
AVDD
AVSS
RESET
VPP
Connect to VSS.
2
–
Input
–
–
Connect directly to VSS.
IC0
11
Data Sheet U14690EJ1V0DS00
µPD78F9136A
Figure 4-1. Pin Input/Output Circuits
Type 2
Type 9-C
Comparator
P-ch
+
IN
N-ch
–
IN
AVSS
(Threshold voltage)
V
REF
Schmitt-triggered input with hysteresis characteristics
Input
enable
Type 13-V
Type 5-A
VDD
Pull-up
enable
P-ch
IN/OUT
V
DD
Output data
Output disable
N-ch
Data
P-ch
IN/OUT
V
SS
Output
disable
N-ch
Input enable
V
SS
Middle-voltage input buffer
Input
enable
Type 8-A
VDD
Pull-up
enable
P-ch
V
DD
Data
P-ch
IN/OUT
Output
disable
N-ch
V
SS
12
Data Sheet U14690EJ1V0DS00
µPD78F9136A
5. MEMORY SPACE
Figure 5-1 shows the memory map of the µPD78F9136A.
Figure 5-1. Memory Map
F F F F H
Special function registers
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
256 × 8 bits
F E 0 0 H
F D F F H
Reserved
Data memory space
3 F F F H
4 0 0 0 H
3 F F F H
Program area
0 0 8 0 H
0 0 7 F H
Program memory
space
Flash memory
CALLT table area
16384 × 8 bits
0 0 4 0 H
0 0 3 F H
Program area
0 0 1 6 H
0 0 1 5 H
Vector table area
0 0 0 0 H
0 0 0 0 H
13
Data Sheet U14690EJ1V0DS00
µPD78F9136A
6. FLASH MEMORY PROGRAMMING
The on-chip program memory in the µPD78F9136A is a flash memory.
The flash memory can be written with the µPD78F9136A mounted on the target system (on-board). Connect the
dedicated flash programmer (Flashpro III (model number: FL-PR3, PG-FP3)) to the host machine and target system
to write the flash memory.
Remark FL-PR3 is made by Naito Densei Machida Mfg. Co., Ltd..
6.1 Selecting Communication Mode
The flash memory is written by using Flashpro III and by means of serial communication. Select a communication
mode from those listed in Table 6-1. To select a communication mode, the format shown in Figure 6-1 is used. Each
communication mode is selected by the number of VPP pulses shown in Table 6-1.
Table 6-1. Communication Mode List
Communication mode
3-wired serial I/O mode
Pins used
Number of VPP pulses
SCK20/ASCK20/P20
SO20/TxD20/P21
SI20/RxD20/P22
0
8
UART
TxD20/SO20/P21
RxD/SI20/P22
Pseudo 3-wire modeNote
P00 (Serial clock input)
P01 (Serial data output)
P02 (Serial data input)
12
Note Serial transfer is performed by controlling a port by software.
Caution
Be sure to select a communication mode depending on the VPP pulse number shown in Table 6-1.
Figure 6-1. Communication Mode Selection Format
10 V
V
PP
V
DD
1
2
n
V
SS
V
DD
RESET
V
SS
14
Data Sheet U14690EJ1V0DS00
µPD78F9136A
6.2 Function of Flash Memory Programming
By transmitting/receiving commands and data in the selected communication mode, operations such as writing to
the flash memory are performed. Table 6-2 shows the major functions of flash memory programming.
Table 6-2. Functions of Flash Memory Programming
Function
Batch erase
Description
Erases all contents of memory
Batch blank check
Data write
Checks erased state of entire memory
Write to flash memory based on write start address and number of data written (number of bytes)
Compares all contents of memory with input data
Batch verify
6.3 Flashpro III Connection
How the Flashpro III is connected to the µPD78F9136A differs depending on the communication mode (3-wired
serial I/O or pseudo 3-wire mode). Figures 6-2 to 6-4 show the connection in the respective mode.
Figure 6-2. Flashpro III Connection in 3-wired Serial I/O Mode
µ
Flashpro III
PD78F9136A
V
PPnNote
V
V
PP
V
DD
DD, AVDD
RESET
CLK
SCK
SO
RESET
P03
SCK20
SI20
SI
SO20
GND
VSS, AVSS
Note n = 1, 2
15
Data Sheet U14690EJ1V0DS00
µPD78F9136A
Figure 6-3. Flashpro III Connection in UART Mode
Flashpro III
µPD78F9136A
V
PPnNote
V
V
PP
V
DD
DD, AVDD
RESET
CLK
SO
RESET
P03
RxD20
TxD20
SI
GND
VSS, AVSS
Note n= 1, 2
Figure 6-4. Flashpro III Connection in Pseudo 3-Wire Mode (When Port 0 is Used)
Flashpro III
µ
PD78F9136A
V
PPnNote
V
V
PP
V
DD
DD, AVDD
RESET
CLK
SCK
SO
RESET
P03
P00 (Serial clock)
P02 (Serial input)
P01 (Serial output)
SI
GND
VSS, AVSS
Note n= 1, 2
16
Data Sheet U14690EJ1V0DS00
µPD78F9136A
6.4 Example of Settings for Flashpro III (PG-FP3)
Set as follows when writing to flash memory using the Flashpro III (PG-FP3).
<1> Download the parameter file.
<2> Select the serial mode and the serial clock using the type command.
<3> The following is a setting example using the PG-FP3.
Table 6-3. Example Using PG-FP3
Communication mode
3-wired serial I/O mode
Setting example using PG-FP3
Number of V
PP pulsesNote1
COMM PORT
SIO ch-0
0
CPU CLK
On target board
In Flashpro
4.1943 MHz
1.0 MHz
On target board
SIO CLK
In Flashpro
SIO CLK
4.0 MHz
1.0 MHz
UART
COMM PORT
CPU CLK
UART-ch0
On target board
In Flashpro
4.1943 MHz
9600 bpsNote2
Port B
8
On target board
UART BPS
Pseudo 3-wire mode
COMM PORT
CPU CLK
12
On target board
In Flashpro
4.1943 MHz
1 kHz
On target board
SIO CLK
In Flashpro
SIO CLK
4.0 MHz
1 kHz
Notes 1. The number of VPP pulses supplied from the Flashpro III during serial communication initialization. The
pins to be used in communication are determined by this number of pulses.
2. Select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps.
Remark COMM PORT: Selection of serial port
SIO CLK
CPU CLK
: Selection of serial clock frequency
: Selection of CPU clock source to be input
17
Data Sheet U14690EJ1V0DS00
µPD78F9136A
7. INSTRUCTION SET OVERVIEW
The instruction set for the µPD78F9136A is listed later.
7.1 Conventions
7.1.1 Operand identifiers and description methods
Operands are described in the “Operand” column of each instruction in accordance with the description method of
the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more
description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, $, and [ ], are keywords
and must be described as they are. Each symbol has the following meaning.
•
•
#: Immediate data specification
!: Absolute address specification
•
•
$:
Relative address specification
[ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #,!, $, or [ ] symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 7-1. Operand Identifiers and Description Methods
Identifier
Description Method
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7),
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special function register symbol
rp
sfr
saddr
FE20H to FF1FH immediate data or label
saddrp
FE20H to FF1FH immediate data or label (even address only)
addr16
addr5
0000H to FFFFH immediate data or label
(Only even addresses for 16-bit data transfer instructions)
0040H to 007FH immediate data or label (even address only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
18
Data Sheet U14690EJ1V0DS00
µPD78F9136A
7.1.2 Descriptions of the operation field
A:
A register; 8-bit accumulator
X:
X register
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
BC:
DE:
HL:
PC:
SP:
PSW:
CY:
AC:
Z:
AX register pair; 16-bit accumulator
BC register pair
DE register pair
HL register pair
Program counter
Stack pointer
Program status word
Carry flag
Auxiliary carry flag
Zero flag
IE:
NMIS:
( ):
XH, XL:
:
Interrupt request enable flag
Non-maskable interrupt servicing flag
Memory contents indicated by address or register contents in parentheses
Higher 8 bits and lower 8 bits of 16-bit register
Logical product (AND)
:
Logical sum (OR)
:
Exclusive OR
:
Inverted data
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
7.1.3 Description of the flag operation field
(Blank): Not affected
0:
1:
×:
R:
Cleared to 0
Set to 1
Set/cleared according to the result
Previously saved value is restored
19
Data Sheet U14690EJ1V0DS00
µPD78F9136A
7.2 Operations
Mnemonic
Operand
Byte
Clock
Operation
Flag
Z AC CY
MOV
r, #byte
3
3
3
2
2
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
2
2
2
1
1
2
3
2
2
1
1
1
6
6
6
4
4
4
4
4
4
8
8
6
4
4
6
6
6
6
6
6
4
6
6
6
8
8
8
6
6
8
4
4
8
r ← byte
saddr , #byte
sfr, #byte
A, r
(addr) ← byte
sfr ← byte
A ← r
Note 1
Note 1
r, A
r ← A
A, saddr
saddr, A
A, sfr
A ← (saddr)
(saddr) ← A
A ← sfr
sfr, A
sfr ← A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
×
×
×
×
×
×
[DE], A
A, [HL]
[HL], A
(HL) ← A
A, [HL + byte]
[HL + byte], A
A, X
A ← (HL + byte)
(HL + byte) ← A
A ↔ X
XCH
Note 2
A, r
A ↔ r
A, saddr
A, sfr
A ↔ (saddr)
A ↔ (sfr)
A, [DE]
A ↔ (DE)
A, [HL]
A ↔ (HL)
A, [HL + byte]
rp, #word
AX, saddrp
saddrp, AX
AX, rp
A ↔ (HL + byte)
rp ← word
AX ← (saddrp)
(saddrp) ← AX
AX ← rp
MOVW
Note 3
Note 3
Note 3
rp, AX
rp ← AX
XCHW
AX, rp
AX ↔ rp
Notes 1. Except r = A
2. Except r = A or X
3. Only when rp = BC, DE, HL
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control
register (PCC).
20
Data Sheet U14690EJ1V0DS00
µPD78F9136A
Mnemonic
ADD
Operand
Byte
Clock
Operation
Flag
Z AC CY
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
A, CY ← A + byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte
A, r
(saddr), CY ← (saddr) + byte
A ,CY ← A + r
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, CY ← A + (HL + byte)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
ADDC
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A – byte
A, [HL + byte]
A, #byte
saddr, #byte
A, r
SUB
(saddr), CY ← (saddr) – byte
A, CY ← A – r
A, saddr
A, !addr16
A, [HL]
A, CY ← A – (saddr)
A, CY ← A – (addr16)
A, CY ← A – (HL)
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, CY ← A – (HL + byte)
A, CY ← A – byte – CY
(saddr), CY ← (saddr) – byte – CY
A, CY ← A – r – CY
SUBC
A, saddr
A, !addr16
A, [HL]
A, CY ← A – (saddr) – CY
A, CY ← A – (addr16) – CY
A, CY ← A – (HL) – CY
A, CY ← A – (HL + byte) – CY
A ← A byte
A, [HL + byte]
A, #byte
saddr, #byte
A, r
AND
(saddr) ← (saddr) byte
A ← A
r
A, saddr
A, !addr16
A, [HL]
A ← A (saddr)
A ← A (addr16)
A ← A (HL)
A, [HL + byte]
A ← A (HL + byte)
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control
register (PCC).
21
Data Sheet U14690EJ1V0DS00
µPD78F9136A
Mnemonic
Operand
Byte
Clock
Operation
Flag
Z AC CY
OR
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
A ← A byte
(saddr) ← (saddr) byte
A ← A
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte
A, r
r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A ← A (saddr)
A ← A (addr16)
A ← A (HL)
A ← A (HL + byte)
A ← A byte
XOR
(saddr) ← (saddr) byte
A ← A
r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A ← A (saddr)
A ← A (addr16)
A ← A (HL)
A ← A (HL + byte)
A – byte
CMP
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
(saddr) – byte
A – r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
AX, #word
AX, #word
AX, #word
r
A – (saddr)
A – (addr16)
A – (HL)
A – (HL + byte)
ADDW
SUBW
CMPW
INC
AX, CY ← AX + word
AX, CY ← AX – word
AX – word
r ← r + 1
saddr
(saddr) ← (saddr) + 1
r ← r – 1
DEC
r
saddr
(saddr) ← (saddr) – 1
rp ← rp + 1
INCW
DECW
ROR
rp
rp
rp ← rp – 1
A, 1
(CY, A7 ← A0, Am – 1 ← Am) × 1
(CY, A0 ← A7, Am + 1 ← Am) × 1
(CY ← A0, A7 ← CY, Am – 1 ← Am) × 1
(CY ← A7, A0 ← CY, Am + 1 ← Am) × 1
×
×
×
×
ROL
A, 1
RORC
ROLC
A, 1
A, 1
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control
register (PCC).
22
Data Sheet U14690EJ1V0DS00
µPD78F9136A
Mnemonic
SET1
Operand
Byte
Clock
Operation
Flag
Z AC CY
saddr. bit
3
3
2
3
2
3
3
2
3
2
1
1
1
3
6
6
(saddr. bit) ← 1
sfr. bit ← 1
A. bit ← 1
sfr. bit
A. bit
4
PSW. bit
[HL]. bit
saddr. bit
sfr. bit
A. bit
6
PSW. bit ← 1
(HL) . bit ← 1
(saddr. bit) ← 0
sfr. bit ← 0
A. bit ← 0
×
×
×
10
6
CLR1
6
4
PSW. bit
[HL]. bit
CY
6
PSW. bit ← 0
(HL) . bit ← 0
CY ← 1
×
×
×
10
2
SET1
CLR1
NOT1
CALL
1
0
×
CY
2
CY ← 0
CY
2
CY ← CY
!addr16
6
(SP – 1) ← (PC + 3)H,(SP – 2) ← (PC + 3)L,
PC ← addr16, SP ← SP – 2
CALLT
[addr5]
1
8
(SP – 1) ← (PC + 1)H,(SP – 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP – 2
RET
1
1
6
8
PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
RETI
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3,
NMIS ← 0
R R R
PUSH
POP
PSW
rp
1
1
2
4
(SP – 1) ← PSW, SP ← SP – 1
(SP – 1) ← rpH, (SP – 2) ← rpL,
SP ← SP – 2
PSW
rp
1
1
4
6
PSW ← (SP), SP ← SP + 1
R R R
rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
MOVW
BR
SP, AX
AX, SP
!addr16
$addr16
AX
2
2
3
2
1
8
6
6
6
6
SP ← AX
AX ← SP
PC ← addr16
PC ← PC + 2 + jdisp8
PCH ← A, PCL ← X
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control
register (PCC).
23
Data Sheet U14690EJ1V0DS00
µPD78F9136A
Mnemonic
Operand
Byte
Clock
Operation
Flag
Z AC CY
BC
$addr16
2
2
2
2
4
6
6
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
BNC
BZ
$addr16
$addr16
6
BNZ
BT
$addr16
6
saddr. bit, $addr16
10
PC ← PC + 4 + jdisp8
if (saddr. bit) = 1
sfr. bit, $addr16
A. bit , $addr16
4
3
4
4
10
8
PC ← PC + 4 + jdisp8 if sfr. bit = 1
PC ← PC + 3 + jdisp8 if A. bit = 1
PC ← PC + 4 + jdisp8 if PSW. bit = 1
PSW. bit, $addr16
saddr. bit, $addr16
10
10
BF
PC ← PC + 4 + jdisp8
if (saddr. bit) = 0
sfr. bit, $addr16
A. bit, $addr16
PSW. bit, $addr16
B, $addr16
4
3
4
2
10
8
PC ← PC + 4 + jdisp8 if sfr. bit = 0
PC ← PC + 3 + jdisp8 if A. bit = 0
PC ← PC + 4 + jdisp8 if PSW. bit = 0
10
6
DBNZ
B ← B – 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16
2
3
6
8
C ← C – 1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
saddr, $addr16
(saddr) ← (saddr) – 1, then
PC ← PC + 3 + jdisp8 if(saddr) ≠ 0
NOP
EI
1
3
3
1
1
2
6
6
2
2
No Operation
IE ← 1(Enable Interrupt)
IE ← 0(Disable Interrupt)
Set HALT Mode
DI
HALT
STOP
Set STOP Mode
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control
register (PCC).
24
Data Sheet U14690EJ1V0DS00
µPD78F9136A
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD, AVDD
VPP
Conditions
Ratings
–0.3 to +6.5
–0.3 to +10.5
–0.3 to VDD + 0.3
–0.3 to +13
–0.3 to VDD + 0.3
–10
Unit
V
VDD = AVDD
V
Input voltage
VI1
Pins other than P50 to P53
V
VI2
P50 to P53
With N-ch open drain
V
Output voltage
VO
V
Output current, high
IOH
Per pin
mA
mA
mA
mA
°C
°C
°C
Total for all pins
–30
Output current, low
IOL
Per pin
30
Total for all pins
160
Operating ambient temperature
Storage temperature
TA
In normal operation mode
During flash memory programming
–40 to +85
10 to 40
Tstg
–40 to +125
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
25
Data Sheet U14690EJ1V0DS00
µPD78F9136A
System Clock Oscillator Characteristics
(TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Recommended
Resonator
Circuit
Parameter
Conditions
MIN. TYP. MAX. Unit
CC)Note 1
V
DD
= oscillation voltage
2.0
4.0
MHz
CL1
CL2
CL2
RC
Oscillation frequency (f
resonator
range
External
clock
CL1 input frequency (fCC)Note 1
1.0
85
5.0
MHz
ns
CL1
CL1 input high-/low-level
width (tXH, tXL)
500
CL1 input frequency (fCC)Note 1 VDD = 2.7 to 5.5 V
1.0
85
5.0
MHz
ns
CL1
CL2
CL1 input high-/low-level
width (tXH, tXL)
500
OPEN
Note Indicates only oscillator characteristics. Refer to AC characteristics for instruction execution time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
RC Oscillator Frequency Characteristics (TA = –40 to +85°C)
Parameter
Symbol
fCC1
Conditions
R = 11.0 k Ω, C = 22 pF
MIN.
1.5
TYP. MAX.
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Oscillator frequency
VDD = 2.7 to 5.5 V
VDD = 1.8 to 3.6 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 3.6 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 3.6 V
VDD = 1.8 to 5.5 V
2.0
2.0
2.0
3.0
3.0
3.0
4.0
4.0
4.0
2.5
2.5
2.5
3.5
3.5
3.5
4.7
4.7
4.7
Target : 2 MHz
fCC2
0.5
fCC3
0.5
fCC4
R = 6.8 k Ω, C = 22 pF
2.5
Target : 3 MHz
fCC5
0.75
0.75
3.5
fCC6
fCC7
R = 4.7 k Ω, C = 22 pF
Target : 4 MHz
fCC8
1.0
fCC9
1.0
Remark So that the TYP. Spec is satisfied between 2.0 to 4.0 MHz, set one of the above nine patterns for R and
C.
26
Data Sheet U14690EJ1V0DS00
µPD78F9136A
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter
Symbol
IOH
Conditions
MIN.
TYP.
MAX.
–1
Unit
mA
mA
mA
mA
V
Output current, high
Per pin
Total for all pins
Per pin
–15
10
Output current, low
Input voltage, high
IOL
Total for all pins
80
VIH1
Pins other than described
below
VDD = 2.7 to 5.5 V
0.7 VDD
0.9 VDD
0.7 VDD
VDD
VDD
12
V
VIH2
P50 to P53 N-ch open drain VDD = 2.7 to 5.5 V
V
VDD = 1.8 to 5.5 V 0.9 VDD
12
V
TA = 25 to 85 °C
VIH3
VIH4
VIL1
RESET, P20 to P25
CL1, CL2
VDD = 2.7 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 2.7 to 5.5 V
0.8 VDD
VDD
VDD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.9 VDD
VDD–0.5
VDD
VDD–0.1
VDD
Input voltage, low
Pins other than described
below
0
0.3 VDD
0.1 VDD
0.3 VDD
0.2 VDD
0.1 VDD
0.4
0
VIL2
VIL3
P50 to P53
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
0
RESET, P20 to P25
0
0
0
VIL4
CL1, CL2
VDD = 4.5 to 5.5 V
0
0.1
Output voltage, high
Output voltage, low
VOH1
VOH2
VOL1
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD–1.0
VDD–0.5
VDD = 1.8 to 5.5 V, IOH = –100 µA
Pins other
than P50 to
P53
VDD = 4.5 to 5.5 V, IOL = 10 mA
1.0
VDD = 1.8 to 5.5 V, IOL = 400 µA
VDD = 4.5 to 5.5 V, IOL = 10 mA
VDD = 1.8 to 5.5 V, IOL = 1.6 mA
0.5
1.0
0.4
V
V
V
VOL2
P50 to P53
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
27
Data Sheet U14690EJ1V0DS00
µPD78F9136A
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter
Symbol
ILIH1
Conditions
MIN.
TYP.
MAX.
Unit
Input leakage current,
high
Pins other than CL1,
VIN = VDD
3
µA
CL2, or P50 to P53
ILIH2
ILIH3
CL1, CL2
20
20
µA
µA
P50 to P53 (N-ch open
drain)
VIN = 12 V
VIN = 0 V
Input leakage current,
low
ILIL1
Pins other than CL1,
CL2, or P50 to P53
–3
µA
ILIL2
ILIL3
CL1, CL2
–20
µA
µA
P50 to P53 (N-ch open
drain)
–3Note 1
µA
µA
kΩ
Output leakage
current, high
ILOH
VOUT = VDD
3
Output leakage
current, low
ILOL
VOUT = 0 V
–3
Software pull-up
resistor
R1
VIN = 0 V, for pins other than P50 to P53
50
100
200
Power supply
current
IDD1Note 2
4.0-MHz RC oscillation
operating mode
VDD = 5.0 V±10%Note 4
5.0
1.9
15.0
4.9
3.0
5.0
2.0
1.5
30
mA
mA
mA
mA
mA
mA
µA
VDD = 3.0 V±10%Note 5
VDD = 2.0 V±10%Note 5
VDD = 5.0 V±10%Note 4
VDD = 3.0 V±10%Note 5
VDD = 2.0 V±10%Note 5
VDD = 5.0 V±10%
(R = 4.7 kΩ, C = 22pF)
1.5
IDD2Note 2
IDD3Note 2
IDD4Note 3
4.0-MHz RC oscillation
HALT mode (R = 4.7
kΩ, C = 22pF)
2.5
1.0
0.75
0.1
STOP mode
µA
VDD = 3.0 V±10%
0.05
0.05
6.2
10
µA
VDD = 2.0 V±10%
10
4.0-MHz RC oscillation
A/D operating mode
(R = 4.7 kΩ, C = 22pF)
VDD = 5.0 V±10%Note 4
VDD = 3.0 V±10%Note 5
VDD = 2.0 V±10%Note 5
17.3
7.2
5.0
mA
mA
mA
3.1
2.5
Notes 1. When port 5 is in input mode, a low-level input leakage current of –60 µA (MAX.) flows only for 1 cycle
time after a read instruction has been executed to port 5.
2. The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) is not
included.
4. High-speed mode operation (when processor clock control register (PCC) is set to 00H.)
5. Low-speed mode operation (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
28
Data Sheet U14690EJ1V0DS00
µPD78F9136A
FLASH MEMORY WRITE/DELETE CHARACTERISTICS (TA = 10°C to 40°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
mA
Write current
(VDD pin)Note
IDDW
When VPP supply voltage = VPP1
(in 5.0-MHz operation mode)
When VPP supply voltage = VPP1
18
Write current
(VPP pin)Note
IPPW
22.5
mA
Delete current
(VDD pin)Note
IDDE
When VPP supply voltage = VPP1
(in 5.0-MHz operation mode)
18
mA
mA
Delete current
(VPP pin)Note
IPPE
When VPP supply voltage = VPP1
115
Unit delete time
Total delete time
Write count
ter
0.5
1
1
20
s
tera
s
Times
V
Delete/write are regarded as 1 cycle
In normal operation
20
VPP supply voltage VPP0
VPP1
0
0.2VDD
10.3
During flash memory programming
9.7
10.0
V
Note The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and AVDD
current are not included.
29
Data Sheet U14690EJ1V0DS00
µPD78F9136A
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
TCY
Conditions
MIN.
0.4
TYP.
MAX.
Unit
VDD = 2.7 to 5.5 V
8
8
µs
(minimum instruction
execution time)
1.6
µs
TI80 input high-/low-
level width
tTIH,
tTIL
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
INTP0 to INTP2
0.1
1.8
0
µs
µs
MHz
kHz
TI80 input frequency
fTI
4
0
275
Interrupt input high-
/low-level width
tINTH,
tINTL
10
µs
µs
µs
RESET low-level
width
tRSL
10
10
CPT20 input high-
/low-level width
tCPH,
tCPL
TCY vs VDD
60
10
µ
Guaranteed
operation range
2.0
1.0
0.5
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
30
Data Sheet U14690EJ1V0DS00
µPD78F9136A
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...Internal clock output)
Parameter
Symbol
tKCY1
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
3200
tKCY1/2 – 50
tKCY1/2 – 150
150
SCK20 high-/low-
level width
tKH1,
tKL1
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
SI20 setup time
tSIK1
tKSI1
tKSO1
(to SCK20↑)
500
SI20 hold time
400
(from SCK20↑)
600
SO20 output delay
R = 1 k Ω,
C = 100 pFNote
VDD = 2.7 to 5.5 V
0
250
time from SCK20↓
0
1000
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...External clock input)
Parameter
Symbol
tKCY2
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
3200
400
1600
100
150
400
600
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
SCK20 high-/low-
level width
tKH2,
tKL2
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
SI20 setup time
tSIK2
tKSI2
tKSO2
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 5.5 V
300
time from SCK20↓
0
1000
120
ns
ns
SO20 setup time
(for SS20↓ when
SS20 is used)
tKAS2
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
400
240
800
ns
ns
ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
Note R and C are the load resistance and load capacitance of the SO output line.
(iii) UART mode (Dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
TYP.
MAX.
78125
19531
Unit
bps
bps
31
Data Sheet U14690EJ1V0DS00
µPD78F9136A
(iv) UART mode (external clock input)
Parameter
Symbol
tKCY3
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ASCK20 cycle time
3200
400
ns
ASCK20 high-/low-
level width
tKH3,
tKL3
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
ns
1600
ns
Transfer rate
39063
9766
1
bps
bps
µ s
ASCK20 rise/fall time
tR,
tF
32
Data Sheet U14690EJ1V0DS00
µPD78F9136A
AC Timing Test Points (excluding CL1 input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Test points
Clock Timing
1/fCC
t
XL
t
XH
V
IH4 (MIN.)
CL1 input
V
IL4 (MAX.)
TI Timing
1/fTI
t
TIL
t
TIH
TI80
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP2
RESET Input Timing
t
RSL
RESET
33
Data Sheet U14690EJ1V0DS00
µPD78F9136A
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
Input data
SI20
t
KSOm
Output data
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20
t
KAS2
t
KDS2
SO20
Output data
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK20
34
Data Sheet U14690EJ1V0DS00
µPD78F9136A
10-Bit A/D Converter Characteristics
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
bit
Resolution
Overall errorNote1,2
4.5 V ≤ VDD ≤ 5.5 V
±0.2
±0.4
±0.8
±0.4
±0.6
±1.2
100
%FSR
%FSR
%FSR
µs
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
Conversion time
tCONV
14
28
100
µs
Zero-scale errorNote1,2
±0.4
±0.6
±1.2
±0.4
±0.6
±1.2
±2.5
±4.5
±8.5
±1.5
±2.0
±3.5
AVDD
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
LSB
Full-scale errorNote1,2
Integral linearity
errorNote1
ILE
LSB
LSB
Differential linearity
errorNote1
DLE
VIAN
LSB
LSB
LSB
Analog input voltage
0
V
Notes 1. Excludes quantization error (±0.05%FSR).
2. It is indicated as a ratio to the full-scale value (%FSR).
35
Data Sheet U14690EJ1V0DS00
µPD78F9136A
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
VDDDR
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention
supply voltage
Release signal
set time
tSREL
0
µs
Oscillation
stabilization wait
timeNote
tWAIT
Release by RESET
Release by interrupt request
27/fCC
27/fCC
ms
ms
Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
Remark fCC: System clock oscillation frequency
Data Retention Timing (STOP mode release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
VDDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
36
Data Sheet U14690EJ1V0DS00
µPD78F9136A
9. EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES)
fCC vs VDD (RC Oscillation, R = 11 kΩ, C = 22 pF)
(TA=–40°C)
2.6
2.4
CL1
CL2
11 kΩ
22 pF
2.2
2.0
1.8
Sample A
Sample B
Sample C
1.6
1.4
2
3
4
5
6
Supply voltage VDD[V]
(TA=25°C)
2.6
2.4
CL1
CL2
11 kΩ
22 pF
2.2
2.0
1.8
Sample A
Sample B
Sample C
1.6
1.4
2
3
4
5
6
Supply voltage VDD[V]
(TA=85°C)
2.6
2.4
CL1
CL2
11 kΩ
22 pF
2.2
2.0
1.8
Sample A
Sample B
Sample C
1.6
1.4
2
3
4
5
6
Supply voltage VDD[V]
37
Data Sheet U14690EJ1V0DS00
µPD78F9136A
fCC vs VDD (RC Oscillation, R = 4.7 kΩ, C = 22 pF)
(TA=–40 C)
4.6
4.4
CL1
CL2
4.7 kΩ
22 pF
4.2
4.0
3.8
Sample A
Sample B
Sample C
3.6
3.4
2
2
2
3
3
3
4
5
5
5
6
6
6
Supply voltage VDD[V]
(TA=25 C)
4.6
4.4
CL1
CL2
4.7 kΩ
22 pF
4.2
4.0
3.8
Sample A
Sample B
Sample C
3.6
3.4
4
Supply voltage VDD[V]
(TA=85 C)
4.6
4.4
CL1
CL2
4.7 kΩ
22 pF
4.2
4.0
3.8
Sample A
Sample B
Sample C
3.6
3.4
4
Supply voltage VDD[V]
38
Data Sheet U14690EJ1V0DS00
µPD78F9136A
10. PACKAGE DRAWING
30-PIN PLASTIC SSOP (7.62 mm (300))
30
16
detail of lead end
F
G
T
P
L
1
15
U
E
A
H
I
J
S
B
C
N
S
M
D
M
K
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
9.85±0.15
0.45 MAX.
0.65 (T.P.)
+0.08
0.24
D
−0.07
E
F
G
H
I
0.1±0.05
1.3±0.1
1.2
8.1±0.2
6.1±0.2
1.0±0.2
0.17±0.03
0.5
J
K
L
M
N
0.13
0.10
+5°
3°
P
−3°
T
0.25
U
0.6±0.15
S30MC-65-5A4-2
39
Data Sheet U14690EJ1V0DS00
µPD78F9136A
11. RECOMMENDED SOLDERING CONDITIONS
The µPD78F9136A should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended
below, contact your NEC sales representative.
Table 10-1. Surface Mounting Type Soldering Conditions
µPD78F9136AMC-5A4: 30-pin plastic SSOP (7.62 mm (300))
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Reflow time: 30 seconds or below (at 210°C
or higher), Number of reflow processes : 3 max., Exposure limit : 7daysNote
(after that, prebaking is necessary at 125°C for 10 hours)
IR35-107-3
VP15-107-3
WS60-107-1
VPS
Package peak temperature: 215°C, Reflow time: 40 seconds or below (at 200°C
or higher), Number of reflow processes : 3 max., Exposure limit : 7daysNote
(after that, prebaking is necessary at 125°C for 10 hours)
Wave soldering
Solder bath temperature: 260°C or below, Flow time: 10 seconds or below,
Number of flow processes: 1
Preheating temperature: 120°C or below (package surface temperature),
Exposure limit : 7daysNote (after that, prebaking is necessary at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C Max., Time: 3 sec. Max. (per pin row)
–
Note
After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
40
Data Sheet U14690EJ1V0DS00
µPD78F9136A
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD78F9116A.
Language Processing Software
RA78K0SNotes 1, 2, 3
CC78K0SNotes 1, 2, 3
DF789136Notes 1, 2, 3
Assembler package common to 78K/0S Series
C compiler package common to 78K/0S Series
Device file for µPD78F9136A
Flash Memory Writing Tools
Flashpro lIl
(Model number: FL-PR3Note 4
Dedicated flash programmer for on-chip flash memory
,
PG-FP3)
FA-30MCNote 4
Flash memory writing adapter
Debugging Tools (1/2)
IE-78K0S-NS
In-circuit emulator serves to debug hardware and software when developing application systems
using a 78K/0S Series product. It supports the ID78K0S-NS integrated debugger. Used in
combination with an AC adapter, emulation probe, and interface adapter connecting to the host
machine.
In-circuit emulator
IE-70000-MC-PS-B
AC adapter
Adapter used to supply power from a power outlet of 100 V AC to 240 V AC.
IE-70000-98-IF-C
Interface adapter
Adapter when PC-9800 series PC (except notebook type) is used as the IE-78K0S-NS host
machine (C bus supported).
IE-70000-CD-IF-A
PC card interface
PC card and interface cable when notebook PC is used as the IE-78K0S-NS host machine
(PCMCIA socket supported).
IE-70000-PC-IF-C
Interface adapter
Adapter when using an IBM PC/AT™ or compatible as the IE-78K0S-NS host machine.
IE-70000-PCI-IF
Interface adapter
Adapter when using PC that includes a PCI bus as the IE-78K0S-NS host machine.
IE-789136-NS-EM1
Emulation board
Board for emulation of the peripheral hardware peculiar to a device. Used in combination with
an in-circuit emulator.
NP-36GSNote 4
Board used to connect the in-circuit emulator to the target system. For a 30-pin plastic SSOP
(MC-5A4 type), used in combination with NGS-30.
NGS-30Note 4
Conversion socket used to connect the NP-36GS to the target system board designed to mount
a 30-pin plastic SSOP (MC-5A4 type).
Conversion socket
Notes 1. PC-9800 series (Japanese Windows™) based
2. IBM PC/AT or compatibles (Japanese/English Windows) based
3. HP9000 series 700™ (HP-UX™), SPARCstation™ (SunOS™, Solaris™), or NEWS™ (NEWS-OS™)
based.
4. Products made by Naito Densei Machida Mfg. Co., Ltd. (Phone: +81-44-822-3813).
Remark RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789136.
41
Data Sheet U14690EJ1V0DS00
µPD78F9136A
Debugging Tools (2/2)
SM78K0SNotes 1, 2
ID78K0S-NSNotes 1, 2
DF789136Notes 1, 2
System simulator common to 78K/0S Series
Integrated debugger common to 78K/0S Series
Device file for µPD78F9136A
Real-time OS
MX78K0SNotes 1, 2
OS for 78K/0S Series
Notes 1. PC-9800 series (Japanese Windows) based.
2. IBM PC/AT or compatibles (Japanese/English Windows) based.
42
Data Sheet U14690EJ1V0DS00
µPD78F9136A
APPENDIX B RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document No.
Document Name
Japanese
U14678J
English
U14678E
µPD789121A, 122A, 124A, 131A, 132A, 134A, 121A(A), 122A(A), 124A(A), 131A(A),
132A(A), 134A(A) Data Sheet
µPD78F9136A Data Sheet
U14690J
U14643J
U11047J
U14458J
This manual
To be prepared
U11047E
µPD789104A, 789114A, 789124A, 789134A Subseries User’s Manual
78K/0S Series User’s Manual Instruction
78K/0, 78K/0S Series Application Note Flash Memory Write
U14458E
Documents Related to Development Tools (User’s Manuals)
Document No.
Japanese English
Document Name
RA78K0S Assembler Package
Operation
U11622J
U11599J
U11623J
U11622E
Assembly Language
U11599E
U11623E
Structured Assembly
Language
CC78K0S C Compiler
Operation
Language
Reference
U11816J
U11817J
U11489J
U10092J
U11816E
U11817E
U11489E
U10092E
SM78K0S System Simulator Windows Based
SM78K Series System Simulator
External Parts User Open
Interface Specifications
ID78K0S-NS Integrated Debugger Windows Based
IE-78K0S-NS In-circuit Emulator
Reference
U12901J
U13549J
U14363J
U12901E
U13549E
U14363E
IE-789136-NS-EM1 Emulation Board
Documents Related to Embedded Software (User’s Manuals)
Document No.
Japanese English
Document Name
78K/0S Series OS MX78K0S
Fundamental
U12938J
U12938E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
43
Data Sheet U14690EJ1V0DS00
µPD78F9136A
Other Related Documents
Document No.
Japanese English
Document Name
SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM)
Semiconductor Device Mounting Technology Manual
X13769X
C10535J
C11531J
C10983J
C11892J
U11416J
C10535E
Quality Grades on NEC Semiconductor Devices
C11531E
C10983E
C11892E
−
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Guide to Microcomputer-Related Products by Third Party
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
44
Data Sheet U14690EJ1V0DS00
µPD78F9136A
[ MEMO ]
45
Data Sheet U14690EJ1V0DS00
µPD78F9136A
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
EEPROM is a trademark of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of SONY Corporation.
46
Data Sheet U14690EJ1V0DS00
µPD78F9136A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Benelux Office
Hong Kong
Eindhoven, The Netherlands
Tel: 040-2445845
Tel: 2886-9318
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 91-504-2787
Fax: 01908-670-290
Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Fax: 02-2719-5951
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Fax: 08-63 80 388
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
47
Data Sheet U14690EJ1V0DS00
µPD78F9136A
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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