UT1553BRTR [ETC]

Remote Terminal with RAM; 与RAM远程终端


型号：	UT1553BRTR
厂家：	ETC
描述：	Remote Terminal with RAM 与RAM远程终端
文件：	总44页 (文件大小：1147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UT1553B RTR Remote Terminal with RAM

Table I of MIL-STD-883, Method 5004, Class B, also

Standard Military Drawing available

FEATURES

❐ Complete MIL-STD-1553B remote terminal interface

❐ Available in 68-pin pingrid array package

❐ 1K x 16 of on-chip static RAM for message data,

completely accessible to host

INTRODUCTION

❐ Self-test capability, including continuous loop-back

The UT1553B RTR is a monolithic CMOS VLSI solution

totherequirementsofthedual-redundantMIL-STD-1553B

interface. Designed to reduce cost and space, the RTR

integrates the remote terminal logic with a user-conﬁgured

1K x 16 static RAM. In addition, the RTR has a ﬂexible

subsystem interface to permit use with most processors or

controllers.

compare

❐ Programmable memory mapping via pointers for

efﬁcient use of internal memory, including buffering

multiple messages per subaddress

❐ RT-RT Terminal Address Compare

❐ Command word stored with incoming data for

enhanced data management

The RTR provides all protocol, data handling, error

checking, and memory control functions, as well as

comprehensive self-test capabilities. The RTR’s memory

meets all of MIL-STD-1553B message storage needs

through user-deﬁned memory mapping. This memory-

mapped architecture allows multiple message buffering at

❐ User selectable RAM Busy (RBUSY) signal for slow

or fast processor interfacing

❐ Full military operating temperature range, -55°C to

+125°C, screened to the speciﬁc test methods listed in

RTA(4:0)

REMOTE TERMINAL

ADDRESS

MCSA(4:0)

MODE CODE/

SUBADDRESS

CONTROL

INPUTS

OUT

STATUS

OUTPUTS

COMMAND

RECOGNITION

CONTROL AND

DECODER

ERROR LOGIC

1K X 16 RAM

ADDR(9:0)

OUT

MUX

PTR REGISTER

ENCODER

12MHz

RESET

DATA(15:0)

2MHz

Figure 1. UT1553B RTR Functional Block Diagram

RTR-1

Table of Contents

1.0 ARCHITECTURE AND OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.1 Memory Map and Host Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.2 RTR RAM Pointer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.3 Internal Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

1.4 Mode Code and Subaddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.5 MIL-STD-1553B Subaddress and Mode Codes . . . . . . . . . . . . . . . . . . . . . . . . .9

1.6 Terminal Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.7 Internal Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.8 Power-up and Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.9 Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.10 RT-RT Transfer Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.11 Illegal Command Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.0

3.0

4.0

5.0

6.0

7.0

MEMORY MAP EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PIN IDENTIFICATION AND DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

MAXIMUM AND RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . 19

DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

AC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PACKAGE OUTLINE DRAWING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

RTR-2

alert the host. The RBUSY signal is programmable via the

internal Control Register to be asserted either 5.7ms or

2.7ms prior to the RTR needing access to its internal RAM.

1.0 ARCHITECTURE AND OPERATION

The UT1553B RTR is an interface device linking a MIL-

STD-1553serialdatabusandahostmicroprocessorsystem.

The RTR’s MIL-STD-1553B interface includes encoding/

decoding logic, error detection, command recognition, 1K

x 16 of SRAM, pointer registers, clock, and reset circuits.

The RTR stores MIL-STD-1553B messages in 1K x 16 of

on-chip RAM. For efﬁcient use of the 1K x 16 memory on

the RTR, the host programs a set of pointers to map where

the 1553B message is stored. The RTR uses the upper 64

words (address 3C0 (hex) through 3FF (hex)) as pointers.

The RTR provides pointers for all 30 receive subaddresses,

all 30 transmit subaddresses, and four mode code

commands with associated data words as deﬁned in MIL-

STD-1553B. The remaining 960 words of memory

contain receive, transmit, and mode code data in a

host-deﬁned structure.

1.1 Memory Map and Host Memory Interface

The host can access the 1K x 16 RAM memory like a

standard RAM device through the 10-bit address and 16-bit

data buses. The host uses the Chip Select (CS), Read/Write

(RD/WR), and Output Enable (OE) signals to control data

transfertoandfrommemory.WhentheRTRrequiresaccess

to its own internal RAM, it asserts the RBUSY signal to

RTR Memory Map

000 (hex)

Message

Storage

Locations

3BF(hex)

15 MSB

0 LSB

XMIT VECTOR WORD MODE CODE (W/DATA)

3C0 (hex)

3C1 (hex)

Receive

Message

Pointers

RCV SUBADDRESS 01

(3C1 TO 3DE)

RCV SUBADDRESS 30

SYNCHRONIZE MODE CODE (W/DATA)

3DE (hex)

3DF (hex)

15 MSB

XMIT LAST COMMAND MODE CODE (W/DATA)

XMT SUBADDRESS 01

3E0 (hex)

3E1 (hex)

Transmit

Message

Pointers

(3E1 TO 3FE)

XMT SUBADDRESS 30

3FE (hex)

3FF (hex)

XMT BIT WORD MODE CODE (W/DATA)

15 MSB

Figure 2. RTR Memory Map

RTR-3

MESSAGE INDEX

15 (MSB)

MESSAGE DATA ADDRESSES

Message Data Address:

0 (LSB)

Message index: Deﬁnes the

maximummessagesbufferedfor

the given subaddresses.

Indicates the starting memory address for incoming

message storage.

Figure 3. Message Pointer Structure

1.2 RTR RAM Pointer Structure

Address Field = 03F (hex)

Index Field = 00 (hex)

The RAM 16-bit pointers have a 6-bit index ﬁeld and a

10-bit address ﬁeld. The 6-bit index ﬁeld allows for the

storage of up to 64 messages per subaddress. A message

consists of the 1553 command word and its associated data

words.

TheTransmit Last Command Mode Code hasAddressField

boundary conditions for the location of command word

buffers. The host can allocate a maximum 63 sequential

locations following the Address Field starting address. For

proper operation, the Address Field must start on an I x 40

(hex) address boundary, where I is greater than or equal to

zero and less than or equal to 14. A list of valid Index and

Address Fields follows:

The 16-bit pointer for Transmit Last Command Mode Code

is located at memory location 3E0 (hex). The Transmit Last

Command Mode Code pointer buffers up to 63 command

words. An example of command word storage follows:

Example:

Valid Index Fields

3F (hex) to 00 (hex)

Valid Address Fields

000 (hex) to 03F (hex)

040 (hex) to 07F (hex)

080 (hex) to 0BF (hex)

0C0 (hex) to 0FF (hex)

100 (hex) to 13F (hex)

140 (hex) to 17F (hex)

180 (hex) to 1BF (hex)

1C0 (hex) to 1FF (hex)

200 (hex) to 23F (hex)

240 (hex) to 27F (hex)

280 (hex) to 2BF (hex)

2C0 (hex) to 2FF (hex

300 (hex) to 33F (hex)

340 (hex) to 37F (hex)

380 (hex) to 3BF (hex)

3E0 (hex)

Contents = FC00 (hex)

11 1111 00 0000 0000

Address Field = 000 (hex)

Index Field = 3F (hex)

First command word storage location (3E0=F801):

Address Field = 001 (hex)

Index Field = 3E (hex)

Sixty-third command word storage location (3E0=003F):

Address Field = 03F (hex)

Index Field = 00 (hex)

Sixty-fourth command word storage location (3E0=003F)

(previous command word overwritten):

10 3F (hex) to 00 (hex)

11 3F (hex) to 00 (hex)

12 3F (hex) to 00 (hex)

13 3F (hex) to 00 (hex)

14 3F (hex) to 00 (hex)

RTR-4

Subaddress/Mode Code

RAM Location Subaddress/Mode Code

Transmit Last Command Mode Code

RAM Location

3E0 (hex)

3E1 (hex)

3E2 (hex)

3E3 (hex)

3E4 (hex)

3E5 (hex)

3E6 (hex)

3E7 (hex)

3E8 (hex)

3E9 (hex)

3EA (hex)

3EB (hex)

3EC (hex)

3ED (hex)

3EE (hex)

3EF (hex)

3F0 (hex)

3F1 (hex)

3F2 (hex)

3F3 (hex)

3F4 (hex)

3F5 (hex)

3F6 (hex)

3F7 (hex)

3F8 (hex)

3F9 (hex)

3FA (hex)

3FB (hex)

3FC (hex)

3FD (hex)

3FE (hex)

3FF (hex)

Transmit Vector Word Mode Code

3C0 (hex)

3C1 (hex)

3C2 (hex)

3C3 (hex)

3C4 (hex)

3C5 (hex)

3C6 (hex)

3C7 (hex)

3C8 (hex)

3C9 (hex)

3CA (hex)

3CB (hex)

3CC (hex)

3CD (hex)

3CE (hex)

3CF (hex)

3D0 (hex)

3D1 (hex)

3D2 (hex)

3D3 (hex)

3D4 (hex)

3D5 (hex)

3D6 (hex)

3D7 (hex)

3D8 (hex)

3D9 (hex)

3DA (hex)

3DB (hex)

3DC (hex)

3DD (hex)

3DE (hex)

3DF (hex)

Receive Subaddress

Transmit Subaddress

Transmit Bit Word Mode Code

Synchronize w/Data Word Mode Code

1.3 Internal Registers

The Control Register toggles bits in the MIL-STD-1553B

status word, enables the biphase inputs, recognizes

broadcast commands, determines RAM Busy (RBUSY)

timing, selects terminal active ﬂag, and puts the part in self-

test mode. The Status Register supplies operational status

of the UT1553B RTR to the host. These registers must be

initialized before attempting RTR operation. Internal

registers can be accessed while RBUSY is active.

The RTR uses two internal registers to allow the host to

control the RTR operation and monitor its status. The host

usestheControl(CTRL)signalalongwithChipSelect(CS),

Read/Write (RD/WR), and Output Enable (OE) to read the

16-bitStatusRegisterorwritetothe11-bitControlRegister.

No address data is needed to select a register.

RTR-5

Control Register (Write Only)

The 11-bit write-only Control Register manages the operation of the RTR. Write to the Control Register by applying a logic

one to OE, and a logic zero to CTRL, CS, and RD/WR. Data is loaded into the Control Register via I/O pins DATA(12:0).

Control register write must occur 50ns before the rising edge of COMSTR to latch data into outgoing status word.

Bit

Initial

Number

Condition

Description

Bit 0

Bit 1

Bit 2

[1]

[0]

Channel A Enable. A logic 1 enables Channel A biphase inputs.

Channel B Enable. A logic 1 enables Channel B biphase inputs.

Terminal Flag. A logic 1 sets the Terminal Flag bit of the Status Word.

System Busy. A logic 1 sets the Busy bit of the Status Word and limits RTR access to the

memory. No data words can be retrieved or stored; command words will be stored.

Bit 3

Bit 4

Bit 5

[1]

[0]

Subsystem Busy. A logic 1 sets the Subsystem Flag bit of the Status Word.

Self-Test Channel Select. This bit selects which channel the self-test checks; a logic 1 selects

Channel A and a logic 0 selects Channel B.

Self-Test Enable. A logic 1 places the RTR in the internal self-test mode and inhibits normal

operation. Channels A and B should be disabled if self-test is chosen.

Bit 6

[0]

Bit 7

[0]

[1]

[X]

Service Request. A logic 1 sets the Service Request bit of the Status Word.

Instrumentation. A logic 1 sets the Instrumentation bit of the Status Word.

Broadcast Enable. A logic 1 enables the RTR to recognize broadcast commands.

Don’t care.

Bit 8

Bit 9

Bit 10

Bit 11

Don’t care.

RBUSY Time Select. A logic 1 selects a 5.7µs RBUSY alert; a logic 0 selects a 2.7µs

RBUSY alert.

Bit 12

[1]

[] - Values in parentheses indicate the initialized values of these bits.

CONTROL REGISTER (WRITE ONLY):

RBUSY

BCEN INS SRQ ITST

ITCS SUBS BUSY TF CH B CH A

[1]

[1] [0] [0] [0]

[0]

[1]

[0]

[1]

MSB

LSB

[ ] deﬁnes reset state

X don’t care

Figure 4a. Control Register

RTR-6

Status Register (Read Only)

The 16-bit read-only Status Register provides the RTR system status. Read the Status Register by applying a logic

0 to CTRL, CS, and OE, and a logic 1 to RD/WR. The 16-bit contents of the Status Register are read from data

I/O pins DATA(15:0).

Bit

Initial

Number

Condition

Description

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

[0]

MCSA0. The LSB of the mode code or subaddress as indicated by the logic state of bit 5.

MCSA1. Mode code or subaddress as indicated by the logic state of bit 5.

MCSA2. Mode code or subaddress as indicated by the logic state of bit 5.

MCSA3. Mode code or subaddress as indicated by the logic state of bit 5.

MCSA4. Mode code or subaddress as indicated by the logic state of bit 5.

MC/SA. A logic 1 indicates that bits 4 through 0 are the subaddress of the transmit or

receive command. A logic 0 indicates that bits 4 through 0 are a mode code, and that the

last command was a mode command.

Bit 6

[1]

Channel A/B. A logic 1 indicates that the most recent command arrived on Channel A; a

logic 0 indicates that it arrived on Channel B.

Bit 7

Bit 8

[1]

Channel B Enabled. A logic 1 indicates that Channel B is available for both

Channel A Enabled. A logic 1 indicates that Channel A is available for both reception

and transmission.

Bit 9

[1]

Terminal Flag Enabled. A logic 1 indicates that the Bus Controller has not Bus Control-

ler, via the above mode code, is overriding the host system’s ability to set the Terminal

Flag bit of the status word.

Bit 10

Busy. A logic 1 indicates the Busy bit is set. This bit is reset when the System Busy bit in

the Control Register is reset.

Bit 11

Bit 12

[0]

Self-Test. A logic 1 indicates that the chip is in the internal self-test mode.

TA Parity Error. A logic 1 indicates the wrong Terminal Address parity; it Error bit being

set to a logic one, and Channels A and B become disabled.

Bit 13

[0]

Message Error. A logic 1 indicates that a message error has occurred since has been

examined. Message error condition must be removed before reading the Status Register

to reset the Message Error bit.

Bit 14

Bit 15

[0]

Valid Message. A logic 1 indicates that a valid message has been received

Terminal Active. A logic 1 indicates the device is executing a transmit or

[] - Values in parentheses indicate the initialized values of these bits.

STATUS REGISTER (READ ONLY):

TERM VAL MESS TAPA SELF BUSY TFEN CH A CH B CHNL MC/ MCSA MCSA MCSA MCSA MCSA

ACTV MESS ERR ERR TEST

A/B SA

[0]

[1]

[1] [0]

[0]

MSB

LSB

[] deﬁnes reset state

Figure 4b. Status Register

RTR-7

1.4 Mode Code and Subaddress

contain the same information as pins MCSA(4:0) and MC/

SA.

The UT1553B RTR provides subaddress and mode code

decoding meetingMIL-STD-1553B. Inaddition, the device

has automatic internal illegal command decoding for

reserved MIL-STD-1553B mode codes. Upon command

word validation and decode, status pins MCSA(4:0) and

MC/SA become valid. Status pin MC/SA will indicate

whether the data on pins MCSA(4:0) is mode code or

subaddress information. Status Register bits 0 through 5

The system designer can use signals MCSA(4:0), MC/SA,

BRDCST, RTRT, etc. to illegalize mode codes,

subaddresses, and other message formats (broadcast and

RT-to-RT) via the Illegal Command (ILLCOM) input to the

part (see ﬁgure 21 on page 31).

RTR MODE CODE HANDLING PROCEDURE

T/R

Mode Code

Function

Operation

1. Command word stored

2. MERR pin asserted

3. MERR bit set in Status Register

4. Status word transmitted

Selected Transmitter Shutdown

10100

1. Command word stored

Override Selected Transmitter Shutdown

Synchronize (w/Data)

10101

2. MERR pin asserted

3. MERR bit set in Status Register

4. Status word transmitted

1. Command word stored

2. Data word stored

3. Status word transmitted

1. Command word stored

2. MERR pin asserted

3. MERR bit set in Status Register

4. Status word transmitted

10001

00000

Dynamic Bus Control

1. Command word stored

2. Status word transmitted

1. Command word stored

2. Status word transmitted

1. Command word stored

2. Status word transmitted

1. Command word stored

2. Alternate bus shutdown

3. Status word transmitted

Synchronize

00001

00010

00011

00100

Transmit Status Word

Initiate Self-Test

Transmitter Shutdown

1. Command word stored

2. Alternate bus enabled

3. Status word transmitted

1. Command word stored

2. Terminal Flag bit set to zero and disabled

3. Status word transmitted

Override Transmitter Shutdown

Inhibit Terminal Flag Bit

Override Inhibit Terminal Flag

00101

00110

00111

1. Command word stored

2. Terminal Flag bit enabled, but not

set to logic one

3. Status word transmitted

1. Command word stored

2. Status word transmitted

1. Command word transmitted

2. Last command word transmitted

1. Command word stored

2. Status word transmitted

3. Data word transmitted

1. Command word stored

2. Status word transmitted

3. Data word transmitted

Reset Remote Terminal

01000

10010

10000

Transmit Last Command Word

Transmit Vector Word

Transmit BIT Word

10011

Notes:

1. Further host interaction required for mode code operation

2. Reserved mode code; A) MERR pin asserted, B) MESS ERR bit set, C) status word transmitted (ME bit set to logic one).

3. Status word not affected.

4. Undeﬁned mode codes are treated as reserved mode codes.

RTR-8

1.5 MIL-STD-1553B Subaddress and Mode Code Deﬁnitions

Table 1: Subaddress and Mode Code Definitions Per MIL-STD-1553B

Subaddress Field

Binary (Decimal)

Message Format

Description

Receive

Transmit

00000 (00)

00001 (01)

00010 (02)

00011 (03)

00100 (04)

00101 (05)

00110 (06)

00111 (07)

01000 (08)

01001 (09)

01010 (10)

01011 (11)

01100 (12)

01101 (13)

01110 (14)

01111 (15)

10000 (16)

10001 (17)

10010 (18)

10011 (19)

10100 (20)

10101 (21)

10110 (22)

10111 (23)

11000 (24)

11001 (25

11010 (26)

11011 (27)

11100 (28)

11101 (29)

11110 (30)

11111 (31)

Notes:

Mode Code Indicator

User Defined

Mode Code Indicator

1. Refer to mode code assignments per MIL-STD-1553B

1.6 Terminal Address

indicates incorrect Terminal Address parity. An

example follows:

The Terminal Address of the RTR is programmed via ﬁve

input pins: RTA(4:0) and RTPTY. Asserting MRST latches

the RTR’s TerminalAddress from pins RTA(4:0) and parity

bit RTPTY. The address and parity cannot change until the

next assertion of the MRST. The parity of the Terminal

Address is odd; input pin RTPTY is set to a logic state to

satisfy this requirement. A logic 1 on Status Register bit 12

RTA(4:0) = 05 (hex) = 00101

RTPTY = 1 (hex) = 1

Sum of 1’s = 3 (odd), Status Register bit 12 = 0

RTA(4:0) = 04 (hex) = 00100

RTPTY = 0 (hex) = 0

Sum of 1’s = 1 (odd), Status Register bit 12 = 0

RTR-9

RTA(4:0) = 04 (hex) = 00100

power-up if the terminal address parity (odd) is incorrect,

the biphase inputs are disabled and the message error pin

(MERR) is asserted. This condition can also be monitored

via bit 12 of the Status Register. The MERR pin is negated

on reception of ﬁrst valid command.

RTPTY = 1 (hex) = 1

Sum of 1’s = 2 (even), Status Register bit 12 = 1

The RTR checks the TerminalAddress and parity on Master

Reset.WithBroadcastdisabled, RTA(4:0)=11111operates

as a normal RT address.

1.9 Encoder and Decoder

The RTR interfaces directly to a bus transmitter/ receiver

via the RTR Manchester II encoder/decoder. The UT1553B

RTR receives the command word from the MIL-STD-

1553B bus and processes it either by the primary or

secondarydecoder. Eachdecoderchecksforthepropersync

pulseandManchesterwaveform,edgeskew,correctnumber

of bits, and parity. If the command is a receive command,

the RTR processes each incoming data word for correct

format and checks the control logic for correct word count

and contiguous data. If an invalid message error is detected,

the message error pinisasserted, the RTR ceasesprocessing

the remainder (if any) of the message, and it then suppresses

status word transmission. Upon command validation

recognition, the external status outputs are enabled.

Reception of illegal commands does not suppress status

word transmission.

1.7 Internal Self-Test

Setting bit 6 of the Control Register to a logic one enables

the internal self-test. Disable ChannelsA and B at this time

to prevent bus activity during self-test by setting bits 0 and

1 of the Control Register to a logic zero. Normal operation

is inhibited when internal self-test is enabled. The self-test

capability of the RTR is based on the fact that the MIL-STD-

1553B status word sync pulse is identical to the command

word sync pulse. Thus, if the status word from the encoder

is fed back to the decoder, the RTR will recognize the

incoming status word as a command word and thus cause

the RTR to transmit another status word. After the host

invokesself-test, theRTRself-testlogicforcesastatusword

transmission even though the RTR has not received a valid

command. The status word is sent to decoder A or B

depending on the channel the host selected for self-test. The

self-test is controlled by the host periodically changing the

bit patterns in the status word being transmitted. Writing to

the Control Register bits 2, 3, 4, 7, and 8 changes the status

word. Monitor the self-test by sampling either the Status

(COMSTR), Transmit/Receive (T/R)). For more detailed

explanation of internal self-test, consult UTMC publication

RTR/RTS Internal Self-Test Routine.

The RTR automatically compares the transmitted word

(encoder word) to the reﬂected decoder word by way of the

continuous loop-back feature. If the encoder word and

reﬂected word do not match, the transmitter error pin

(TXERR) is asserted. In addition to the loop-back compare

test, a timer precludes a transmission greater than 760µs by

the assertion of Fail-safe Timer (TIMERON). This timer is

reset upon receipt of another command.

1.8 Power-up and Master Reset

1.10 RT-RT Transfer Compare

After power-up, reset initializes the part with its biphase

ports enabled, latches the Terminal Address, and turns on

the busy option. The device is ready to accept commands

from the MIL-STD-1553B bus. The busy ﬂag is asserted

whilethehostisloadingthemessagepointersandmessages.

After this task is completed, the host removes the busy

condition via a Control Register write to the RTR. On

The RT-to-RT TerminalAddress compare logic makes sure

that the incoming status word’s Terminal Address matches

the TerminalAddress of the transmitting RT speciﬁed in the

command word. An incorrect match results in setting the

MessageErrorbitandsuppressingtransmissionofthestatus

word. (RT-to-RT transfer time-out = 54µs)

RTR-10

1.11 Illegal Command Decoding

2.0 MEMORY MAP EXAMPLE

The host has the option of asserting the ILLCOM pin to

illegalize a received command word. On receipt of an illegal

command, the RTR sets the Message Error bit in the status

word, sets the message error output, and sets the message

error latch in the Status Register.

Figures 5 and 6 illustrate the UT1553B RTR buffering three

receive command messages to Subaddress 4. The receive

message pointer for Subaddress 4 is located at 03C4 (hex)

in the 1K x 16 RAM. The 16-bit contents of location 03C4

(hex) point to the memory location where the ﬁrst receive

message is stored. The Address Field deﬁned as bits 0

through 9 of address 03C4 (hex) contain address

information. The Index Field deﬁned as bits 10 through 15

ofaddress03C4(hex)containthemessagebufferindex(i.e.,

number of messages buffered).

The following RTR outputs may be used to externally

decode an illegal command, Mode Code or Subaddress

indicator (MC/SA), Mode Code or Subaddress bus

MCSA(4:0), Command Strobe (COMSTR), Broadcast

(BRDCST), and Remote Terminal to Remote Terminal

transfer (RTRT) (see ﬁgure 21 on page 31).

Figure 5 demonstrates the updating of the message pointer

aseachmessageisreceivedandstored.Thememorystorage

of these three messages is shown in ﬁgure 6.After receiving

the third message for Subaddress 4 (i.e., Index Field equals

zero) the Address Field of the message pointer is not

incremented. Ifthehostdoesnotupdatethereceivemessage

pointer for Subaddress 4 before the next receive command

for Subaddress 4 is accepted, the third message will

be overwritten.

To illegalize a transmit command, the ILLCOM pin must

be asserted within 3.3µs after VALMSG goes to a logic 1 if

the RTR is to respond with the Message Error bit of the

status word at a logic 1. If the illegal command is mode code

2, 4, 5, 6, 7, or 18, the ILLCOM pin must be asserted within

664ns after Command Strobe (COMSTR) transitions to

logic0.AssertingtheILLCOMpinwithinthe664nsinhibits

themodecodefunction. Formodecodeillegalization, assert

the ILLCOM pin until the VALMSG signal is asserted.

Figures 7 and 8 show an example of multiple message

retrieval from Subaddress 16 upon reception of a MIL-STD-

1553Btransmitcommand.Themessagepointerfortransmit

Subaddress 16 is located at 03F0 (hex) in the 1K x 16 RAM.

The 16-bit contents of location 03F0 (hex) point to the

memory location where the ﬁrst message data words

are stored.

Foranillegalreceivecommand,theILLCOMpinisasserted

within 18.2µs after the COMSTR transitions to a logic 0 in

order to suppress data words from being stored. In addition,

the ILLCOM pin must be at a logic 1 throughout the

reception of the message until VALMSG is asserted. This

does not apply to illegal transmit commands since the status

word is transmitted ﬁrst.

Figure 7 demonstrates the updating of the message pointer

as each message is received and stored. The data memory

for these three messages is shown in ﬁgure 8.

The above timing conditions also apply when the host

externally decodes an illegal broadcast command. The host

must remove the illegal command condition so that the next

command is not falsely decoded as illegal.

RTR-11

Example:

Remote terminal will receive and buffer three MIL-STD-1553 receive commands of various word

lengths to Subaddress 4.

MIL-STD-1553 Bus Activity:

DW0 DW1 DW2 DW3

CMD WORD #1

SA = 4

CMD WORD #2 DW0DW1

T/R = 0

WC = 4

SA = 4

T/R = 0

WC = 2

DW2

CMD WORD #3 DW0 DW1

DW3

SA = 4

T/R = 0

WC = 4

Receive Subaddress 4;

data pointer at 03C4

(hex). (Initial condition)

After message #1,

4 data words plus

command word.

After message #2,

2 data words plus

command word.

After message #3,

4 data words plus

command word.

INDEX= 0000 10

ADDRESS= 00 0100 0000

03C4 (hex)

0840 (hex)

0445 (hex)

0048 (hex)

INDEX= 0000 01

ADDRESS= 00 0100 0101

INDEX= 0000 00

ADDRESS= 00 0100 1000

INDEX= 0000 00

ADDRESS= 00 0100 1000

Figure 5. RTR Message Handling

03C4 (hex)

0840 (hex)

COMMAND WORD #1

DATA WORD 0

040 (hex)

041 (hex)

042 (hex)

043 (hex)

044 (hex)

045 (hex)

046 (hex)

047 (hex)

048 (hex)

049 (hex)

04A (hex)

04B (hex)

04C (hex)

DATA WORD 1

DATA WORD 2

DATA WORD 3

03C4 (hex)

0445 (hex)

0048 (hex)

COMMAND WORD #2

DATA WORD 0

DATA WORD 1

COMMAND WORD #3

DATA WORD 0

DATA WORD 1

DATA WORD 2

DATA WORD 3

03C4 (hex)

0048 (hex)

Figure 6. Memory Storage Subaddress 4

RTR-12

Example:

Remote terminal will transmit and buffer three MIL-STD-1553 transmit commands of various word lengths to

Subaddress 16.

MIL-STD-1553 Bus Activity:

CMD WORD #1 SW

DW2

DW3

DW0 DW1

SA= 16

CMD WORD #2 SW DW0 DW1

SA= 16

T/R=1

WC= 4

DW2 DW3

DW0 DW1

CMD WORD #3 SW

T/R=1

WC= 2

SA= 16

T/R=1

WC= 4

Transmit Subaddress 16; 03F0 (hex)

data pointer at 03F0

(hex). (Initial condition)

0830 (hex)

INDEX= 0000 10

ADDRESS= 00 0011 0000

After message #1,

4 data words.

03F0 (hex)

0434 (hex)

INDEX= 0000 01

ADDRESS= 00 0011 0100

After message #2,

2 data words.

03F0 (hex)

0036 (hex)

INDEX= 0000 00

ADDRESS= 00 0011 0110

After message #3,

4 data words.

INDEX= 0000 00

ADDRESS= 00 0011 0110

Figure 7. RTR Message Handling

DATA WORD 0

DATA WORD 1

DATA WORD 2

DATA WORD 3

DATA WORD 0

DATA WORD 1

DATA WORD 0

DATA WORD 1

DATA WORD 2

DATA WORD 3

0830 (hex)

030 (hex)

031 (hex)

032 (hex)

033 (hex)

034 (hex)

035 (hex)

036 (hex)

037 (hex)

038 (hex)

039 (hex)

0434 (hex)

0036 (hex)

030436(h(hexe)x)

Note:

The example is valid only if message structure is known in advance.

Figure 8. Memory Storage Subaddress 16

RTR-13

3.0 PIN IDENTIFICATION AND DESCRIPTION

BIPHASE OUT

TAZ

TAO

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDRESS

BUS

ADDR(9:0)

A10

B10

TBZ

TBO

BIPHASE IN

RAZ

RAO

RBZ

RBO

TERMINAL

ADDRESS

RTA0

RTA1

RTA2

RTA3

RTA4

RTPTY

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

DATA BUS

DATA(15:0)

L10

K10

K11

J10

J11

H10

H11

G10

F11

E10

E11

D10

D11

C10

C11

B11

MODE/CODE

SUBADDRESS

MCSA0

MCSA1

MCSA2

MCSA3

MCSA4

UT1553B

RTR

STATUS

SIGNALS

MERR

TERACT

TXERR

TIMERON

COMSTR

MC/SA

BRDCST

T/R

F10

POWER

RTRT

GROUND

G11

VALMSG

RBUSY

12MHZ

2MHZ

CLOCK

RES

CONTROL

SIGNALS

RD/WR

CTRL

MRST

ILLCOM

Figure 9. UT1553B RTR Pin Description

RTR-14

Legend for TYPE and ACTIVE ﬁelds:

TTO = Three-state TTL output

TTB = Three-state TTL bidirectional

AL = Active low

TI = TTL input

TUI = TTL input (pull-up)

TDI = TTL input (pull-down)

TO = TTL output

AH = Active high

[] - Value in parentheses indicates initial state of pins.

DATA BUS

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

DATA15

DATA14

DATA13

DATA12

DATA11

DATA10

DATA9

DATA8

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

B11

C11

C10

D11

D10

E11

E10

F11

G10

H11

H10

J11

TTB

Bit 15 (MSB) of the bidirectional Data bus.

Bit 14 of the bidirectional Data bus.

Bit 13 of the bidirectional Data bus.

Bit 12 of the bidirectional Data bus.

Bit 11 of the bidirectional Data bus.

Bit 10 of the bidirectional Data bus.

Bit 9 of the bidirectional Data bus.

Bit 8 of the bidirectional Data bus.

Bit 7 of the bidirectional Data bus.

Bit 6 of the bidirectional Data bus.

Bit 5 of the bidirectional Data bus.

Bit 4 of the bidirectional Data bus.

Bit 3 of the bidirectional Data bus.

Bit 2 of the bidirectional Data bus.

Bit 1 of the bidirectional Data bus.

Bit 0 (LSB) of the bidirectional Data bus.

J10

K11

K10

L10

ADDRESS BUS

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

ADDR9

ADDR8

ADDR7

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

Bit 9 (MSB) of the Address bus.

Bit 8 of the Address bus.

Bit 7 of the Address bus.

Bit 6 of the Address bus.

Bit 5 of the Address bus.

Bit 4 of the Address bus.

Bit 3 of the Address bus.

Bit 2 of the Address bus.

Bit 1 of the Address bus.

Bit 0 (LSB) of the Address bus.

RTR-15

CONTROL INPUTS

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

Chip Select. The host processor uses the CS signal for RTR

Status Register reads, Control Register writes, or host

access to the RTR internal RAM.

RD/WR

Read/Write. The host processor uses a high level on this

input in conjunction with CS to read the RTR Status

input is used in conjunction with CS to write to the RTR

Control Register or the RTR internal RAM.

CTRL

Control. The host processor uses the active low CTRL

input signal in conjunction with CS and

RD/WR to access the RTR registers. A high level on this

input means access is to RTR internal RAM only.

Output Enable. The active low OE signal is used to control

the direction of data ﬂow from the RTR. For OE = 1, the

RTR Data bus is three-state; for

OE = 0, the RTR Data bus is active.

ILLCOM

TDI

Illegal Command. The host processor uses the

ILLCOM input to inform the RTR that the present

command is illegal.

STATUS INPUTS

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

MERR

[0]

Message Error. The active high MERR output

signals that the Message Error bit in the Status

or an error during message sequence. MERR will reset to

logic zero on the receipt of the next valid command.

TXERR

[0]

Transmission Error. The active high TXERR output is

asserted when the RTR detects an error in the reﬂected

word versus the transmitted word, using the continuous

loop-back compare feature. Reset on next COMSTR

assertion.

TIMERON

[1]

Fail-safe Timer. The TIMERON output pulses low for

760µs when the RTR begins transmitting (i.e., rising edge

of VALMSG) to provide a fail-safe timer meeting the

requirements of MIL-STD-1553B. This pulse is reset when

COMSTR goes low or during a Master Reset.

COMSTR

[1]

Command Strobe. COMSTR is an active low output of

500ns duration identifying receipt of a valid command.

TERACT

Terminal Active. The active low TERACT output is

asserted at the beginning of the RTR access to internal

RAM for a given command and negated after the last

access for that command.

RTR-16

STATUS INPUTS

Continued from page 16.

NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

(PGA)

Broadcast. BRDCST is an active low output that identiﬁes

receipt of a valid broadcast command.

BRDCST

[1]

Transmit/Receive. A high level on this pin indicates a

transmit command message transfer is being or was

processed, while a low level indicates a receive command

message transfer is being or was processed.

T/R

[0]

Valid Message. VALMSG is an active high output

indicating a valid message (including Broadcast) has been

received. VALMSG goes high prior to transmitting the

1553 status word and is reset upon receipt of the next

command.

RTRT

[1]

RTR Busy. RBUSY is asserted high while the RTR is

accessing its own internal RAM either to read or update the

pointers or to store or retrieve data words. RBUSY

becomes active either 2.7µs or 5.7µs before RTR requires

RAM access. This timing is controlled by Control Register

bit 12 (see section 1.3).

RBUSY

[0]

MODE CODE/SUBADDRESS OUTPUTS

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

Mode Code/Subaddress Indicator. If MC/SA is low, it

indicates that the most recent command word is a mode

code command. If MC/SA is high, it indicates that the most

recent command word is for a subaddress. This output

indicates whether the mode code/subaddress ouputs (i.e.,

MCSA(4:0)) contain mode code or subaddress

information.

MC/SA

[0]

Mode Code/Subaddress Output 0. If MC/SA is low, this

pin represents the least signiﬁcant bit of the most recent

command word (the LSB of the mode code). If MC/SA is

high, this pin represents the LSB of the subaddress.

MCSA0

[0]

Mode Code/Subaddress Output 1.

Mode Code/Subaddress Output 2.

Mode Code/Subaddress Output 3.

MCSA1

[0]

MCSA2

[0]

MCSA3

[0]

Mode Code/Subaddress Output 4. If MC/SA is low, this

pin represents the most signiﬁcant bit of the mode code. If

MC/SA is high, this pin represents the MSB of the

subaddress.

MCSA4

[0]

RTR-17

REMOTE TERMINAL ADDRESS INPUTS

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

Remote Terminal Address bit 4 (MSB).

Remote Terminal Address bit 3.

Remote Terminal Address bit 2.

Remote Terminal Address bit 1.

Remote Terminal Address bit 0 (LSB).

RTA4

RTA3

RTA2

RTA1

RTA0

RTPTY

TUI

Remote Terminal Address Parity. This input must provide

odd parity for the Remote Terminal Address.

BIPHASE INPUTS

NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

(PGA)

Receiver - Channel A, Zero Input. Idle low Manchester

input form the 1553 bus receiver.

RAZ

RAO

RBZ

RBO

Receiver - Channel A, One Input. This input is the

complement of RAZ.

Receiver - Channel B, Zero Input. Idle low Manchester

input from the 1553 bus receiver.

Receiver - Channel B, One Input. This input is the

complement of RBZ.

Note:

1. For uniphase operation, tie RAZ (or RBZ) to V_DDand apply true uniphase input signal to RAO (or RBO).

BIPHASE OUTPUTS

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

Transmitter - Channel A, Zero Output. This idle low

Manchester encoded data output is connected to the 1553

bus transmitter input. The output is idle low.

A10

TAZ

[0]

Transmitter - Channel A, One Output. This output is the

complement of TAZ. The output is idle low.

B10

TAO

[0]

Transmitter - Channel B, Zero Output. This idle low

Manchester encoded data output is connected to the 1553

bus transmitter input. The output is idle low.

TBZ

[0]

Transmitter - Channel B, One Output. This input is the

complement of TBZ. The output is idle low.

TBO

[0]

RTR-18

MASTER RESET AND CLOCK

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

MRST

TUI

Master Reset. Initializes all internal functions of the RTR.

MRST must be asserted 500ns before normal RTR

operation (500ns minimum). Does not reset RAM.

12MHz

2MHz

12 MHz Input Clock. This is the RTR system clock that

requires an accuracy greater than 0.01% with a duty cycle

of 50% ± 10%.

2MHz Clock Output. This is a 2MHz clock output

generated by the 12MHz input clock. This clock is stopped

when MRST is low.

POWER AND GROUND

NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

(PGA)

VDD

+5 V Power. Power supply must be +5 V

± 10%.

F10

PWR

VSS

Reference ground. Zero V logic ground.

G11

GND

4.0 OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS*

(referenced to V

)

SYMBOL

PARAMETER

DC supply voltage

LIMITS

UNIT

-0.3 to +7.0

Voltage on any pin

DC input current

Storage temperature

0.3 to V +0.3

±10

°C

-65 to +150

300

STG

Maximum power dissipation

Maximum junction temperature

+175

°C

Thermal resistance, junction-to-case

°C/W

Note:

1. Does not reﬂect the added P_Ddue to an output short-circuited.

Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and

functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this speciﬁcation

is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

DC supply voltage

LIMITS

4.5 to 5.5

0 to V

UNIT

DC input voltage

Temperature range

Operating frequency

-55 to +125

12 ± .01%

°C

MHz

RTR-19

5.0 DC ELECTRICAL CHARACTERISTICS

(V_DD= 5.0V ±10%; -55°C < T_C< +125°C)

SYMBOL

PARAMETER

Low-level input voltage

High-level input voltage

CONDITION

MINIMUM

MAXIMUM

UNIT

0.8

2.0

Input leakage current

TTL inputs

Inputs with pull-down resistors

Inputs with pull-up resistors

= V or V

DD SS

-1

1110

-2000

µA

= V

-2000

-110

Low-level output voltage

= 3.2mA

0.4

High-level output voltage

Three-state output

leakage current

= -400µA

O DD SS

2.4

-10

+10

µA

V = V or V

1, 2

Short-circuit output current

= 5.5V, V = V

DD O DD

-90

= 5.5V V = 0V

Input capacitance

ƒ = 1MHz @ 0V

Output capacitance

ƒ = 1MHz @ 0V

OUT

Bidirect I/O capacitance

1, 4

Average operating current

ƒ = 12MHz, CL = 50pF

Note 5

Quiescent current

1.5

Notes:

1. Supplied as a design limit but not guaranteed or tested.

2. Not more than one output may be shorted at a time for a maximum duration of one second.

3. Measured only for initial qualiﬁcation, and after process or design changes that could affect input/output capacitance.

4. Includes current through input pull-ups. Instantaneous surge currents on the order of 1 ampere can occur during output switching.

Voltage supply should be adequately sized and decoupled to handle a large surge current.

5. All inputs with internal pull-ups or pull-downs should be left open circuit. All other inputs tied high or low.

BIT TIMES

1 2 3

4 5 6 7 8

10 11 12 13 14

15 16 17 18 19

COMMAND

WORD

T/R

DATA WORD COUNT/

MODE CODE

SYNC REMOTE TERMINAL

ADDRESS

SUBADDRESS/MODE

CODE

DATA WORD

SYNC

DATA

STATUS WORD

REMOTE TERMINAL

SYNC

ADDRESS

Figure 10. MIL-STD-1553B Word Formats

RTR-20

6.0 AC ELECTRICAL CHARACTERISTICS

(Over recommended operating conditions)

VIH MIN

VIL MAX

MIN

MAX

INPUT

VOH MIN

VOL MAX

IN-PHASE

OUTPUT

OUT-OF-PHASE

OUTPUT

VOH MIN

VOL MAX

VOH MIN

VOL MAX

BUS

SYMBOL

PARAMETER

INPUT to response

↑

↓

^{INPUT to response}↓

↓

^INPUT↑^{to response}

↓

↑

INPUT to response

↓

INPUT to data valid

↓

INPUT to high Z

↓

^INPUT↑ ^{to high Z}

INPUT to data valid

↑

Notes:

1. Timing measurements made at (V MIN + V MAX)/2.

MAX + V

2. Timing measurements made at (V

3. Based on 50pF load.

MIN)/2.

4. Unless otherwise noted, all AC electrical characteristics are guaranteed by design or characterization.

Figure 11a. Typical Timing Measurements

(source)

REF

90%

REF

10%

50pF

< 2ns

(sink)

REF

Input Pulses

Note:

50pF including scope probe and test socket

Figure 11b. AC Test Loads and Input Waveforms

RTR-21

12MHz

12i

12j

12a

12b

12c

12f

CTRL

RD/WR

12k

12g

ADDR(9:0)

12d

12l

DATA(15:0)

DATA VALID

12h

12e

12m

Figure 12. Microprocessor RAM Read

SYMBOL

PARAMETER

MIN

MAX

UNITS

CTRL↑ set up wrt CS↓

12a

12b

12c

12d

12e

12f

RD/WR ↑ set up wrt CS↓

ADDR(9:0) Valid to CS↓ (Address Set up)

CS↓ to DATA(15:0) Valid

155

OE↓ to DATA(15:0) Don’t Care (Active)

CS↑ to CTRL Don’t Care

CS↑ to ADDR(9:0) Don’t Care

OE↑ to DATA(15:0) High Impedance

12g

12h

12i

5500

CS↓ to CS↑

220

CS↑ to CS↓

12j

CS↑ to RD/WR Don’t Care

12k

12l

CS↑ to DATA(15:0) Invalid

OE↓ to OE↑

12m

Notes:

1. “wrt” deﬁned as “with respect to.”

2. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7µs RBUSY option. For the 2.7µs

RBUSY option, the maximum CS low time is 2500ns.

3. Assumes OE is asserted.

RTR-22

12MHz

13i

13j

13a

13k

CTRL

13b

RD/WR

ADDR(9:0)

DATA(15:0)

13f

13c

13d

13g

13h

VALID DATA

13e

Figure 13. Microprocessor RAM Write

SYMBOL

PARAMETER

MIN

MAX

UNITS

CTRL↑ set up wrt CS↓

13a

RD/WR↓ set up wrt CS↓

13b

13c

13d

13e

13f

ADDR(9:0) Valid to CS↓(Address set up)

DATA(15:0) Valid to CS↓(DATA set up)

OE↑ to DATA(15:0) High Impedance

CS↑ to RD/WR Don’t Care

CS↑ to ADDR(9:0) Don’t Care

13g

13h

13i

CS↑ to DATA(15:0) Don’t Care (Hold-time)

180

CS↓ to CS↑

5500

CS↑ to CS↓

13j

CS↑ to CTRL Don’t Care

13k

Note:

1. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7ms RBUSY option. For the 2.7ms

RBUSY option, the maximum CS low time is 2500ns.

RTR-23

12MHz

14c

14a

14e

CTRL

14b

RD/WR

14f

14h

DATA(15:0)

VALID DATA

14d

14g

Figure 14. Control Register Write

SYMBOL

PARAMETER

MIN

MAX

UNITS

CTRL↓ set up wrt CS↓

RD/WR↓ set up wrt CS↓

14a

5500

14b

14c

14d

14e

14f

CS↓ to CS↑

CS↑ to DATA(15:0) Don’t Care (Hold-time)

CS↑ to CTRL Don’t Care

CS↑ to RD/WR Don’t Care

OE↑ to DATA(15:0) High Impedance

DATA(15:0) Valid to CS↓ (DATA set up)

14g

14h

Note:

1. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7µs RBUSY option. For the 2.7µs

RBUSY option, the maximum CS low time is 2500ns.

RTR-24

12MHz

15b

15a

15e

CTRL

15c

RD/WR

DATA(15:0)

15f

15d

15j

VALID DATA

15h

15g

15i

Figure 15. Status Register Read

SYMBOL

PARAMETER

MIN

MAX

UNITS

CTRL↓ set up wrt CS↓

5500

15a

15b

15c

15d

15e

15f

CS↓ to CS↑

RD/WR↑ set up wrt CS↓

CS↓ to DATA(15:0) Valid

CS↑ to CTRL Don’t Care

CS↑ to RD/WR Don’t Care

OE↓ to DATA(15:0) Don’t Care (Active)

OE↑ to DATA(15:0) High Impedance

OE↓ to OE↑

15g

15h

15i

CS↓ to DATA(15:0) Don’t Care (Active)

15j

Note:

1. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7ms RBUSY option. For the 2.7ms

RBUSY option, the maximum CS low time is 2500ns.

RTR-25

VALMSG

TIMERON

16a

16c

A/B

BIPHASE

OUTPUT ZERO

16b

COMSTR

ILLCOM

16d

16g

16e

16f

Figure 16. RT Fail-Safe Timer Signal Relationships

SYMBOL

PARAMETER

MIN

MAX

UNITS

VALMSG↑ before TIMERON↓

TIMERON↓ before ﬁrst

BIPHASE OUT O↑

µs

16a

16b

1.2

TIMERON low pulse width (time-out)

727.3

727.4

µs

16c

16d

16e

16f

COMSTR↓ to TIMERON↑

VALMSG↑ to ILLCOM↑

3.3

COMSTR↓ to ILLCOM↑

664

18.2

COMSTR↓ to ILLCOM↑

16f

ILLCOM↑ to ILLCOM↓

500

16g

Notes:

1. Mode code 2, 4, 5, 6, 7, or 18 received.

2. To suppress data word storage.

3. For transmit command illegalization.

RTR-26

12MHz

CS COMMAND WORD

BIPHASE IN

17a

MC/SA

and MCSA(4:0)

17b

17c

17l

COMSTR

BRDCST

T/R

17d

17e

17f

17g

17h

17i

VALMSG

17j

17k

MERR

Note:

1. Measured from the mid-bit parity crossing.

Figure 17. Status Output Timing

SYMBOL

PARAMETER

MIN

MAX

UNITS

12MHz↑ to MC/SA Valid

2.1

2.8

µs

17a

17b

17c

17d

17e

17f

Command Word to MC/SA Valid

12MHz↑ to COMSTR↓

Command Word to COMSTR↓

12MHz↑ to BRDCST↓

3.2

3.7

Command Word to BRDCST↓

12MHz↑ to T/R Valid

2.6

3.2

17g

17h

17i

Command Word to T/R Valid

12MHz↑ to VALMSG↑

2.2

2.7

1, 2, 3

Command Word to VALMSG↑

12MHz↑ to MERR↑

6.2

6.7

17j

17k

17l

COMSTR↓ to COMSTR↑

485

500

Notes:

1. Receive last data word to Valid Message active (VALMSG↑).

2. Transmit command word to Valid Message active (VALMSG↑).

3. Command word measured from mid-bit crossing.

4. Guaranteed by test.

RTR-27

12MHz

CS COMMAND WORD

BIPHASE IN

18a

t_18i

RBUSY

18h

18b

18c

TERACT

18d

18e

RTRT

18f

MRST

18g

Note:

1. Measured from mid-bit parity crossing.

Figure 18. Status Output Timing

SYMBOL

PARAMETER

MIN

MAX

UNITS

12MHz↑ to RBUSY↑

3.2

3.8

µs

18a

18b

18c

18d

18e

18f

Command Word to RBUSY↑

12MHz↑ to TERACT↓

Command Word to TERACT↓

12MHz↑ to RTRT↑

3.1

3.7

Command Word to RTRT↑

21.0

500

22.0

MRST↓ to MRST↑

18g

RBUSY↑ to RBUSY↓ (2.7ms)

(5.7ms)

5.5

8.5

µs

18h

RBUSY↓ to RBUSY↑ (2.7ms)

(5.7ms)

3.10

240

µs

18i

Notes:

1. Guaranteed by test.

2. Command word measured from mid-bit crossing.

RTR-28

BIPHASE IN

COMSTR

DATA WORD

CSCOMMAND WORD DATA WORD P DS

T/R

RBUSY

TERACT

SS STATUS

BIPHASE OUT

VALMSG

Notes:

1. Burst of 5 DMAs: read command pointer, store command word, update command pointer, read data word pointer, store

command word.

2. Burst of 1 DMA: store data word.

3. Burst of 2 DMAs: store data word, update data word pointer.

4.Approximately 560ns per DMA access.

Figure 19a. Receive Command with Two Data Words

BIPHASE IN

CS COMMAND

COMSTR

T/R

RBUSY

TERACT

BIPHASE OUT

VALMSG

SS STATUS

DS DATA

CS = Command sync

SS = Status sync

DS = Data sync

P = Parity

Notes:

1. Burst of 4 DMAs: read command pointer, store command word, update command pointer, read data word pointer.

2. Burst of 1 DMA: read data word.

3. Burst of 2 DMAs: read data word, update data word pointer.

4. Approximately 560ns per DMA access.

Figure 19b. Transmit Command with Two Data Words

RTR-29

ADDR(9:0)

DATA(15:0)

CONTROL

HOST

SUBSYSTEM

UT1553B

RTR

UT63M125

1553 TRANSCEIVER

1553 BUS A

1553 BUS B

Figure 20a. RTR General System Diagram (Idle low interface)

RAO

RXOUT

RAZ

CHANNEL A

RTR

TXINHB

TXIN

TAO

TAZ

TXIN

UTMC

63M125

RXOUT

RBO

RBZ

CHANNEL B

TXINHB

TXIN

CHANNEL B

TBO

TBZ

TXIN

TIMERON

Figure 20b. RTR Transceiver Interface Diagram

RTR-30

MC/SA

MCSA0

MCSA1

MCSA2

MCSA3

MCSA4

ILLEGAL

COMMAND

DECODER

RTR

COMSTR

BRDCST

RTRT

T/R

ILLCOM

Figure 21. Mode Code/Subaddress Illegalization Circuit

RTR-31

Package Selection Guide

Product

RTI RTMP RTR BCRT BCRTM BCRTMP RTS XCVR

24-pin DIP

(single cavity)

36-pin DIP

(dual cavity)

68-pin PGA

84-pin PGA

144-pin PGA

84-lead LCC

36-lead FP

(dual cavity)

(50-mil ctr)

84-lead FP

132-lead FP

NOTE:

1. 84LCC package is not available radiation-hardened.

Packaging-1

0.130 MAX.

1.565 ± 0.025

-A-

0.040 REF.

0.050 ± 0.010

0.080 REF.

(2 Places)

0.130 ±0.010

0.100 REF.

(4 Places)

1.565 ± 0.025

-B-

PIN 1 I.D.

(Geometry Optional)

-C-

(Base Plane)

TOP VIEW

0.100

TYP.

0.018 ± 0.002

0.030 C A

0.010

SIDE VIEW

D1/E1

1.400

4 5 6 7 8 9 10 11 12 13 14 15

PIN 1 I.D.

(Geometry Optional)

0.003 MIN. TYP.

BOTTOM VIEW

Notes:

1. True position applies to pins at base plane (datum C).

2. True position applies at pin tips.

3. All package finishes are per MIL-M-38510.

4. Letter designations are for cross-reference to MIL-M-38510.

144-Pin Pingrid Array

Packaging-2

D/E

0.110

0.006

1.525 ± 0.015 SQ.

D1/E1

0.950 ± 0.015 SQ.

PIN 1 I.D.

(Geometry

Optional)

0.025

SEE DETAIL A

LEAD KOVAR

TOP VIEW

0.005

+ 0.002

- 0.001

0.250

MIN.

REF.

SIDE VIEW

0.005 MIN. TYP.

0.018 MAX. REF.

0.014 MAX. REF.

(At Braze Pads)

DETAIL A

BOTTOM VIEW A-A

Notes:

1. All package finishes are per MIL-M-38510.

2. Letter designations are for cross-reference to MIL-M-38510.

132-Lead Flatpack (25-MIL Lead Spacing)

Packaging-3

0.115 MAX.

D/E

1.150 ± 0.015 SQ.

0.080 ± 0.008

PIN 1 I.D.

(Geometry Optional)

TOP VIEW

SIDE VIEW

L/L1

0.050 ± 0.005 TYP.

0.040 x 45_

REF. (3 Places)

0.025 ± 0.003

0.050

0.015 MIN.

0.020 X 455 REF.

PIN 1 I.D.

(Geometry Optional)

BOTTOM VIEW A-A

Notes:

1. All package finishes are per MIL-M-38510.

2. Letter designations are for cross-reference to MIL-M-38510.

84-LCC

Packaging-4

D/E

1.810 ± 0.015 SQ.

0.110

0.060

D1/E1

1.150 ± 0.012 SQ.

PIN 1 I.D.

(Geometry

Optional)

0.050

0.016 ± 0.002

SEE DETAIL A

LEAD KOVAR

TOP VIEW

0.007 ± 0.001

SIDE VIEW

0.260

MIN.

REF.

0.005 MIN. TYP.

0.018 MAX. REF.

0.014 MAX.

REF.

(At Braze Pads)

DETAIL A

BOTTOM VIEW A-A

Notes:

1. All package finishes are per MIL-M-38510.

2. Letter designations are for cross-reference to MIL-M-38510.

84-Lead Flatpack (50-MIL Lead Spacing)

Packaging-5

0.130 MAX.

-A-

1.100 ± 0.020

0.050 ± 0.010

0.130 ± 0.010

1.100 ± 0.020

PIN 1 I.D.

(Geometry Optional)

-B-

-C-

TOP VIEW

(Base Plane)

0.018 ± 0.002

0.100

TYP.

0.030 C A

0.010

SIDE VIEW

D1/

1.000

8 9 10 11

PIN 1 I.D.

(Geometry Optional)

0.003 MIN.

BOTTOM VIEW A-A

Notes:

1. True position applies to pins at base plane (datum C).

2. True position applies at pin tips.

3. All packages finishes are per MIL-M-38510.

4. Letter designations are for cross-reference to MIL-M-38510.

84-Pin Pingrid Array

Packaging-6

0.130 MAX.

0.050 ± 0.010

-A-

1.100 ± 0.020

0.130 ± 0.010

1.100 ± 0.020

-B-

PIN 1 I.D.

(Geometry Optional)

-C-

(Base Plane)

TOP

0.010 ± 0.002

0.100

0.030

0.010

TYP.

SIDE VIEW

D1/E1

1.00

10 11

PIN 1 I.D.

(Geometry Optional)

0.003 MIN. TYP.

BOTTOM VIEW A-A

Notes:

True position applies to pins at base plane (datum C).

True position applies at pin tips.

3. All packages finishes are per MIL-M-38510.

4. Letterdesignationsareforcross-referencetoMIL-M-38510.

68-Pin Pingrid Array

Packaging-7

0.490

MIN.

0.750 ± 0.015

0.015 ± 0.002

1.800 ± 0.025

0.10

PIN 1 I.D.

(Geometry Optional)

TOP VIEW

+ 0.002

- 0.001

0.008

0.130 MAX.

END VIEW

0.080 ± 0.010

(At Ceramic Body)

Notes:

All package finishes are per MIL-M-38510.

2. It is recommended that package ceramic be mounted to

aheatremovalraillocatedontheprintedcircuitboard.

A thermally conductive material such as MERECO XLN-589 or

equivalent should be used.

3. Letter designations are for cross-reference to MIL-M-38510.

36-Lead Flatpack, Dual Cavity (100-MIL Lead Spacing)

Packaging-8

0.700 + 0.015

0.330

MIN.

0.016 + 0.002

1.000 ± 0.025

0.050

PIN 1 I.D

(Geometry Optional)

TOP

+ 0.002

- 0.001

0.007

0.100 MAX.

0.070 + 0.010

(At Ceramic Body)

END

Notes:

1. All package finishes are per MIL-M-38510.

2. It is recommended that package ceramic be mounted to

a heat removal rail located on the printed circuit board.

A thermally conductive material such as MERECO XLN-589

or equivalent should be used.

3. Letter designations are for cross-reference to MIL-M-38510.

36-Lead Flatpack, Dual Cavity (50-MIL Lead Spacing)

Packaging-9

0.005 MIN.

0.590 ± 0.012

0.005 MAX.

0.100

1.800 ± 0.025

0.018 ± 0.002

PIN 1 I.D.

(Geometry Optional)

L/L1

0.150 MIN.

0.155 MAX.

TOP VIEW

SIDE VIEW

Notes:

1. All package finishes are per MIL-M-38510.

2. It is recommended that package ceramic be mounted to

a heat removal rail located on the printed circuit board.

A thermally conductive material such as MERECO XLN-589

or equivalent should be used.

+ 0.002

0.010

- 0.001

0.600 + 0.010

(At Seating Plane)

3. Letter designations are for cross-reference to MIL-M-38510.

END VIEW

36-Lead Side-Brazed DIP, Dual Cavity

Packaging-10

0.005 MIN.

0.590 ± 0.015

0.005 MAX.

0.100

1.200 ± 0.025

0.018 ± 0.002

L/L1

0.150 MIN.

PIN 1 I.D.

(Geometry Optional)

0.140 MAX.

SIDE VIEW

TOP VIEW

Notes:

1. All package finishes are per MIL-M-38510.

2. It is recommended that package ceramic be mounted to

a heat removal rail located on the printed circuit board.

A thermally conductive material such as MERECO XLN-589 or

equivalent should be used.

+ 0.002

- 0.001

0.010

0.600 + 0.010

(At Seating Plane)

3. Letter designations are for cross-reference to MIL-M-38510.

END VIEW

24-Lead Side-Brazed DIP, Single Cavity

Packaging-11

ORDERING INFORMATION

UT1553B RTR Remote Terminal with RAM: S

5962

Lead Finish:

(A)

(C)

(X)

Solder

Gold

Optional

Case Outline:

(X) 68 pin PGA

Class Designator:

(-) Blank or No field is QML Q

Drawing Number: 8957601

Total Dose:

(-)

None

Federal Stock Class Designator: No options

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).

3. For QML Q product, the Q designator is intentionally left blank in the SMD number (e.g. 5962-8957601XC).

UT1553B RTR Remote Terminal with RAM

No UT Part

Number-

Lead Finish:

(A)

(C)

(X)

Solder

Gold

Optional

Package Type:

(G) 68 pin PGA

UTMC Core Part Number

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).

UT1553BRTR [ETC]

相关型号：

UT1553BRTR-GA

UT1553BRTR-GC

UT1553BRTR-GX

UT1553BRTR-GXA

UT1553BRTR-GXC

UT16N10G-K08-3030-R

UT16N10G-TA3-R

UT16N10G-TN3-R

UT16N10L-K08-3030-R

UT16N10L-TN3-R

UT16RD

UT1701-7