UT61L6416 [ETC]
ASYNCHRONOUS STATIC RAM- High Speed ; 异步静态RAM-高速\n
| 型号： | UT61L6416 |
| 厂家： | 
ETC |
| 描述： | ASYNCHRONOUS STATIC RAM- High Speed
|
| 文件： | 总10页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UTRON
UT61L6416
64K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.1
REVISION HISTORY
REVISION
DESCRIPTION
Date
Preliminary Rev. 0.4 Original.
Preliminary Rev. 0.5
Mar, 2001
Aug 31,2001
1.The symbols CE# and OE# and WE# are revised as.CE and
OE and WE .
2.Separate Industrial and Commercial SPEC.
3.Add access time 15ns range.
4.Delete SOJ package.
1.Revised CMOS low power operating :
Operating current : 195ꢀ150mA (max.)
Standby current : 30mA (max.) ꢀ1mA (Typ.)
2.Revised power supply : 3.0~3.6Vꢀ3.15~3.6V
3.Revised DC CHARACTERISTICE
Rev. 1.0
May 20,2003
I
I
I
I
I
I
I
CC –8ns (max) : 200ꢀ150mA
CC –10ns (max) : 195ꢀ120mA
CC –12ns (max) : 190ꢀ100mA
CC –15ns (max) : 150ꢀ80 mA
SB (max) : 30ꢀ10mA, ISB (typ) : NAꢀ3mA
SB1 (max) : 10ꢀ3mA, ISB1 (typ) : NAꢀ1mA
SB1 (max)<1 mA for special order
4. Add order information for lead free product
Rev. 1.1
Jul 03,2003
℃
℃
1.Add Extended temperature : -20 ~80
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80072
1
UTRON
UT61L6416
64K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.1
FEATURES
GENERAL DESCRIPTION
ꢁFast access time :
8ns for Vcc=3.15V~3.6V
10/12/15ns for Vcc=3.0V~3.6V
ꢁCMOS low power operating :
Operating current : 150mA (max.)
Standby current : 1mA (typ.)
ꢁSingle 3.15~3.6V power supply
ꢁOperating temperature :
The UT61L6416 is a 1,048,576-bit high speed CMOS
static random access memory organized as 65,536
words by 16 bits.
The UT61L6416 operates from a single 3.15 ~ 3.6V
power supply and all inputs and outputs are fully TTL
compatible.
The UT61L6416 is designed for lower and upper byte
℃
℃
℃
Commercial : 0 ~70
℃
access by data byte control.(
)
LB UB
Extended : -20 ~80
ꢁAll TTL compatible inputs and outputs
ꢁFully static operation
ꢁThree state outputs
PIN DESCRIPTION
ꢁData byte control :
(I/O0~I/O7)
LB
SYMBOL
A0 - A15
DESCRIPTION
Address Inputs
(I/O8~I/O15)
UB
Ⅱ
ꢁPackage : 44-pin 400mil TSOP
I/O0 - I/O15
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Lower Byte Control
Upper Byte Control
CE
WE
OE
LB
FUNCTIONAL BLOCK DIAGRAM
×
64K 16 bit
A0-A15
DECODER
MEMORY
ARRAY
UB
VCC
VSS
NC
Power Supply
Ground
No Connection
Vcc
Vss
I/O DATA
CIRCUIT
I/O0-I/O15
PIN CONFIGURATION
COLUMN I/O
A4
A3
A5
A6
1
44
2
3
43
42
A2
A1
A7
OE
4
41
40
39
CE
A0
UB
LB
5
6
OE
WE
UB
LB
CE
CONTROL
CIRCUIT
7
8
9
I/O0
I/O1
I/O15
I/O14
38
37
36
35
34
I/O2
I/O3
I/O13
I/O12
Vss
10
11
Vcc
Vss
Vcc
12
13
33
32
I/O4
I/O5
I/O11
I/O10
14
15
31
I/O9
I/O6
I/O7
WE
30
29
I/O8
NC
A8
16
17
28
27
18
A15
A9
19
20
26
25
A14
A13
A12
NC
A10
A11
NC
21
22
24
23
TSOP II
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80072
2
UTRON
UT61L6416
64K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.1
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
VTERM
TA
RATING
-0.5 to 4.6
0 to 70
-20 to 80
-65 to 150
1
UNIT
V
℃
Terminal Voltage with Respect to VSS
Operating Temperature
Commercial
Extended
TA
℃
℃
Storage Temperature
Power Dissipation
DC Output Current
TSTG
PD
W
mA
℃
IOUT
50
Soldering Temperature (under 10 secs)
Tsolder
260
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
I/O OPERATION
MODE
Standby
SUPPLY CURRENT
OE
UB
CE
WE
LB
I/O0-I/O7
I/O8-I/O15
H
X
L
L
L
L
L
L
L
L
X
X
H
H
L
L
L
X
X
X
X
X
H
H
H
H
H
L
X
H
L
X
L
H
L
L
X
H
X
L
H
L
L
H
L
High – Z
High – Z
ISB, ISB1
ICC
ICC
High – Z
High – Z
DOUT
High – Z
DOUT
High – Z
High – Z
High – Z
DOUT
Output Disable
Read
Write
DOUT
DIN
High – Z
DIN
DIN
L
L
H
L
High – Z
DIN
ICC
L
Note: H = VIH, L=VIL, X = Don't care.
℃
℃
℃
℃
DC ELECTRICAL CHARACTERISTICS
(TA = 0 to 70 / -20 to 80 (E))
PARAMETER
Power Voltage
SYMBOL
TEST CONDITION
10/12/15
MIN.
3.15
3.0
2.0
-0.3
- 2
- 2
2.4
-
TYP.
3.3
3.3
MAX.
3.6
3.6
VCC+0.3
0.8
2
UNIT
8
V
V
V
V
A
µ
A
µ
V
V
mA
mA
mA
mA
VCC
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
VIH
VIL
ILI
-
-
-
-
-
-
-
-
-
-
≦
≦
VSS VIN VCC
ILO
VOH
VOL
≦
≦
2
-
VSS VI/O VCC; Output Disable
IOH= -4mA
IOL= 8mA
0.4
150
120
100
80
Cycle time=min, 100%duty
8
-
Operating Power
Supply Current
10
12
15
I/O=0mA,
=V
IL
-
-
-
CE
ICC
Standby Current (TTL)
ISB
-
3
10
mA
=VIH, other pins =VIL or VIH
CE
CE
=V -0.2V, other pins at 0.2V
3*4
mA
CC
Standby Current (CMOS) ISB1
-
1
or Vcc-0.2V
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 6ns.
2. Undershoot : Vss-3.0v for pulse width less than 6ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
4. ISB1< 1mA for special order or requirement.
UTRON TECHNOLOGY INC.
P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
3
UTRON
UT61L6416
64K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.1
℃
(TA=25 , f=1.0MHz)
CAPACITANCE
PARAMETER
Input Capacitance
SYMBOL
CIN
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Input/Output Capacitance
Note : These parameters are guaranteed by device characterization, but not production tested.
CI/O
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
3ns
1.5V
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
CL = 30pF, IOH/IOL = -4mA / 8mA
℃
℃
℃
℃
AC ELECTRICAL CHARACTERISTICS
(TA =0 to 70 / -20 to 80 (E))
(1) READ CYCLE
UT61L6416
-8
CC=3.15∼ 3.6 VCC=3.0∼ 3.6 VCC=3.0∼ 3.6
UT61L6416 UT61L6416 UT61L6416
-10 -12 -15
PARAMETER
SYMBOL
UNIT
∼
V
V
CC=3.0 3.6
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
8
-
-
-
8
8
4
-
10
-
-
-
10
10
5
-
-
5
5
-
12
-
-
-
12
12
6
-
-
6
6
-
15
-
-
-
15
15
7
-
-
7
7
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
3
0
-
-
3
3
0
-
-
3
3
0
-
-
3
3
0
-
-
3
-
4
4
-
tBA
-
-
4
4
-
-
-
5
5
-
-
-
6
6
-
-
-
7
7
-
ns
ns
ns
,
Access Time
LB UB
tBHZ
tBLZ
,
to High Z Output
to Low Z Output
LB UB
0
0
0
0
,
LB UB
(2) WRITE CYCLE
PARAMETER
UT61L6416
-8
VCC=3.15∼ 3.6
UT61L6416 UT61L6416 UT61L6416
-10 -12 -15
VCC=3.0∼ 3.6 VCC=3.0∼ 3.6
SYMBOL
UNIT
∼
CC=3.0 3.6
V
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
8
7
7
0
7
0
5.5
0
3
-
-
-
-
-
-
-
-
-
-
10
8
8
0
8
0
6
0
3
-
-
-
-
-
-
-
-
-
-
12
9
9
0
9
0
7
0
3
-
-
-
-
-
-
-
-
-
-
15
10
10
0
10
0
8
0
3
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
tOW*
tWHZ*
4
5
6
7
tBW
7
-
8
-
9
-
10
-
ns
,
Valid to End of Write
LB UB
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
4
UTRON
UT61L6416
64K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.1
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
(1,2)
tRC
Address
tAA
tOH
tOH
Previous data valid
Dout
Data Valid
READ CYCLE 2 (
and
Controlled)
OE
(1,3,4,5)
CE
tRC
Address
CE
tAA
tACE
tBA
LB , UB
OE
tBHZ
tBLZ
tCHZ
tOHZ
tOH
tOE
tCLZ
tOLZ
Dout
High-Z
High-Z
Data Valid
Notes :
1.
is high for read cycle.
WE
2.Device is continuously selected
=low,
=low,
CE
or
LB UB
=low.
or
OE
3.Address must be valid prior to or coincident with
=low,
=low transition; otherwise tAA is the limiting parameter.
±
CE
LB UB
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL=5pF. Transition is measured 500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tBHZ is less than tBLZ, tOHZ is less than tOLZ
.
UTRON TECHNOLOGY INC.
P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
5
UTRON
UT61L6416
64K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.1
WRITE CYCLE 1 (
Controlled)
(1,2,3,5,6)
WE
tWC
Address
CE
tAW
tCW
tAS
tWP
tWR
WE
tBW
LB , UB
tWHZ
(4)
tOW
tDH
High-Z
Dout
Din
(4)
tDW
Data Valid
WRITE CYCLE 2 (
Controlled)
(1,2,5,6)
CE
tWC
Address
tAW
CE
tWR
tAS
tCW
tWP
WE
tBW
LB , UB
tWHZ
High-Z
(4)
Dout
Din
tDW
tDH
Data Valid
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80072
6
UTRON
UT61L6416
64K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.1
WRITE CYCLE 3 (
,
Controlled)
(1,2,5,6)
LB UB
tWC
Address
tAW
CE
tAS
tCW
tWR
tWP
WE
LB , UB
Dout
tBW
tWHZ
High-Z
tDW
tDH
Din
Data Valid
Notes :
1.
,
,
,
must be high during all address transitions.
WE CE LB UB
2.A write occurs during the overlap of a low
, low
,
or
=low.
CE
OE
WE LB UB
3.During a
controlled write cycle with
low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed
WE
on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the low transition occurs simultaneously with or after low transition, the outputs remain in a high impedance state.
,
,
CE LB UB
WE
±
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
UTRON TECHNOLOGY INC.
P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
7
UTRON
UT61L6416
64K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.1
PACKAGE OUTLINE DIMENSION
Ⅱ
44-pin 400mil TSOP-
PACKAGE OUTLINE DIMENSION
SYMBOLS DIMENSIONS IN MILLMETERS
DIMENSIONS IN INCHS
MIN
1.00
0.05
0.95
0.30
0.12
18.313
11.854
10.058
-
NOM
-
MAX.
1.20
0.15
1.05
0.45
0.21
18.517
11.838
10.282
-
MIN.
NOM.
-
MAX.
A
A1
A2
b
c
D
E
E1
e
L
2D
y
0.039
0.002
0.037
0.012
0.0047
0.721
0.460
0.398
-
0.047
0.006
0.041
0.018
0.083
0.728
0.470
0.404
-
-
-
1.00
0.35
-
18.415
11.836
10.180
0.800
0.50
0.805
-
0.039
0.014
-
0.725
0.466
0.400
0.0315
0.020
0.0317
-
0.40
-
0.60
-
0.0157
-
0.0236
-
0.00
0.076
0.000
0.003
0o
-
5o
0o
-
5o
Θ
UTRON TECHNOLOGY INC.
P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
UTRON
UT61L6416
64K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.1
ORDERING INFORMATION
COMMERCIAL TEMPERATURE
PART NO.
ACCESS TIME
(ns)
PACKAGE
UT61L6416MC-8
UT61L6416MC-10
UT61L6416MC-12
UT61L6416MC-15
8
Ⅱ
Ⅱ
Ⅱ
Ⅱ
44 PIN TSOP-
44 PIN TSOP-
44 PIN TSOP-
44 PIN TSOP-
10
12
15
EXTENDED TEMPERATURE
PART NO.
ACCESS TIME
(ns)
PACKAGE
UT61L6416MC-8E
UT61L6416MC-10E
UT61L6416MC-12E
UT61L6416MC-15E
8
Ⅱ
Ⅱ
Ⅱ
Ⅱ
44 PIN TSOP-
44 PIN TSOP-
44 PIN TSOP-
44 PIN TSOP-
10
12
15
ORDERING INFORMATION (for lead free product)
COMMERCIAL TEMPERATURE
ACCESS TIME
PART NO.
(ns)
PACKAGE
UT61L6416MCL-8
UT61L6416MCL-10
UT61L6416MCL-12
UT61L6416MCL-15
8
Ⅱ
Ⅱ
Ⅱ
Ⅱ
44 PIN TSOP-
44 PIN TSOP-
44 PIN TSOP-
44 PIN TSOP-
10
12
15
EXTENDED TEMPERATURE
PART NO.
ACCESS TIME
(ns)
PACKAGE
UT61L6416MCL-8E
UT61L6416MCL-10E
UT61L6416MCL-12E
UT61L6416MCL-15E
8
Ⅱ
Ⅱ
Ⅱ
Ⅱ
44 PIN TSOP-
44 PIN TSOP-
44 PIN TSOP-
44 PIN TSOP-
10
12
15
UTRON TECHNOLOGY INC.
P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
9
UTRON
UT61L6416
64K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.1
THIS PAGE IS LEFT BLANK INTENTIONALLY.
UTRON TECHNOLOGY INC.
P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
10
相关型号：
©2020 ICPDF网 联系我们和版权申明