VL-MM9-4SBN [ETC]
4GB 512Mx64 DDR3 SDRAM LOW VOLTAGE NON-ECC UNBUFFERED SODIMM 204-PIN; 4GB 512Mx64 DDR3 SDRAM的低电压非ECC无缓冲的SODIMM 204针
| 型号： | VL-MM9-4SBN |
| 厂家： | 
ETC |
| 描述： | 4GB 512Mx64 DDR3 SDRAM LOW VOLTAGE NON-ECC UNBUFFERED SODIMM 204-PIN |
| 文件： | 总14页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Specifications
PART NO.:
REV: 1.2
VL47D5263A-K0/K9/F8/E7SD
General Information
4GB 512Mx64 DDR3 SDRAM LOW VOLTAGE NON-ECC UNBUFFERED SODIMM 204-PIN
Description
The VL47D5263A is a 512Mx64 DDR3 SDRAM high density SODIMM. This dual rank memory module consists of
sixteen CMOS 256Mx8 bits with 8 banks DDR3 synchronous DRAMs in BGA packages and a 2K EEPROM in an 8-
pin MLF package. This module is a 204-pin small-outline dual in-line memory module and is intended for mounting
into an edge connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR3
SDRAM.
Features
Pin Description
204-pin, small-outline dual in-line memory module (SODIMM)
Pin Name
A0~A14
Function
Fast data transfer rates: PC3-12800, PC3-10600, PC3-8500, PC3-6400
VDD = VDDQ = 1.35V (1.28V~1.45V) & 1.5V (1.425V~1.575V)
JEDEC standard 1.35V (1.28V~1.45V) & 1.5V (1.425V~1.575V)
VDDSPD = 3.0V to 3.6V
Eight internal component banks for concurrent operation
8-bit pre-fetch architecture
Bi-directional differential data-strobe
Nominal and dynamic on-die termination (ODT)
ZQ calibration support
Programmable CAS# latency:
11 (DDR3-1600), 9 (DDR3-1333), 7 (DDR3-1066), 6 (DDR3-800)
Programmable burst; length (8)
Average refresh period 7.8 us
Asynchronous reset
Fly-by topology
On board terminated command, address, and control bus
Serial presence detect (SPD) EEPROM with thermal sensor
Thermal sensor range: -40oC to +125oC (Max +/-3oC accuracy)
Lead-free, RoHS compliant
Address Inputs
A10/AP
Address Input/ Autoprecharge
Address Input/ Burst Chop
Bank Address Inputs
Data Input/Output
A12/BC#
BA0~BA2
DQ0~DQ63
DQS0~DQS7
DQS0#~DQS7#
DM0~DM7
Data Strobes
Data Strobes Complement
Data Masks
CK0,CK0#,
CK1,CK1#
Clock Input
ODT0, ODT1
CKE0, CKE1
CS0#, CS1#
RAS#
On-die Termination Control
Clock Enables
Chip Selects
Row Address Strobes
Column Address Strobes
Write Enable
CAS#
WE#
Gold edge contacts
VDD
Voltage Supply
PCB: Height 30.00mm (1.181”), double sided component
Operating temperature (TOPER): - Commercial (0oC <= Tc <= 95oC)
- Industrial (-40oC <= Tc <= 95oC)
Notes: Double refresh rate is required when 85oC < TOPER <= 95oC.
TOPER is DRAM case temperature (Tc).
VSS
Ground
SA0~SA1
SDA
SPD Address
SPD Data Input/Output
SPD Clock Input
SCL
EVENT#
VREFCA
VREFDQ
VDDSPD
VTT
Temperature Event Output
Reference Voltage for CA
Reference Voltage for DQ
SPD Voltage Supply
Termination Voltage
Register and SDRAM Control
No Connect
Order Information:
VL47D5263A-K0 S D-X
OPERATING TEMPERATURE
None: Commercial
S1: Industrial screening
RESET#
NC
DRAM DIE
D-DIE
DRAM MANUFACTURER
S - SAMSUNG
MODULE SPEED
K0: PC3-12800 @ CL11
K9: PC3-10600 @ CL9
F8: PC3-8500 @ CL7
E7: PC3-6400 @ CL6
VL: Lead-free/RoHS
DRAM component: Samsung K4B2G0846D-HYK0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – www.virtium.com
1
Product Specifications
PART NO.:
REV: 1.2
VL47D5263A-K0/K9/F8/E7SD
Pin Configuration
204-PIN DDR3 SODIMM FRONT
204-PIN DDR3 SODIMM BACK
Pin
1
Name
VREFDQ
VSS
Pin Name Pin
DQ19 105
VSS 107
Name
VDD
A10
Pin
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
Name
DQ42
DQ43
VSS
Pin
2
Name
VSS
Pin
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
Name
VSS
Pin
106
108
110
112
Name
VDD
BA1
Pin
158
160
162
164
166
168
170
172
174
176
Name
DQ46
DQ47
VSS
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
3
4
DQ4
DQ28
DQ29
VSS
5
DQ0
DQ24 109
DQ25 111
BA0
6
DQ5
RAS#
VDD
CS0#
ODT0
VDD
ODT1
NC
7
DQ1
VDD
WE#
CAS#
VDD
A13
DQ48
DQ49
VSS
8
VSS
DQ52
DQ53
VSS
9
VSS
VSS
DM3
VSS
113
115
117
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
DQS0#
DQS0
VSS
DQS3# 114
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
DM0
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
A15 *
A14
116
118
120
122
124
VSS
DQS6#
DQS6
VSS
DM6
DQ2
DQ26 119
DQ27 121
DQ6
VSS
DQ3
CS1#
VDD
NC
DQ7
DQ54
DQ55
VSS
VSS
VSS
123
DQ50
DQ51
VSS
VSS
VDD
DQ8
CKE0 125
DQ12
DQ13
VSS
126 VREFCA 178
DQ9
VDD
NC
127
129
131
133
VSS
DQ32
DQ33
VSS
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
VSS
DQ36
DQ37
VSS
180
182
184
186
188
190
192
194
196
DQ60
DQ61
VSS
VSS
DQ56
DQ57
VSS
DQS1#
DQS1
VSS
BA2
VDD
A12
A9
DM1
RESET#
VSS
VDD
A11
DQS7#
DQS7
VSS
135 DQS4# 187
DM7
DM4
DQ10
DQ11
VSS
137
139
141
143
145
147
149
151
153
155
DQS4
VSS
189
191
193
195
197
VSS
DQ14
DQ15
VSS
A7
VSS
VDD
A8
DQ58
DQ59
VSS
VDD
A6
DQ38
DQ39
VSS
DQ62
DQ63
VSS
DQ34
DQ35
VSS
DQ16
DQ17
VSS
A5
DQ20
DQ21
VSS
A4
VDD
A3
SA0
VDD
A2
DQ44
DQ45
VSS
198 EVENT#
DQ40
DQ41
VSS
199 VDDSPD
200
202
204
SDA
SCL
VTT
DQS2#
DQS2
VSS
A1
201
203
SA1
VTT
DM2
A0
VDD
CK0
CK0#
VSS
VDD
CK1
CK1#
DQS5#
DQS5
VSS
DM5
DQ22
DQ23
DQ18
VSS
*: These pins are not used in this module.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – www.virtium.com
2
Product Specifications
PART NO.:
REV: 1.2
VL47D5263A-K0/K9/F8/E7SD
Function Block Diagram
CS1#
CS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Vss
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
D8
D4
D12
DQ4
DQ4
DQ5
DQ6
DQ7
ZQ
DQ5
DQ6
DQ7
ZQ
DQ7
ZQ
ZQ
Vss
Vss
Vss
Vss
Vss
Vss
DQS1
DQS1#
DM1
DQS5
DQS5#
DM5
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Vss
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Vss
D1
D9
D5
D13
DQ4
DQ4
DQ5
DQ6
DQ7
ZQ
DQ5
DQ6
DQ7
ZQ
DQ7
ZQ
DQ7
ZQ
Vss
Vss
Vss
DQS2
DQS2#
DM2
DQS6
DQS6#
DM6
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
Vss
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
Vss
D2
D10
D6
D14
DQ4
DQ4
DQ5
DQ6
DQ7
ZQ
DQ5
DQ6
DQ7
ZQ
DQ7
ZQ
DQ7
ZQ
DQS3
DQS3#
DM3
DQS7
DQS7#
DM7
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Vss
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Vss
D3
D11
D7
D15
DQ4
DQ4
DQ5
DQ6
DQ7
ZQ
DQ5
DQ6
DQ7
ZQ
DQ7
ZQ
DQ7
ZQ
Command, address, control, and clock line terminations
A0-A14, BA0-BA2
36 ohm+/-5%
DDR3
A0-A14: SDRAMs D0-D15
BA0-BA2: SDRAMs D0-D15
RAS#: SDRAMs D0-D15
CAS#: SDRAMs D0-D15
WE#: SDRAMs D0-D15
CKE0: SDRAMs D0-D7
ODT0: SDRAMs D0-D7
CKE1: SDRAMs D8-D15
ODT1: SDRAMs D8-D15
RESET#: SDRAMs D0-D15
A0-A14
RAS#, CAS#, WE#,
CS0#, CKE0, ODT0
VTT
SDRAM
BA0-BA2
RAS#
CAS#
WE#
CKE0
ODT0
CKE1
ODT1
RESET#
Serial PD
w ith integrated thermal sensor
CS1#, CKE1, ODT1
30 ohm+/-5%
0.1uF
DDR3
SDRAM
CK0, CK1
CK0#, CK1#
SCL
SDA
VDD
EVENT#
A0 A1 A2
EVENT#
SA0 SA1
Vss
Serial PD/
Thermal sensor
VDDSPD
VDD
D0-D15
D0-D15
D0-D15
D0-D15
D0-D15
VTT
CK0
CK1
D0-D7
D8-D15
VREFCA
VREFDQ
VSS
CK0#
CK1#
3.3pF
3.3pF
Notes:
1. Unless otherw ise noted, resistor values are 15 ohms +/-5%
2. ZQ resistors are 240 ohms +/-1%
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – www.virtium.com
3
Product Specifications
PART NO.:
REV: 1.2
VL47D5263A-K0/K9/F8/E7SD
Absolute Maximum Ratings
Symbol
VDD
Parameter
Min
-0.4
-0.4
-0.4
-55
Max
Unit
V
Voltage on VDD pin relative to VSS
1.975
1.975
1.975
100
VDDQ
Voltage on VDDQ pin relative to VSS
Voltage on any pin relative to VSS
Storage temperature
V
VIN, VOUT
TSTG
V
0C
Address, RAS#,
CAS#, WE#, BA
-32
-16
32
16
uA
uA
Input leakage current; Any input 0V<VIN<VDD;
VREF input 0V<VIN<0.95V;
CS#, CKE, ODT,
CK, CK#
IL
Other pins not under test = 0V
DM
-4
4
uA
uA
uA
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT are disabled
IOZ
DQ, DQS, DQS#
-10
-16
10
16
IVREF
VREF supply leakage current; VREF = Valid VREF level
DC Operating Conditions
Symbol
Parameter
Operating Voltage
Min
1.283
Typical
1.35
Max
Unit Notes
1.35V
1.5V
1.45
1.575
VDD
Supply Voltage
V
1,2
1.425
1.5
1.35V
1.5V
1.283
1.35
1.45
VDDQ
I/O Supply Voltage
V
1,2
1.425
1.5
1.575
VREFDQ (DC) I/O reference voltage DQ bus
VREFCA (DC) Input reference voltage CMD/ADD bus
VTT Termination Reference Voltage
0.49 x VDD
0.49 x VDD
-0.483 x VDDQ
0.5 x VDD
0.5 x VDD
0.51 x VDD
0.51 x VDD
V
V
V
3,4
3,4
5
0.5 x VDDQ +0.517 x VDDQ
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than +/-1% VDD
4. For reference: approximate VDD/2 +/-15mV.
5. VTT termination voltage in excess of stated limit will adversely affect the command and address signals’ voltage margin and will reduce
timing margins.
Operating Temperature Condition
Symbol
Parameter
Rating
0 to 95
Units Notes
Commercial
Industrial
TOPER
Operating temperature
0C
1,2
-40 to +95
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JEDEC JESD51-2.
o
2. At -40 to +85 C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when
o
o
85 C < TOPER <= 95 C.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – www.virtium.com
4
Product Specifications
PART NO.:
REV: 1.2
VL47D5263A-K0/K9/F8/E7SD
Input DC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Min
Max
Unit
1.35V
Command and Address
VIHCA(DC)
VILCA(DC)
DQ and DM
VIHDQ(DC)
VILDQ(DC)
VREF + 0.090
VSS
VDD
V
V
Input High (Logic 1) Voltage (DDR3-800/1066/1333/1600)
Input Low (Logic 0) Voltage (DDR3-800/1066/1333/1600)
VREF - 0.090
VREF + 0.090
VSS
VDD
V
V
Input High (Logic 1) Voltage (DDR3-800/1066/1333/1600)
Input Low (Logic 0) Voltage (DDR3-800/1066/1333/1600)
1.5V
VREF - 0.090
Command and Address
VIHCA(DC)
VILCA(DC)
DQ and DM
VIHDQ(DC)
VILDQ(DC)
VREF + 0.100
VSS
VDD
V
V
Input High (Logic 1) Voltage (DDR3-800/1066/1333/1600)
Input Low (Logic 0) Voltage (DDR3-800/1066/1333/1600)
VREF - 0.100
VREF + 0.100
VSS
VDD
V
V
Input High (Logic 1) Voltage (DDR3-800/1066/1333/1600)
Input Low (Logic 0) Voltage (DDR3-800/1066/1333/1600)
VREF – 0.100
Input AC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Min
Max
Unit
1.35V
Command and Address
VIHCA(AC)
VILCA(AC)
DQ and DM
VIHDQ(AC)
VILDQ(AC)
VIHDQ(AC)
VILDQ(AC)
VREF + 0.160
-
-
V
V
Input High (Logic 1) Voltage (DDR3-800/1066/1333/1600)
Input Low (Logic 0) Voltage (DDR3-800/1066/1333/1600)
VREF - 0.160
VREF + 0.160
-
V
V
V
V
Input High (Logic 1) Voltage (DDR3-800/1066)
Input Low (Logic 0) Voltage (DDR3-800/1066)
Input High (Logic 1) Voltage (DDR3-1333/1600)
Input Low (Logic 0) Voltage (DDR3-1333/1600)
1.5V
-
VREF - 0.160
-
VREF + 0.135
-
VREF - 0.135
Command and Address
VIHCA(AC)
VILCA(AC)
DQ and DM
VIHDQ(AC)
VILDQ(AC)
VIHDQ(AC)
VILDQ(AC)
VREF + 0.175
-
-
V
V
Input High (Logic 1) Voltage (DDR3-800/1066/1333/1600)
Input Low (Logic 0) Voltage (DDR3-800/1066/1333/1600)
VREF - 0.175
VREF + 0.175
-
V
V
V
V
Input High (Logic 1) Voltage (DDR3-800/1066)
Input Low (Logic 0) Voltage (DDR3-800/1066)
Input High (Logic 1) Voltage (DDR3-1333/1600)
Input Low (Logic 0) Voltage (DDR3-1333/1600)
-
VREF - 0.175
-
VREF + 0.150
-
VREF - 0.150
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – www.virtium.com
5
Product Specifications
PART NO.:
REV: 1.2
VL47D5263A-K0/K9/F8/E7SD
Input/Output Capacitance
TA=250C, f=100MHz
K0
K9
F8
E7
(DDR3-1600) (DDR3-1333) (DDR3-1066) (DDR3-800)
Parameter
Symbol
Unit
Min
1.35V
16
Max
Min
Max
Min
Max
Min
Max
Input capacitance (A0~A14, BA0~BA2, RAS#,
CAS#, WE#)
CIN1
CIN2
24.8
14.4
16
10
24.8
14.4
16
10
24.8
14.4
16
10
24.8
14.4
pF
pF
Input capacitance (CKE0, CKE1), (ODT0, ODT1),
(CS0#, CS1#)
10
Input capacitance (CK0, CK0#), (CK1, CK1#)
Input/Output capacitance (DQ, DQS, DQS#, DM)
CIN3
CIO
10.4
6.4
15.2
8.6
10.4
7
15.2
8.6
10.4
7
16.8
9
10.4
7
16.8
9
pF
pF
1.5V
16
Input capacitance (A0~A14, BA0~BA2, RAS#,
CAS#, WE#)
CIN1
24.8
16
24.8
16
28
16
28
pF
Input capacitance (CKE0, CKE1), (ODT0, ODT1),
(CS0#, CS1#)
CIN2
CIN3
CIO
10
10.4
6.8
14.4
15.2
8.6
10
10.4
7
14.4
15.2
9
10
10.4
7
16
16.8
9.4
10
10.4
7
16
16.8
10
pF
pF
pF
Input capacitance (CK0, CK0#), (CK1, CK1#)
Input/Output capacitance (DQ, DQS, DQS#, DM)
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – www.virtium.com
6
Product Specifications
PART NO.:
REV: 1.2
VL47D5263A-K0/K9/F8/E7SD
Basic IDD and IDDQ Measurement Conditions
Condition
Symbol
Operating one bank active-precharge current;
IDD0*
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
Operating one bank active-read-precharge current;
IDD1*
IDD2P-F**
IDD2P-S**
IDD2N**
IDD2Q**
IDD3P**
IDD3N**
IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD); CKE
is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W.
Precharge power-down current Fast Exit;
All device banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
Precharge power-down current Low Exit;
All device banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
Precharge standby current;
All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are SWITCHING; Data
bus inputs are SWITCHING.
Precharge quiet standby current;
All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING.
Active power-down current;
All device banks open; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
Active standby current;
All device banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS= tRAS MAX(IDD)); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Operating burst read current;
All device banks open; Continuous burst reads; IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS
MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data
pattern is same as IDD4W.
IDD4R*
IDD4W*
Operating burst write current;
All device banks open; Continuous burst writes; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP=
tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
Burst refresh current;
IDD5**
IDD6**
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH; CS# is HIGH between valid commands; Other
control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING.
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 8; CL = CL(IDD); AL = tRCD(IDD) - 1*tCK(IDD); tCK= tCK(IDD); tRC=
tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between valid commands; Address bus
inputs are STABLE during DESELECTs; Data pattern is same as IDD4R.
IDD7*
Notes:
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – www.virtium.com
7
Product Specifications
PART NO.:
REV: 1.2
VL47D5263A-K0/K9/F8/E7SD
IDD Specification
K0
K9
(DDR3-1333)
F8
E7
(DDR3-800)
(DDR3-1600)
(DDR3-1066)
Symbol
Unit
1.35V
1.5V
1.35V
1.5V
1.35V
1.5V
1.35V
1.5V
IDD0
IDD1
400
480
240
160
272
272
272
480
600
680
1840
160
1080
456
360
440
208
160
240
240
240
400
560
600
1840
160
1040
416
320
400
208
160
240
240
240
400
480
520
1760
160
840
376
320
400
208
160
240
240
240
400
480
520
1760
160
840
376
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
536
240
192
320
320
320
560
816
856
1920
192
1216
496
240
192
320
320
272
560
696
736
1840
192
1176
456
240
192
272
272
272
480
616
656
1760
192
936
456
240
192
272
272
272
480
616
656
1760
192
936
IDD2P-F
IDD2P-S
IDD2N
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
Note: IDD specification is based on Samsung D-die components.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – www.virtium.com
8
Product Specifications
PART NO.:
REV: 1.2
VL47D5263A-K0/K9/F8/E7SD
AC TIMING PARAMETERS & SPECIFICATIONS
K0
K9
F8
E7
(DDR3-1600)
(DDR3-1333)
(DDR3-1066)
(DDR3-800)
Parameter
Symbol
Unit
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
tCK(DLL_OFF)
tCK(avg)
8
-
8
-
8
-
8
-
ns
ns
Average Clock Period
Clock Period
1.25
<1.50
1.5
<1.875
1.875
<2.5
2.5
3.3
tCK(avg)min tCK(avg)max tCK(avg)min tCK(avg)max tCK(avg)min tCK(avg)max tCK(avg)min tCK(avg)max
tCK(abs)
+
+
+
+
+
+
+
+
ns
tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max
Average high pulse width
tCH(avg)
tCL(avg)
0.47
0.47
-70
0.53
0.53
70
0.47
0.47
-80
0.53
0.53
80
0.47
0.47
-90
0.53
0.53
90
0.47
0.47
-100
-90
0.53
0.53
100
90
tCK(avg)
Average low pulse width
tCK(avg)
ps
Clock Period Jitter
tJIT(per)
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
tJIT(per, lck)
tJIT(cc)
-60
60
-70
70
-80
80
ps
140
120
160
140
180
160
200
180
ps
Cycle to Cycle Period Jitter during DLL
locking period
tJIT(cc, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
ps
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
-103
-122
-136
-147
-155
-163
-169
-175
-180
-184
-188
103
122
136
147
155
163
169
175
180
184
188
-118
-140
-155
-168
-177
-186
-193
-200
-205
-210
-215
118
140
155
168
177
186
193
200
205
210
215
-132
-157
-175
-188
-200
-209
-217
-224
-231
-237
-242
132
157
175
188
200
209
217
224
231
237
242
-147
-175
-194
-209
-222
-232
-241
-249
-257
-263
-269
147
175
194
209
222
232
241
249
257
263
269
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Cumulative error across n = 13, 14 ... 49, 50
cycles
tERR(nper)min =(1+ 0.68ln(n))*tJIT(per)min
tERR(nper)max=(1+ 0.68ln(n))*tJIT(per)max
tERR(nper)
ps
Absolute clock HIGH pulse width
Absolute clock Low pulse width
Data Timing
tCH(abs)
tCL(abs)
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
tCK(avg)
tCK(avg)
DQS,DQS# to DQ skew, per group, per
access
tDQSQ
-
100
-
125
-
150
-
200
ps
DQ output hold time from DQS, DQS#
DQ low-impedance time from CK, CK#
DQ high-impedance time from CK, CK#
tQH
0.38
-450
-
-
0.38
-500
-
-
0.38
-600
-
-
0.38
-800
-
-
tCK(avg)
tLZ(DQ)
tHZ(DQ)
225
225
250
250
300
300
400
400
ps
ps
tDS(base)
(AC160)
-
-
-
-
-
-
-
-
-
-
40
-
-
-
-
-
90
-
-
-
-
-
ps
ps
ps
ps
Data setup time to DQS, DQS#
referenced to Vih(ac)Vil(ac)
levels
1.35V
1.5V
tDS(base)
(AC135)
25
-
45
-
tDS(base)
(AC175)
25
-
75
-
Data setup time to DQS, DQS#
referenced to Vih(ac)Vil(ac)
levels
tDS(base)
(AC150)
10
30
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – www.virtium.com
9
Product Specifications
PART NO.:
REV: 1.2
VL47D5263A-K0/K9/F8/E7SD
AC TIMING PARAMETERS & SPECIFICATIONS
K0
K9
F8
E7
(DDR3-1600)
(DDR3-1333)
(DDR3-1066)
(DDR3-800)
Parameter
Symbol
Unit
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Data hold time to DQS, DQS# referenced to
Vih(ac)Vil(ac) levels
tDH(base)
tDIPW
55
-
75
-
110
-
160
-
ps
ps
DQ and DM Input pulse width for each input
360
-
400
-
490
-
600
-
Data Strobe Timing
DQS, DQS# READ Preamble
DQS, DQS# differential READ Postamble
DQS, DQS# output high time
DQS, DQS# output low time
tRPRE
tRPST
tQSH
0.9
0.3
0.4
0.4
0.9
0.3
-
-
-
-
-
-
0.9
0.3
0.4
0.4
0.9
0.3
-
-
-
-
-
-
0.9
0.3
-
-
-
-
-
-
0.9
0.3
-
-
-
-
-
-
tCK
tCK
0.38
0.38
0.9
0.38
0.38
0.9
tCK(avg)
tCK(avg)
tCK
tQSL
DQS, DQS# WRITE Preamble
DQS, DQS# WRITE Postamble
tWPRE
tWPST
0.3
0.3
tCK
DQS, DQS# rising edge output access time
from rising CK, CK#
tDQSCK
-225
-450
225
225
-255
-500
255
250
-300
-600
300
300
-400
-800
400
400
ps
ps
DQS, DQS# low-impedance time
(Referenced from RL-1)
tLZ(DQS)
DQS, DQS# high-impedance time
(Referenced from RL+BL/ 2)
tHZ(DQS)
tDQSL
-
225
0.55
0.55
-
250
0.55
0.55
-
300
0.55
0.55
-
400
0.55
0.55
ps
DQS, DQS# differential input low pulse width
0.45
0.45
0.45
0.45
0.45
0.45
0.45
0.45
tCK
tCK
DQS, DQS# differential input high pulse
width
tDQSH
DQS, DQS# rising edge to CK, CK# rising
edge
tDQSS
tDSS
-0.27
0.18
0.18
0.27
-0.25
0.2
0.25
-0.25
0.2
0.25
-0.25
0.2
0.25
tCK(avg)
tCK(avg)
tCK(avg)
DQS,DQS# failing edge setup time to CK,
CK# rising edge
-
-
-
-
-
-
-
-
DQS,DQS# failing edge hold time to CK,
CK# rising edge
tDSH
0.2
0.2
0.2
Command and Address Timing
DLL locking time
tDLLK
tRTP
512
-
-
512
-
-
512
-
-
512
-
-
nCK
Internal READ Command to PRECHARGE
Command delay
max
(4tCK,7.5ns)
max
(4tCK,7.5ns)
max
(4tCK,7.5ns)
max
(4tCK,7.5ns)
Delay from start of internal write transaction
to internal read command
max
(4tCK,7.5ns)
max
(4tCK,7.5ns)
max
(4tCK,7.5ns)
max
(4tCK,7.5ns)
tWTR
-
-
-
-
WRITE recovery time
tWR
tMRD
tMOD
tCCD
15
4
-
-
-
-
15
4
-
-
-
-
15
4
-
-
-
-
15
4
-
-
-
-
ns
Mode Register Set command cycle time
Mode Register Set command update delay
CAS# to CAS# command delay
nCK
max
(12tCK,15ns)
max
(12tCK,15ns)
max
(12tCK,15ns)
max
(12tCK,15ns)
4
4
4
4
nCK
nCK
Auto precharge write recovery + precharge
time
tDAL(min)
WR + roundup (tRP / tCK(AVG))
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
ACTIVE to internal read or write delay time
PRECHARGE command period
tMPRR
tRAS
tRCD
tRP
1
-
1
-
1
-
1
-
nCK
ns
35
9*tREFI
36
9*tREFI
37.5
9*tREFI
37.5
15
9*tREFI
13.75
13.75
48.75
-
-
-
13.5
13.5
49.5
-
-
-
13.13
13.13
50.63
-
-
-
-
-
-
ns
15
ns
ACTIVE to ACTIVE or REF command period
tRC
52.5
ns
ACTIVE to ACTIVE command period for
1KB page size
max
(4tCK,6ns)
max
(4tCK,6ns)
max
(4tCK,7.5ns)
max
(4tCK,10ns)
tRRD
tRRD
-
-
-
-
-
-
-
-
ACTIVE to ACTIVE command period for
2KB page size
max
(4tCK,7.5ns)
max
(4tCK,7.5ns)
max
(4tCK,10ns)
max
(4tCK,10ns)
Four activate window for 1KB page size
Four activate window for 2KB page size
tFAW
tFAW
30
40
-
-
30
45
-
-
37.5
50
-
-
40
50
-
-
ns
ns
tIS(base)
(AC160)
-
-
-
-
-
-
140
-
-
-
215
-
-
-
ps
ps
Command and Address setup
time to CK, CK# referenced to
Vih(ac) / Vil(ac) levels
1.35V
tIS(base)
(AC135)
185
205
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – www.virtium.com
10
Product Specifications
PART NO.:
REV: 1.2
VL47D5263A-K0/K9/F8/E7SD
AC TIMING PARAMETERS & SPECIFICATIONS
K0
K9
F8
E7
(DDR3-1600)
(DDR3-1333)
(DDR3-1066)
(DDR3-800)
Parameter
Symbol
Unit
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tIS(base)
(AC175)
45
45 + 125
130
-
65
65 + 125
150
-
125
125 + 150
210
-
200
200 + 150
285
-
ps
ps
ps
ps
Command and Address setup
time to CK, CK# referenced to
Vih(ac) / Vil(ac) levels
1.5V
tIS(base)
(AC150)
-
-
-
-
-
-
-
-
-
-
-
-
Command and Address hold time from CK,
CK# referenced to Vih(ac) / Vil(ac) levels
tIH(base)
tIPW
Control & Address Input pulse width for each
input
560
620
780
900
Refresh Timing
2Gb REFRESH to REFRESH or REFRESH
to ACTIVE command interval
tRFC
tREFI
tREFI
160
7.8
3.9
-
-
-
160
7.8
3.9
-
-
-
160
7.8
3.9
-
-
-
160
7.8
3.9
-
-
-
ns
us
us
Average periodic refresh interval
(0°C<= TCASE <= 85 °C)
Average periodic refresh interval
(85°C<= TCASE <= 95 °C)
Calibration Timing
Power-up and RESET calibration time
tZQinitI
tZQoper
tZQCS
512
256
64
-
-
-
512
256
64
-
-
-
512
256
64
-
-
-
512
256
64
-
-
-
tCK
tCK
tCK
Normal operation Full calibration time
Normal operation Short calibration time
Reset Timing
max
(5tCK, tRFC
+ 10ns)
max
(5tCK, tRFC
+ 10ns)
max
(5tCK, tRFC
+ 10ns)
max
(5tCK, tRFC
+ 10ns)
Exit Reset from CKE HIGH to a valid
command
tXPR
-
-
-
-
Self Refresh Timing
max(5tC,
tRFC
+10ns)
max(5tC,
tRFC
+10ns)
Exit Self Refresh to commands not requiring
a locked DLL
max(5tC,
tRFC+10ns)
max(5tC,
tRFC+10ns)
tXS
-
-
-
-
Exit Self Refresh to commands requiring a
locked DLL
tXSDLL
tCKESR
tCKSRE
tCKSRX
tDLLK(min)
-
-
-
-
tDLLK(min)
-
-
-
-
tDLLK(min)
-
-
-
-
tDLLK(min)
-
-
-
-
nCK
Minimum CKE low width for Self refresh
entry to exit timing
tCKE(min) +
1tCK
tCKE(min) +
1tCK
tCKE(min) +
1tCK
tCKE(min) +
1tCK
Valid Clock Requirement after Self Refresh
Entry (SRE)
max(5tC,
10ns)
max(5tCK,
10ns)
max(5tCK,
10ns)
max(5tCK,
10ns)
Valid Clock Requirement before Self
Refresh Exit (SRX)
max(5tC,
10ns)
max(5tCK,
10ns)
max(5tCK,
10ns)
max(5tCK,
10ns)
Power Down Timing
Exit Power Down with DLL to any valid
command; Exit Precharge Power Down with
DLL frozen to commands not requiring a
locked DLL
max
(3tCK,6ns)
max
(3tCK,6ns)
max
(3tCK,7.5ns)
max
(3tCK,7.5ns)
tXP
-
-
-
-
Exit Precharge Power Down with DLL frozen
to commands requiring a locked DLL
max
(10tCK,24ns)
max
(10tCK,24ns)
max
(10tCK,24ns)
max
(10tCK,24ns)
tXPDLL
tCKE
-
-
-
-
max (3tCK,
5ns)
max (3tCK,
5.625ns)
max (3tCK,
5.625ns)
max (3tCK,
7.5ns)
CKE minimum pulse width
-
-
-
-
Command pass disable delay
Power Down Entry to Exit Timing
tCPDED
tPD
1
-
1
-
1
-
1
-
nCK
tCK
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
Timing of ACT command to Power Down
entry
tACTPDEN
tPRPDEN
tRDPDEN
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
nCK
nCK
Timing of PRE command to Power Down
entry
Timing of RD/RDA command to Power
Down entry
RL + 4 +1
RL + 4 +1
RL + 4 +1
RL + 4 +1
WL + 4
+ (tWR/
tCK(avg))
WL + 4
+ (tWR/
tCK(avg))
WL + 4
+ (tWR/
tCK(avg))
WL + 4
+ (tWR/
tCK(avg))
Timing of WR command to Power Down
entry BL8 (OTF, MRS), BL4OTF
tWRPDEN
-
-
-
-
-
-
-
-
nCK
nCK
Timing of WRA command to Power Down
entry BL8 (OTF, MRS), BL4OTF
WL+4
+WR+1
WL+4
+WR+1
WL+4
+WR+1
WL+4
+WR+1
tWRAPDEN
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – www.virtium.com
11
Product Specifications
PART NO.:
REV: 1.2
VL47D5263A-K0/K9/F8/E7SD
AC TIMING PARAMETERS & SPECIFICATIONS
K0
K9
F8
E7
(DDR3-1600)
(DDR3-1333)
(DDR3-1066)
(DDR3-800)
Parameter
Symbol
Unit
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
WL + 2
+ (tWR/
tCK(avg))
WL + 2
+ (tWR/
tCK(avg))
WL + 2
+ (tWR/
tCK(avg))
WL + 2
+ (tWR/
tCK(avg))
Timing of WR command to Power Down
entry (BL4MRS)
tWRPDEN
-
-
-
-
nCK
nCK
Timing of WRA command to Power Down
entry (BL4MRS)
WL+2
+WR+1
WL+2
+WR+1
WL+2
+WR+1
WL+2
+WR+1
tWRAPDEN
tREFPDEN
tMRSPDEN
-
-
-
-
-
-
-
-
-
-
-
-
Timing of REF command to Power Down
entry
1
1
1
1
Timing of MRS command to Power Down
entry
tMOD(min)
tMOD(min)
tMOD(min)
tMOD(min)
ODT Timing
ODT high time without write command or
with write command and BC4
ODTH4
ODTH8
tAONPD
tAOFPD
tAON
4
6
-
4
6
-
4
6
-
4
6
-
nCK
nCK
ODT high time with Write command and BL8
-
-
-
-
Asynchronous RTT turn-on delay (Power-
Down with DLL frozen)
2
8.5
8.5
225
0.7
0.7
2
8.5
8.5
250
0.7
0.7
2
8.5
8.5
300
0.7
0.7
2
8.5
8.5
400
0.7
0.7
ns
Asynchronous RTT turn-off delay (Power-
Down with DLL frozen)
2
2
2
2
ns
ODT turn-on
-225
0.3
0.3
-250
0.3
0.3
-300
0.3
0.3
-400
0.3
0.3
ps
RTT_NOM and RTT_WR turn-off time from
ODTL off reference
tAOF
tCK(avg)
tCK(avg)
RTT dynamic change skew
tADC
Write Leveling Timing
First DQS pulse rising edge after tDQSS
margining mode is programmed
tWLMRD
tWLDQSEN
tWLS
40
25
165
165
0
-
-
40
25
195
195
0
-
-
40
25
245
245
0
-
-
40
25
325
325
0
-
-
tCK
tCK
ps
DQS/DQS delay after tDQS margining mode
is programmed
Setup time for tDQSS latch
Hold time for tDQSS latch
Write leveling output delay
Write leveling output error
-
-
-
-
tWLH
-
-
-
-
ps
tWLO
7.5
2
9
2
9
2
9
2
ns
tWLOE
0
0
0
0
ns
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – www.virtium.com
12
Product Specifications
PART NO.:
REV: 1.2
VL47D5263A-K0/K9/F8/E7SD
Package Dimensions
FRONT VIEW
3.40 MAX
67.60
4.0 +/- 0.10 (2X)
30.00
1.80 (2X)
TYP
20.00
6.00 TYP
0.5 R
1.0 +/- 0.10
TYP
PIN 203
2.15 TYP
0.60 TYP
PIN 1
0.45 TYP
1.0 +/- 0.10
63.60 TYP
BACK VIEW
4.00 TYP
PIN 2
2.55 TYP
3.00 TYP
PIN 204
21.00 TYP
24.80 TYP
39.00 TYP
Note: 1. All dimensions are in millimeters with tolerance +/- 0.15mm unless otherwise specified.
2. The dimensional diagram is for reference only.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – www.virtium.com
13
Product Specifications
PART NO.:
REV: 1.2
VL47D5263A-K0/K9/F8/E7SD
Revision History:
Date
Rev.
Page
Changes
04/17/2012
05/04/2012
05/07/2012
1.0
1.1
1.2
All
5
Spec released
Update Input AC Logic Level table
Typo correction
5
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – www.virtium.com
14
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