VS1002D [ETC]
MP3 AUDIO CODEC; MP3音频编解码器
| 型号： | VS1002D |
| 厂家： | 
ETC |
| 描述： | MP3 AUDIO CODEC |
| 文件： | 总54页 (文件大小：517K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VS1002D
VS1002d
VS1002d - MP3 AUDIO CODEC
Features
Description
• Decodes MPEG 1.0 & 2.0 audio layer III (CBR
VS1002d is a single-chip MP3 audio decoder. It
contains a high-performance, low-power DSP pro-
cessor core VS DSP4, working data memory, 5
KiB instruction RAM and 2.5 KiB data RAM for
user applications, serial control and input data in-
terfaces, 4 general purpose I/O pins, an UART, as
well as a high-quality variable-sample-rate mono
ADC and stereo DAC, followed by an earphone
amplifier and a ground buffer.
+ VBR); WAV and PCM files
• Encodes ADPCM from microphone input
• Streaming support for MP3 and WAV
• Bass control
• Operates with single a clock 12..13 MHz or
24..26 MHz.
• Internal clock doubler
• Low-power operation
• High-quality on-chip stereo DAC with no
phase error between channels
VS1002d receives its input bitstream through a
serial input bus, which it listens to as a system
slave. The input stream is decoded and passed
through a digital volume control to an 18-bit over-
sampling, multi-bit, sigma-delta DAC. The decod-
ing is controlled via a serial control bus. In addi-
tion to the basic decoding, it is possible to add
application specific features, like DSP effects, to
the user RAM memory.
• Stereo earphone driver capable of driving a
30 load
• Separate 2.5 V..3.6 V operating voltages for
analog and digital
• 7.5 KiB On-chip RAM for user code / data
• Serial control and data interfaces
• Can be used as a slave co-processor
• SPI flash boot for special applications
• UART for debugging purposes
• New functions may be added with software
and 4 GPIO pins
• Lead-free RoHS-compliant packages
audio
VS1002
L
audio
Mono
ADC
Stereo
DAC
Stereo Ear−
phone Driver
MIC AMP
R
4
output
GPIO
GPIO
X ROM
X RAM
Y ROM
Y RAM
DREQ
SO
SI
Serial
Data/
4
SCLK
XCS
XDCS
Control
Interface
VSDSP
RX
UART
TX
Instruction
RAM
Instruction
ROM
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CONTENTS
Contents
1
2
3
4
License
9
9
Disclaimer
Definitions
9
Characteristics & Specifications
10
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.5 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.6 Switching Characteristics - Boot Initialization . . . . . . . . . . . . . . . . . . . . . . . 12
5
Packages and Pin Descriptions
13
5.1 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1 LQFP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.2 BGA-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 LQFP-48 and BGA-49 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
7
Connection Diagram, LQFP-48
SPI Buses
15
16
7.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2 SPI Bus Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2.1 VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . . . . . . 16
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7.2.2 VS1001 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.3 Data Request Pin DREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.4 Serial Protocol for Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . . 17
7.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.4.2 SDI in VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . . 17
7.4.3 SDI in VS1001 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . 18
7.5 Serial Protocol for Serial Command Interface (SCI) . . . . . . . . . . . . . . . . . . . . 18
7.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.5.2 SCI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.5.3 SCI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.6 SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.7 SPI Examples with SM SDINEW and SM SDISHARED set . . . . . . . . . . . . . . . 21
7.7.1 Two SCI Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.7.2 Two SDI Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.7.3 SCI Operation in Middle of Two SDI Bytes . . . . . . . . . . . . . . . . . . . . 21
8
Functional Description
22
8.1 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.2 Supported Audio Codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.2.1 Supported MP3 (MPEG layer III) Formats . . . . . . . . . . . . . . . . . . . . 22
8.2.2 Supported RIFF WAV Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.3 Data Flow of VS1002d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.4 Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.5 Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.6 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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CONTENTS
8.6.1 SCI MODE (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.6.2 SCI STATUS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.6.3 SCI BASS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.6.4 SCI CLOCKF (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.6.5 SCI DECODE TIME (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.6.6 SCI AUDATA (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.6.7 SCI WRAM (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.6.8 SCI WRAMADDR (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.6.9 SCI HDAT0 and SCI HDAT1 (R) . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.6.10 SCI AIADDR (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.6.11 SCI VOL (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.6.12 SCI AICTRL[x] (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9
Operation
33
9.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.2 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.4 SPI Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.5 Play/Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.6 Feeding PCM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.7 SDI Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.7.1 Sine Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.7.2 Pin Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.7.3 Memory Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.7.4 SCI Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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CONTENTS
10 VS1002d Registers
37
10.1 Who Needs to Read This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.2 The Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.3 VS1002d Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.4 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.5 Serial Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.6 DAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10.7 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10.8 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.9 A/D Modulator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.10Watchdog v1.0 2002-08-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.10.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.11UART v1.0 2002-04-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.11.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.11.2 Status UARTx STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.11.3 Data UARTx DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.11.4 Data High UARTx DATAH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.11.5 Divider UARTx DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.11.6 Interrupts and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.12Timers v1.0 2002-04-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.12.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.12.2 Configuration TIMER CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.12.3 Configuration TIMER ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.12.4 Timer X Startvalue TIMER Tx[L/H] . . . . . . . . . . . . . . . . . . . . . . . 47
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10.12.5 Timer X Counter TIMER TxCNT[L/H] . . . . . . . . . . . . . . . . . . . . . . 47
10.12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.13System Vector Tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.13.1 AudioInt, 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.13.2 SciInt, 0x21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.13.3 DataInt, 0x22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.13.4 ModuInt, 0x23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.13.5 TxInt, 0x24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.13.6 RxInt, 0x25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.13.7 Timer0Int, 0x26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.13.8 Timer1Int, 0x27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.13.9 UserCodec, 0x0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.14System Vector Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.14.1 WriteIRam(), 0x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.14.2 ReadIRam(), 0x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.14.3 DataBytes(), 0x6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.14.4 GetDataByte(), 0x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.14.5 GetDataWords(), 0xa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.14.6 Reboot(), 0xc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11 VS1002 Version Changes
52
11.1 Changes Between VS1002c and VS1002d, 2004-05-13 . . . . . . . . . . . . . . . . . . 52
12 Document Version Changes
53
12.1 Version 1.0 for VS1002d, 2005-04-27 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.2 Version 0.71 for VS1002d, 2004-07-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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12.3 Version 0.70 for VS1002d, 2004-05-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.4 Version 0.62 for VS1002c, 2004-03-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.5 Version 0.61 for VS1002c, 2004-03-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.6 Version 0.6 for VS1002c, 2004-02-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13 Contact Information
54
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LIST OF FIGURES
List of Figures
1
2
3
4
5
6
7
8
9
Pin Configuration, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Configuration, BGA-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical Connection Diagram Using LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . 15
BSYNC Signal - one byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
BSYNC Signal - two byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SCI Word Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SCI Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Two SCI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10 Two SDI Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11 Two SDI Bytes Separated By an SCI Operation. . . . . . . . . . . . . . . . . . . . . . . 21
12 Data Flow of VS1002d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
13 ADPCM Frequency Responses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
14 User’s Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
15 RS232 Serial Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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1. LICENSE
1 License
MPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and Thomson.
2 Disclaimer
This is a preliminary datasheet. All properties and figures are subject to change.
3 Definitions
ASIC Application Specific Integrated Circuit.
B Byte, 8 bits.
b Bit.
IC Integrated Circuit.
Ki “Kibi” = 10 = 1024 (IEC 60027-2).
Mi “Mebi” = 20 = 1048576 (IEC 60027-2).
VS DSP VLSI Solution’s DSP core.
W Word. In VS DSP, instruction words are 32-bit and data words are 16-bit wide.
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4. CHARACTERISTICS & SPECIFICATIONS
4 Characteristics & Specifications
4.1 Absolute Maximum Ratings
Parameter
Symbol Min
Max
Unit
Analog Positive Supply
Digital Positive Supply
Current at Any Digital Output
Voltage at Any Digital Input 2
Operating Temperature
Storage Temperature
AVDD -0.3
DVDD -0.3
3.6
3.6
±50
V
V
mA
V
◦C
◦C
-0.3 DVDD+0.31
-40
-65
+85
+150
1 Must not exceed 3.6 V
2 Current must be limited to ± mA
4.2 Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max Unit
Ambient Operating Temperature
Analog and Digital Ground 1
Positive Analog
-40
+85
◦C
AGND DGND
AVDD
0.0
2.7
2.7
V
2.5
2.3
3.6
3.6
26
13
26
V
V
MHz
MHz
MHz
Positive Digital
DVDD
Input Clock Frequency
Input Clock Frequency, with clock doubler
Internal Clock Frequency
Internal Clock Frequency, DVDD
Master Clock Duty Cycle
XTALI
XTALI
CLKI
24 24.576
12 12.288
242 24.576
242
V
CLKI
28.636 MHz
60
40
50
%
1 Must be connected together as close to the device as possible for latch-up immunity.
2 The maximum sample rate that can be played with correct speed is CLKI/512.
Thus, if CLKI is 24 MHz, 48 kHz is played 2.5% off-pitch.
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4. CHARACTERISTICS & SPECIFICATIONS
4.3 Analog Characteristics
Unless otherwise noted: AVDD=2.5..3.6V, DVDD=2.3..3.6V, TA=-40..+85◦C, XTALI=12..13MHz,
internal Clock Doubler active. DAC tested with 1307.894 Hz full-scale output sinewave, measurement
bandwidth 20..20000 Hz, analog output load: LEFT to GBUF 30 , RIGHT to GBUF 30 . Microphone
test amplitude 100 mVpp, f=1 kHz.
Parameter
Symbol Min Typ Max Unit
DAC Resolution
Total Harmonic Distortion
18
0.1
90
85
75
40
bits
%
dB
dB
dB
dB
THD
IDR
SNR
0.2
Dynamic Range (DAC unmuted, A-weighted)
S/N Ratio (full scale signal)
Interchannel Isolation (Cross Talk), AC-coupled
Interchannel Isolation (Cross Talk), with GBUF
Interchannel Gain Mismatch
Frequency Response 20 Hz..15000 Hz
Frequency Response 15000 Hz..19000 Hz
Full Scale Output Voltage (Peak-to-peak)
Deviation from Linear Phase
Analog Output Load Resistance
Analog Output Load Capacitance
Microphone input impedance
70
50
-0.5
-0.2
-1.0
0.5 dB
0.2 dB
-0.2 dB
2.0 Vpp
1.4 1.61
◦
5
AOLR
16
302
100 pF
k
100
Microphone input amplitude
1003 280 mVpp AC
Microphone Total Harmonic Distortion
Microphone S/N Ratio
MTHD
MSNR
0.03 0.10
82
%
dB
70
1 3.2 volts can be achieved with +-to-+ wiring for mono difference sound.
2 AOLR may be much lower, but below Typical distortion performance may be compromised.
3 100 mVpp is optimum level. Above typical amplitude the Harmonic Distortion increases.
4.4 Power Consumption
Average current tested with an MPEG 1.0 Layer III 128 kbit/s sample and generated sine, output at full
volume, XTALI = 12.288 MHz, internal clock doubler enabled, DVDD = 2.7 V, AVDD = 2.7 V.
Parameter
Min Typ Max Unit
Power Supply Consumption AVDD, Reset
Power Supply Consumption DVDD, Reset
0.6
3.7 10.0
5.0
A
A
Power Supply Consumption AVDD, sine test, 30 + GBUF
Power Supply Consumption DVDD, sine test
22
9
30
18
mA
mA
Power Supply Consumption AVDD, no load
Power Supply Consumption AVDD, output load 30
Power Supply Consumption AVDD, 30 + GBUF
Power Supply Consumption DVDD
6
mA
mA
mA
mA
10
16
19
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4. CHARACTERISTICS & SPECIFICATIONS
4.5 Digital Characteristics
Parameter
Symbol
Min
Typ
Max
DVDD+0.31
Unit
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage at I = -2.0 mA
Low-Level Output Voltage at I = 2.0 mA
Input Leakage Current
SPI Input Clock Frequency 2
×DVDD
V
V
V
V
A
MHz
ns
-0.2
×DVDD
×DVDD
×DVDD
-1.0
1.0
6
50
Rise time of all output pins, load = 50 pF
1 Must not exceed 3.6V
2 Value for SCI reads. SCI and SDI writes allow
.
4
4.6 Switching Characteristics - Boot Initialization
Parameter
Symbol Min
Max
Unit
XTALI
XRESET active time
XRESET inactive to software ready
Power on reset, rise time of DVDD
2
500001 XTALI
V/s
10
1 DREQ rises when initialization is complete. You should not send any data or commands before that.
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5. PACKAGES AND PIN DESCRIPTIONS
5 Packages and Pin Descriptions
5.1 Packages
Both LPQFP-48 and BGA-49 are lead (Pb) free and also RoHS compliant packages. RoHS is a short
name of Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical
and electronic equipment.
5.1.1 LQFP-48
48
1
Figure 1: Pin Configuration, LQFP-48.
LQFP-48 package dimensions are at http://www.vlsi.fi/ .
5.1.2 BGA-49
A1 BALL PAD CORNER
4
5
3
6
7
1
2
A
B
C
D
E
F
G
1.10 REF
0.80 TYP
4.80
7.00
TOP VIEW
Figure 2: Pin Configuration, BGA-49.
BGA-49 package dimensions are at http://www.vlsi.fi/ .
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5. PACKAGES AND PIN DESCRIPTIONS
5.2 LQFP-48 and BGA-49 Pin Descriptions
Pin Name
LQFP- BGA49 Pin
48 Pin Ball Type
Function
MICP2
1
2
3
4
6
8
9
C3
C2
B1
D2
D3
E2
E1
AI
AI
DI
PWR
PWR
DO
DI
microphone input, use pull-down resistor if not used
microphone input, use pull-down resistor if not used
active low asynchronous reset
digital ground
digital power supply
data request output
general purpose IO 2 / serial input data bus clock, use
pull-down resistor if not used
general purpose IO 3 / serial data input, use pull-down
resistor if not used
MICN2
XRESET
DGND0
DVDD0
DREQ
GPIO22 / DCLK1
GPIO32 / SDATA1 10
F2
DI
XDCS / BSYNC1
DVDD1
DGND1
XTALO
XTALI
DVDD2
DGND2
DGND3
DGND4
XCS
13
14
16
17
18
19
20
21
22
23
26
27
28
29
30
32
E3
F3
F4
G3
E4
F5
F6
F6
F6
G6
E6
F7
D6
E7
D5
C6
C7
B6
C5
B5
A6
B4
A5
C4
A4
B3
A3
B2
A2
DI
data chip select / byte sync
digital power supply
digital ground
crystal output
crystal input
digital power supply
digital ground (in BGA-49, DGND2, 3, 4 conn. together)
digital ground
PWR
PWR
AO
AI
PWR
PWR
PWR
PWR
DI
DI
DO
DI
DI
digital ground
chip select input (active low)
UART receive, use pull-up resistor if not used
UART transmit
clock for serial bus
serial input
RX
TX
SCLK
SI
SO
TEST
DO3
DI
serial output
reserved for test, connect to DVDD
general purpose IO 0, use 100 k pull-down resistor
general purpose IO 1, use pull-down resistor if not used
analog ground, low-noise reference
analog power supply
right channel output
analog ground
analog ground
virtual ground for audio output, 1.23 V nominal
analog power supply
SPIBOOT / GPIO03 33
DIO
DIO
PWR
PWR
AO
PWR
PWR
AO
PWR
AIO
PWR
AO
GPIO12
AGND0
AVDD0
RIGHT
AGND1
AGND2
GBUF
34
37
38
39
40
41
42
43
44
45
46
47
AVDD1
RCAP
AVDD2
LEFT
filtering capacitance for reference
analog power supply
left channel output
AGND3
PWR
analog ground
1
2
3
First pin function is active in New Mode, latter in Compatibility Mode.
If not used, use 100 kΩ pull-down resistor.
Unless pull-down resistor is used, SPI Boot is tried. See Chapter 9.4 for details.
Type Description
Type Description
DI
Digital input, CMOS Input Pad
AI
Analog input
DO
DIO
Digital output, CMOS Input Pad
Digital input/output
AO
AIO
Analog output
Analog input/output
DO3 Digital output, CMOS Tri-stated Output Pad
PWR Power supply pin
In BGA-49, no-connect balls are A1, A7, B7, C1, D1, D4, D7, E5, F1, G1, G2, G7.
In LQFP-48, no-connect pins are 5, 7, 11, 12, 15, 24, 25, 31, 35, 36, 48.
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6. CONNECTION DIAGRAM, LQFP-48
6 Connection Diagram, LQFP-48
Figure 3: Typical Connection Diagram Using LQFP-48.
The ground buffer GBUF can be used for common voltage (1.23 V) for earphones. This will eliminate
the need for large isolation capacitors on line outputs, and thus the audio output pins from VS1002d may
be connected directly to the earphone connector.
If GBUF is not used, LEFT and RIGHT must be provided with 1-100 F capacitors depending load
resistance.
If UART is not used, RX should connect to DVDD and TX be unconnected.
Note: This connection assumes SM SDINEW is active (see Chapter 8.6.1). If also SM SDISHARE is
used, xDCS should have a pull-up resistor (see Chapter 7.2.1).
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7. SPI BUSES
7 SPI Buses
7.1 General
The SPI Bus - that was originally used in some Motorola devices - has been used for both VS1002d’s
Serial Data Interface SDI (Chapters 7.4 and 8.4) and Serial Control Interface SCI (Chapters 7.5 and 8.5).
7.2 SPI Bus Pin Descriptions
7.2.1 VS1002 Native Modes (New Mode)
These modes are active when SM SDINEW is set to 1 (default at startup). DCLK, SDATA and BSYNC
are replaced with GPIO2, GPIO3 and XDCS, respectively.
SDI Pin SCI Pin Description
XDCS
XCS
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state. If SM SDISHARE is 1, pin
XDCS is not used, but the signal is generated internally by inverting
XCS.
SCK
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written.
Serial input. If a chip select is active, SI is sampled on the rising CLK edge.
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
SI
-
SO
7.2.2 VS1001 Compatibility Mode
This mode is active when SM SDINEW is set to 0. In this mode, DCLK, SDATA and BSYNC are active.
SDI Pin SCI Pin Description
-
XCS
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state. There is no chip select for SDI, which
is always active.
BSYNC
DCLK
-
SDI data is synchronized with a rising edge of BSYNC.
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written.
Serial input. SI is sampled on the rising SCK edge, if XCS is low.
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
SDATA
-
SI
SO
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7. SPI BUSES
7.3 Data Request Pin DREQ
The DREQ pin/signal is used to signal if VS1002d’s FIFO is capable of receiving data. If DREQ is high,
VS1002d can take at least 32 bytes of SDI data or one SCI command. When these criteria are not met,
DREQ is turned low, and the sender should stop transferring new data.
Because of the 32-byte safety area, the sender may send upto 32 bytes of SDI data at a time without
checking the status of DREQ, making controlling VS1002d easier for low-speed microcontrollers.
Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ should
only be used to decide whether to send more bytes. It should not abort a transmission that has already
started.
7.4 Serial Protocol for Serial Data Interface (SDI)
7.4.1 General
The serial data interface operates in slave mode so the DCLK signal must be generated by an external
circuit.
Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 8.6).
VS1002d assumes its data input to be byte-sychronized. SDI bytes may be transmitted either MSb or
LSb first, depending of contents of SCI MODE (Chapter 8.6.1).
The firmware is able to accept the maximum bitrate the SDI supports.
7.4.2 SDI in VS1002 Native Modes (New Mode)
In VS1002 native modes, byte synchronization is achieved by XDCS (or XCS if SM SDISHARE is 1).
The state of XDCS (or XCS) may not change while a data byte transfer is in progress. To always maintain
data synchronization even if there may be glitches in the boards using VS1002d, it is recommended to
turn XDCS (or XCS) every now and then, for instance once after every flash data block or a few kilobytes,
just to keep sure the host and VS1002d are in sync.
If SM SDISHARE is 1, the XDCS signal is internally generated by inverting the XCS input.
For new designs, using VS1002 native modes are recommended.
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7. SPI BUSES
7.4.3 SDI in VS1001 Compatibility Mode
BSYNC
SDATA
D7
D6
D5
D4
D3
D2
D1
D0
DCLK
Figure 4: BSYNC Signal - one byte transfer.
When VS1002d is running in VS1001 compatibility mode, a BSYNC signal must be generated to ensure
correct bit-alignment of the input bitstream. The first DCLK sampling edge (rising or falling, depending
on selected polarity), during which the BSYNC is high, marks the first bit of a byte (LSB, if LSB-first
order is used, MSB, if MSB-first order is used). If BSYNC is ’1’ when the last bit is received, the receiver
stays active and next 8 bits are also received.
BSYNC
SDATA
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
DCLK
Figure 5: BSYNC Signal - two byte transfer.
7.5 Serial Protocol for Serial Command Interface (SCI)
7.5.1 General
The serial bus protocol for the Serial Command Interface SCI (Chapter 8.5) consists of an instruction
byte, address byte and one 16-bit data word. Each read or write operation can read or write a single
register. Data bits are read at the rising edge, so the user should update data at the falling edge. Bytes are
always send MSb firrst.
The operation is specified by an 8-bit instruction opcode. The supported instructions are read and write.
See table below.
Instruction
Name
Opcode
Operation
READ
0b0000 0011 Read data
WRITE 0b0000 0010 Write data
Note: After sending an SCI command, it is not allowed to send SCI or SDI data for 5 microseconds.
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7. SPI BUSES
7.5.2 SCI Read
VS1002d registers are read by the following sequence, as shown in Figure 6. First, XCS line is pulled
low to select the device. Then the READ opcode (0x3) is transmitted via the SI line followed by an 8-bit
word address. After the address has been read in, any further data on SI is ignored. The 16-bit data
corresponding to the received address will be shifted out onto the SO line.
XCS should be driven high after data has been shifted out.
XCS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
30 31
SCK
3
2
1
0
SI
don’t care
data out
don’t care
0
0
0
0
0
0
1
1
0
0
0
0
instruction (read)
address
15 14
1
0
SO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
Figure 6: SCI Word Read
7.5.3 SCI Write
VS1002d registers are written to using the following sequence, as shown in Figure 7. First, XCS line is
pulled low to select the device. Then the WRITE opcode (0x2) is transmitted via the SI line followed by
an 8-bit word address.
After the word has been shifted in and the last clock has been sent, XCS should be pulled high to end the
WRITE sequence.
XCS
0
0
0
1
2
3
4
5
6
1
0
7
0
0
8
0
0
9
0
0
10 11 12 13 14 15 16 17
30 31
SCK
15 14
1
0
3
2
1
0
X
SI
0
0
0
0
0
0
0
data out
instruction (write)
address
X
SO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7: SCI Word Write
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7. SPI BUSES
7.6 SPI Timing Diagram
tWL tWH
tXCSH
tXCSS
XCS
tXCS
30
0
1
14
15
16
31
SCK
SI
tH
tSU
SO
tZ
tV
tDIS
Figure 8: SPI Timing Diagram.
Symbol Min
Max Unit
tXCSS
tSU
tH
5
-26
2
ns
ns
XTALI cycles
tZ
0
2
2
ns
XTALI cycles
XTALI cycles
2 (+ 25ns1) XTALI cycles
ns
tWL
tWH
tV
tXCSH
tXCS
tDIS
-26
2
XTALI cycles
10 ns
1 25ns is when pin loaded with 100pF capacitance. The time is shorter with lower capacitance.
Note: As tWL and tWH, as well as tH require at least 2 clock cycles, the maximum speed for the SPI
bus that can easily be used is 1/6 of VS1011’s external clock speed XTALI. Slightly higher speed can be
achieved with very careful timing tuning. For details, see Application Notes for VS10XX.
Note: Negative numbers mean that the signal can change in different order from what is shown in the
diagram.
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7. SPI BUSES
7.7 SPI Examples with SM SDINEW and SM SDISHARED set
7.7.1 Two SCI Writes
SCI Write 1
SCI Write 2
XCS
0
1
2
3
30
31
32
33
61
62
63
SCK
1
0
2
1
0
SI
0
0
0
0
X
0
0
X
Figure 9: Two SCI Operations.
Figure 9 shows two consecutive SCI operations. Note that xCS must be raised to inactive state between
the writes.
7.7.2 Two SDI Bytes
SDI Byte 1
SDI Byte 2
XCS
0
1
2
3
6
7
8
9
13
14
15
SCK
7
6
5
4
3
1
0
7
6
5
2
1
0
SI
X
Figure 10: Two SDI Bytes.
SDI data is synchronized with a raising edge of xCS as shown in Figure 10. However, every byte doesn’t
need separate synchronization.
7.7.3 SCI Operation in Middle of Two SDI Bytes
SDI Byte
SDI Byte
SCI Operation
XCS
0
1
6
7
8
9
38
39
40
41
46
47
SCK
7
6
5
1
0
1
0
7
6
5
1
0
X
SI
0
0
Figure 11: Two SDI Bytes Separated By an SCI Operation.
Figure 11 shows how an SCI operation is embedded in between SDI operations. The changes in xCS are
used to synchronize both SDI and SCI.
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8. FUNCTIONAL DESCRIPTION
8 Functional Description
8.1 Main Features
VS1002d is based on a proprietary digital signal processor, VS DSP. It contains all the code and data
memory needed for MP3 and WAV PCM + ADPCM audio decoding, together with serial interfaces, a
multirate stereo audio DAC and analog output amplifiers and filters. Also ADPCM audio encoding is
supported using a microphone amplifier and A/D converter. A UART is provided for debugging purposes.
VS1002d can play all MPEG 1.0 and 2.0 layer III files, with all sample rates and bitrates, including
variable bitrate (VBR).
8.2 Supported Audio Codecs
Conventions
Mark Description
+
-
Format is supported
Format exists but is not supported
Format doesn’t exist
8.2.1 Supported MP3 (MPEG layer III) Formats
MPEG 1.01:
Samplerate / Hz
Bitrate / kbit/s
32
40
48
56
64
80
96
112 128 160 192 224 256 320
3
3
48000
44100
32000
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
3
MPEG 2.01:
Samplerate / Hz
Bitrate / kbit/s
8
16
24
32
40
48
56
64
80
96
112 128 144 160
24000
22050
16000
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
MPEG 2.51 2
:
Samplerate / Hz
Bitrate / kbit/s
8
16
24
32
40
48
56
64
80
96
112 128 144 160
12000
11025
8000
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
1 Also all variable bitrate (VBR) formats are supported.
2 Incompatibilities may occur because MPEG 2.5 is not a standard format.
3 Nominal CLKI=24.576 MHz may be too little for glitchless playback.
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8. FUNCTIONAL DESCRIPTION
8.2.2 Supported RIFF WAV Formats
The most common RIFF WAV subformats are supported.
Format Name
Supported Comments
0x01
0x02
0x03
0x06
0x07
0x10
0x11
0x15
0x16
0x30
0x31
0x3b
0x3c
0x40
0x41
0x50
0x55
0x64
0x65
PCM
ADPCM
IEEE FLOAT
ALAW
MULAW
OKI ADPCM
IMA ADPCM
DIGISTD
DIGIFIX
DOLBY AC2
GSM610
ROCKWELL ADPCM
ROCKWELL DIGITALK
G721 ADPCM
G728 CELP
MPEG
MPEGLAYER3
G726 ADPCM
G722 ADPCM
+
-
-
-
-
-
+
-
-
-
-
-
-
-
-
-
+
-
-
16 and 8 bits, any sample rate ≤ 48kHz
Any sample rate ≤ 48kHz, mono only
For supported MP3 modes, see Chapter 8.2.1
8.3 Data Flow of VS1002d
SCI_BASS = 0
A1ADDR = 0
L
SDI
MP3/PlusV/
WAV/ADPCM
decoding
Bitstream
FIFO
Bass
enhancer
User
application
Volume
control
Audio
FIFO
S.rate.conv.
and DAC
R
16384 bits
SCI_BASS != 0
A1ADDR != 0
SCI_VOL
512 stereo
samples
SM_ADPCM=0
Figure 12: Data Flow of VS1002d.
First, depending on the audio data, and provided ADPCM encoding mode is not set, MP3, PCM WAV or
mono IMA ADPCM WAV data is received and decoded from the SDI bus.
After decoding, data may be sent to the Bass Enhancer depending on SCI BASS.
Then, if SCI AIADDR is non-zero, application code is executed from the address pointed to by that
register. For more details, see Application Notes for VS10XX.
After the optional user application, the signal is fed to the volume control unit, which also copies the
data to the Audio FIFO.
The Audio FIFO holds the data, which is read by the Audio interrupt (Chapter 10.13.1) and fed to the
sample rate converter and DACs. The size of the audio FIFO is 512 stereo (2×16-bit) samples.
The sample rate converter converts all different sample rates to CLKI/512 and feeds the data to the DAC,
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8. FUNCTIONAL DESCRIPTION
which in order creates a stereo in-phase analog signal. This signal is then forwarded to the earphone
amplifier.
8.4 Serial Data Interface (SDI)
The serial data interface is meant for transferring compressed MP3 audio data as well as WAV PCM and
ADPCM data.
If the input of the decoder is invalid or it is not received fast enough, analog outputs are automatically
muted.
Also several different tests may be activated through SDI as described in Chapter 9.
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8. FUNCTIONAL DESCRIPTION
8.5 Serial Control Interface (SCI)
The serial control interface is compatible with the SPI bus specification. Data transfers are always 16
bits. VS1002d is controlled by writing and reading the registers of the interface.
The main controls of the control interface are:
• control of the operation mode
• uploading user programs
• access to header data
• status information
• access to encoded digital data
8.6 SCI Registers
SCI registers, prefix SCI , offset 0xC000
Reg Type Reset Abbrev[bits]
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
rw
rw
rw
rw
r
rw
rw
rw
r
0x800 MODE
0x2C1 STATUS
Mode control.
Status of VS1002d.
Built-in bass enhancer.
Clock freq + doubler.
Decode time in seconds.
Misc. audio data.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BASS
CLOCKF
DECODE TIME
AUDATA
WRAM
WRAMADDR
HDAT0
HDAT1
AIADDR
VOL
AICTRL0
AICTRL1
AICTRL2
AICTRL3
RAM write.
Base address for RAM write.
Stream header data 0.
Stream header data 1.
Start address of application.
Volume control.
Application control register 0.
Application control register 1.
Application control register 2.
Application control register 3.
r
rw
rw
rw
rw
rw
rw
1 Firmware changes the value of this register immediately to 0x28, and in less than 100 ms to 0x20.
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8. FUNCTIONAL DESCRIPTION
8.6.1 SCI MODE (RW)
SCI MODE is used to control operation of VS1002d. Note that this register is not reset to 0, but to
0x0800 (i.e. SM SDINEW is set).
Bit Name
SM DIFF
Function
Value Description
normal in-phase audio
0
1
2
3
4
5
6
7
8
9
Differential
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
left channel inverted
right
wrong
no reset
reset
SM SETTOZERO Set to zero
SM RESET
Soft reset
SM OUTOFWAV Jump out of WAV decoding
no
yes
SM PDOWN
SM TESTS
SM STREAM
SM PLUSV
SM DACT
Powerdown
power on
powerdown
not allowed
allowed
no
yes
no
yes
rising
falling
MSb first
MSb last
no
yes
no
yes
no
Allow SDI tests
Stream mode
MP3+V active
DCLK active edge
SDI bit order
SM SDIORD
10 SM SDISHARE
11 SM SDINEW
12 SM ADPCM
Share SPI chip select
VS1002 native SPI modes
ADPCM recording active
ADPCM high-pass filter active
yes
no
yes
13 SM ADPCM HP
When SM DIFF is set, the player inverts the left channel output. For a stereo input this creates a virtual
surround, and for a mono input this effectively creates a differential left/right signal.
By setting SM RESET to 1, the player is software reset. This bit clears automatically.
When the user decoding a WAV file wants to get out of the file without playing it to the end, set
SM OUTOFWAV, and send zeros to VS1002d until SM OUTOFWAV is again zero. If the user doesn’t
want to check SM OUTOFWAV, send 128 zeros.
Bit SM PDOWN sets VS1002d into software powerdown mode. During powerdown, no audio is played
and no SDI operations are performed. For best results, set SCI VOL to 0xFFFF before activating soft-
ware powerdown. Note that software powerdown is not nearly as power efficient as hardware powerdown
activated with the XRESET pin.
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If SM TESTS is set, SDI tests are allowed. For more details on SDI tests, look at Chapter 9.7.
SM STREAM activates VS1002d’s stream mode. In this mode, data should be sent with as even intervals
as possible (and preferable with data blocks of less than 512 bytes), and VS1002d makes every attempt
to keep its input buffer half full by changing its playback speed upto 5%. For best quality sound, the
average speed error should be within 0.5%, the bitrate should not exceed 160 kbit/s and VBR should not
be used. For details, see Application Notes for VS10XX.
SM PLUSV activates MP3+V decoding. Without this bit set, only MP3 decoding is performed even for
files with additional PlusV data.
SM DACT defines the active edge of data clock for SDI. If clear data is read at the rising edge, and if set
data is read at the falling edge.
When SM SDIORD is clear, bytes on SDI are sent as a default MSb first. By setting SM SDIORD, the
user may reverse the bit order for SDI, i.e. bit 0 is received first and bit 7 last. Bytes are, however, still
sent in the default order. This register bit has no effect on the SCI bus.
Setting SM SDISHARE makes SCI and SDI share the same chip select, as explained in Chapter 7.2, if
also SM SDINEW is set.
Setting SM SDINEW will activate VS1002 native serial modes as described in Chapters 7.2.1 and 7.4.2.
Note, that this bit is set as a default when VS1002d is started up.
By activating SM ADPCM and SM RESET at the same time, the user will activate IMA ADPCM record-
ing mode. More information is available in document Application Notes for VS10XX.
If SM ADPCM HP is set at the same time as SM ADPCM and SM RESET, ADPCM mode will start
with a high-pass filter. This may help intelligibility of speech when there is lots of background noise.
The difference created to the ADPCM encoder frequency response is as shown in Figure 13.
VS1002 AD Converter with and Without HP Filter
5
No High−Pass
High−Pass
0
−5
−10
−15
−20
0
500
1000
1500
2000
2500
3000
3500
4000
Frequency / Hz
Figure 13: ADPCM Frequency Responses.
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8. FUNCTIONAL DESCRIPTION
8.6.2 SCI STATUS (RW)
SCI STATUS contains information on the current status of VS1002d and lets the user shutdown the chip
without audio glitches.
Name
Bits Description
SS VER
6..4 Version
SS APDOWN2
SS APDOWN1
SS AVOL
3
2
Analog driver powerdown
Analog internal powerdown
1..0 Analog volume control
SS VER is 0 for VS1001, 1 for VS1011, 2 for VS1002 and 3 for vs1003.
SS APDOWN2 controls analog driver powerdown. Normally this bit is controlled by the system firmware.
However, if the user wants to powerdown VS1002d with a minimum power-off transient, turn this bit to
1, then wait for at least a few milliseconds before activating reset.
SS APDOWN1 controls internal analog powerdown. This bit is meant to be used by the system firmware
only.
SS AVOL is the analog volume control: 0 = -0 dB, 1 = -6 dB, 3 = -12 dB. This register is meant to be
used automatically by the system firmware only.
8.6.3 SCI BASS (RW)
Name
SB AMPLITUDE 7..4 Enhancement in 1 dB steps (0..15)
SB FREQLIMIT 3..0 Lower limit frequency in 10 Hz steps (2..15)
Bits Description
The Bass Enhancer VSBE is a powerful bass boosting DSP algorithm, which tries to take the most out
of the users earphones without causing clipping.
VSBE is activated when SB AMPLITUDE is set to non-zero. SB AMPLITUDE should be set to the
user’s preferences, and SB FREQLIMIT to roughly 1.5 times the lowest frequency the user’s audio
system can reproduce.
Note: Because VSBE tries to avoid clipping, it gives the best bass boost with dynamical music material,
or when the playback volume is not set to maximum.
8.6.4 SCI CLOCKF (RW)
SCI CLOCKF is used to tell if the input clock XTALI is running at something else than 24.576 MHz.
XTALI is set in 2 kHz steps. Thus, the formula for calculating the correct value for this register is
2000
(XTALI is in Hz). Values may be between 0..32767, although hardware limits the highest allowed speed.
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Also, with speeds lower than 24.576 MHz all sample rates and bitstream widths are no longer available.
Setting the MSB of SCI CLOCKF to 1 activates internal clock-doubling. A clock of upto 15 MHz may
be doubled depending on the voltage provided to the chip.
Note: SCI CLOCKF must be set before beginning decoding audio data; otherwise the sample rate will
not be set correctly.
Note: Unlike with VS1011, SCI CLOCKF only needs to be written to after a hardware reset.
26000000
2000
Example 1: For a 26 MHz clock the value would be
.
Example 2: For a 13 MHz external clock and using internal clock-doubling for a 26 MHz internal
13000000
2000
frequency, the value would be
.
24576000
2000
Example 3: For a 24.576 MHz clock the value would be either
, or just the default
value . For this clock frequency, SCI CLOCKF doesn’t need to be set.
8.6.5 SCI DECODE TIME (RW)
When decoding correct data, current decoded time is shown in this register in full seconds.
The user may change the value of this register. However, in that case the new value should be written
twice.
SCI DECODE TIME is reset at every software reset.
8.6.6 SCI AUDATA (RW)
When decoding correct data, the current sample rate and number of channels can be found in bits 15..1
and 0 of SCI AUDATA, respectively. Bits 15..1 contain the sample rate divided by two, and bit 0 is 0 for
mono data and 1 for stereo. Writing to this register will change the sample rate on the run to the number
given.
Example: 44100 Hz stereo data reads as 0xAC45 (44101).
8.6.7 SCI WRAM (RW)
SCI WRAM is used to upload application programs and data to instruction and data RAMs. The start
address must be initialized by writing to SCI WRAMADDR prior to the first call of SCI WRAM. As 16
bits of data can be transferred with one SCI WRAM write, and the instruction word is 32 bits long, two
consecutive writes are needed for each instruction word. The byte order is big-endian (i.e. MSBs first).
After each full-word write, the internal pointer is autoincremented.
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8. FUNCTIONAL DESCRIPTION
SM WRAMADDR Dest. addr.
Bits/
Description
Start... End
Start... End
Word
0x1380... 0x13FF
0x4780... 0x47FF
0x8030... 0x84FF
0x1380... 0x13FF 16
0x0780... 0x07FF 16
0x0030... 0x04FF 32
X data RAM
Y data RAM
Instruction RAM
8.6.8 SCI WRAMADDR (RW)
SCI WRAMADDR is used to set the program address for following SCI WRAM writes.
8.6.9 SCI HDAT0 and SCI HDAT1 (R)
For WAV files, SPI HDAT0 and SPI HDAT1 read as 0x7761, and 0x7665, respectively.
For MP3 files, SCI HDAT[0... 1] have the following content:
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8. FUNCTIONAL DESCRIPTION
Bit
Function
Value Explanation
2047 stream valid
HDAT1[15:5]
HDAT1[4:3]
syncword
ID
3
2
1
0
3
2
1
0
1
0
ISO 11172-3 1.0
MPG 2.0 (1/2-rate)
MPG 2.5 (1/4-rate)
MPG 2.5 (1/4-rate)
I
II
III
HDAT1[2:1]
HDAT1[0]
layer
reserved
No CRC
protect bit
CRC protected
ISO 11172-3
reserved
32/16/8 kHz
48/24/12 kHz
44/22/11 kHz
additional slot
normal frame
not defined
mono
HDAT0[15:12] bitrate
HDAT0[11:10] sample rate
3
2
1
0
1
0
HDAT0[9]
pad bit
HDAT0[8]
HDAT0[7:6]
private bit
mode
3
2
1
0
dual channel
joint stereo
stereo
HDAT0[5:4]
HDAT0[3]
extension
copyright
ISO 11172-3
copyrighted
free
original
copy
CCITT J.17
reserved
50/15 microsec
none
1
0
1
0
3
2
1
0
HDAT0[2]
original
HDAT0[1:0]
emphasis
When read, SCI HDAT0 and SCI HDAT1 contain header information that is extracted from MP3 stream
being currently being decoded. Right after resetting VS1002d, 0 is automatically written to both registers,
indicating no data has been found yet.
The “sample rate” field in SCI HDAT0 is interpreted according to the following table:
“sample rate” ID=3 / Hz ID=2 / Hz ID=0,1 / Hz
3
2
1
0
-
32000
48000
44100
-
16000
24000
22050
-
8000
12000
11025
The “bitrate” field in HDAT0 is read according to the following table:
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“bitrate” ID=3 / kbit/s ID=0,1,2 / kbit/s
15
14
13
12
11
10
9
forbidden
320
256
224
192
160
128
112
96
forbidden
160
144
128
112
96
80
64
56
8
7
6
80
48
5
64
40
4
56
32
3
48
24
2
40
16
1
32
8
0
-
-
8.6.10 SCI AIADDR (RW)
SCI AIADDR indicates the start address of the application code written earlier with SCI WRAMADDR
and SCI WRAM registers. If no application code is used, this register should not be initialized, or it
should be initialized to zero. For more details, see Application Notes for VS10XX.
8.6.11 SCI VOL (RW)
SCI VOL is a volume control for the player hardware. For each channel, a value in the range of 0 .. 255
may be defined to set its attenuation from the maximum volume level (in 0.5 dB steps). The left channel
value is then multiplied by 256 and the values are added. Thus, maximum volume is 0 and total silence if
0xFFFF. Example: for a volume of -2.0 dB for the left channel and -3.5 dB for the right channel: (4*256)
+ 7 = 0x407. Note, that at startup volume is set to full volume. Resetting the software does not reset the
volume setting.
Note: Setting the volume to total silence (255 for both left and right channels) will turn analog power
off.
8.6.12 SCI AICTRL[x] (RW)
SCI AICTRL[x] registers ( x=[0 .. 3] ) can be used to access the user’s application program.
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9. OPERATION
9 Operation
9.1 Clocking
VS1002d operates on a single, nominally 24.576 MHz fundamental frequency master clock. This clock
can be generated by external circuitry (connected to pin XTALI) or by the internal clock chrystal interface
(pins XTALI and XTALO). This clock is sufficient to support a high quality audio output for almost all
standard sample rates and bit-rates (see Application Notes for VS10XX).
9.2 Hardware Reset
When the XRESET -signal is driven low, VS1002d is reset and all the control registers and internal
states are set to the initial values. XRESET-signal is asynchronous to any external clock. The reset mode
doubles as a full-powerdown mode, where both digital and analog parts of VS1002d are in minimum
power consumption stage, and where clocks are stopped. Also XTALO and XTALI are grounded.
After a hardware reset (or at power-up), the user should set such basic software registers as SCI VOL
for volume (and SCI CLOCKF if the input clock is anything else than 24.576 MHz) before starting
decoding.
9.3 Software Reset
In some cases the decoder software has to be reset. This is done by activating bit 2 in SCI MODE register
(Chapter 8.6.1). Then wait for at least 2 s, then look at DREQ. DREQ will stay down for at least 6000
clock cycles, which means an approximate 250 s delay if VS1002d is run at 24.576 MHz. After DREQ
is up, you may continue playback as usual.
If you want to make sure VS1002d doesn’t cut the ending of low-bitrate data streams and you want to do
a software reset, it is recommended to feed 2048 zeros to the SDI bus after the file and before the reset.
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9. OPERATION
9.4 SPI Boot
If GPIO0 is set with a pull-up resistor to 1 at boot time, VS1002d tries to boot from external SPI memory.
SPI boot redefines the following pins:
Normal Mode SPI Boot Mode
GPIO0
GPIO1
DREQ
GPIO2
xCS
CLK
MOSI
MISO
The memory has to be an SPI Bus Serial EEPROM with 16-bit addresses (i.e. at least 1 KiB). The serial
speed used by VS1002d is 490 kHz with the nominal 24.576 MHz clock. The first three bytes in the
memory have to be 0x50 0x26, 0x48. The exact record format is explained in the Application Notes for
VS10XX.
9.5 Play/Decode
This is the normal operation mode of VS1002d. SDI data is decoded. Decoded samples are converted
to analog domain by the internal DAC. If there bad problems in the decoding process, the error flags of
SCI HDAT0 and SCI HDAT1 are set to 0 and analog outputs are muted.
When there is no input for decoding, VS1002d goes into idle mode (lower power consumption than
during decoding) and actively monitors the serial data input for valid data.
9.6 Feeding PCM data
VS1002d can be used as a PCM decoder by sending to it a WAV file header. If the length sent in the
WAV file is 0 or 0xFFFFFFF, VS1002d will stay in PCM mode indefinitely. 8-bit linear and 16-bit linear
audio is supported in mono or stereo.
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9. OPERATION
9.7 SDI Tests
There are several test modes in VS1002d, which allow the user to perform memory tests, SCI bus tests,
and several different sine wave tests.
All tests are started in a similar way: VS1002d is hardware reset, SM TESTS is set, and then a test
command is sent to the SDI bus. Each test is started by sending a 4-byte special command sequence,
followed by 4 zeros. The sequences are described below.
9.7.1 Sine Test
Sine test is initialized with the 8-byte sequence 0x53 0xEF 0x6E 0 0 0 0, where defines the sine test
to use. is defined as follows:
bits
Name Bits Description
7:5 Sample rate index
4:0 Sine skip speed
0
1
2
3
4
5
6
7
44100 Hz
48000 Hz
32000 Hz
22050 Hz
24000 Hz
16000 Hz
11025 Hz
12000 Hz
The frequency of the sine to be output can now be calculated from
×
.
128
Example: Sine test is activated with value 126, which is 0b01111110. Breaking to its components,
and thus
≈
.
, and thus the final sine frequency
30
128
×
.
To exit the sine test, send the sequence 0x45 0x78 0x69 0x74 0 0 0 0.
Note: Sine test signals go through the digital volume control, so it is possible to test channels separately.
9.7.2 Pin Test
Pin test is activated with the 8-byte sequence 0x50 0xED 0x6E 0x54 0 0 0 0. This test is meant for chip
production testing only.
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9. OPERATION
9.7.3 Memory Test
Memory test mode is initialized with the 8-byte sequence 0x4D 0xEA 0x6D 0x54 0 0 0 0. After this
sequence, wait for 200000 clock cycles. The result can be read from the SCI register SCI HDAT0, and
’one’ bits are interpreted as follows:
Bit(s) Meaning
15
Test finished
14..7 Unused
6
5
4
3
2
1
0
Mux test succeeded
Good I RAM
Good Y RAM
Good X RAM
Good I ROM
Good Y ROM
Good X ROM
Memory tests overwrite the current contents of the RAM memories.
9.7.4 SCI Test
Sci test is initialized with the 8-byte sequence 0x53 0x70 0xEE 0 0 0 0, where
number to test. The content of the given register is read and copied to SCI HDAT0. If the register to be
tested is HDAT0, the result is copied to SCI HDAT1.
−
is the register
Example: if is 48, contents of SCI register 0 (SCI MODE) is copied to SCI HDAT0.
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10. VS1002D REGISTERS
10 VS1002d Registers
10.1 Who Needs to Read This Chapter
User software is required when a user wishes to add some own functionality like DSP effects or tone
controls to VS1002d.
However, most users of VS1002d don’t need to worry about writing their own code, or about this chapter,
including those who only download software plug-ins from VLSI Solution’s Web site.
10.2 The Processor Core
VS DSP is a 16/32-bit DSP processor core that also had extensive all-purpose processor features. VLSI
Solution’s free VSKIT Software Package contains all the tools and documentation needed to write, sim-
ulate and debug Assembly Language or Extended ANSI C programs for the VS DSP processor core.
VLSI Solution also offers a full Integrated Development Environment VSIDE for full debug capabilities.
10.3 VS1002d Memory Map
VS1002d’s Memory Map is shown in Figure 14.
10.4 SCI Registers
SCI registers described in Chapter 8.6 can be found here between 0xC000..0xC00F. In addition to these
registers, there is one in address 0xC010, called SPI CHANGE.
SPI registers, prefix SPI
Reg Type Reset Abbrev[bits]
Description
0xC010
r
0
CHANGE[5:0]
Last SCI access address.
SPI CHANGE bits
Bits Description
1 if last access was a write cycle.
3:0 SPI address of last access.
Name
SPI CH WRITE
SPI CH ADDR
4
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10. VS1002D REGISTERS
Instruction (32−bit)
X (16−bit)
Y (16−bit)
0000
0030
0098
0000
0030
0098
System Vectors
Stack
Stack
User
Instruction
RAM
0500
0780
0800
0C00
1000
X DATA
RAM
Y DATA
RAM
0500
0780
0800
0C00
1000
User
Space
PlusV
Space
1380
1400
1800
1380
1400
1800
User
Space
4000
4000
Instruction
ROM
X DATA
ROM
Y DATA
ROM
6000
6000
7000
7000
C000
C000
Hardware
Register
Space
C100
C100
Figure 14: User’s Memory Map.
10.5 Serial Data Registers
SDI registers, prefix SER
Reg Type Reset Abbrev[bits]
Description
0xC011
0xC012
r
w
0
0
DATA
DREQ[0]
Last received 2 bytes, big-endian.
DREQ pin control.
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10. VS1002D REGISTERS
10.6 DAC Registers
DAC registers, prefix DAC
Reg Type Reset Abbrev[bits]
Description
0xC013
0xC014
0xC015
0xC016
rw
rw
rw
rw
0
0
0
0
FCTLL
FCTLH[4:0]
LEFT
DAC frequency control, 16 LSbs.
Clock doubler + DAC frequency control MSbs.
DAC left channel PCM value.
RIGHT
DAC right channel PCM value.
Every fourth clock cycle, an internal 26-bit counter is added to by DAC FCTLH[3:0] × 65536 + DAC FCTLL.
Whenever this counter overflows, values from DAC LEFT and DAC RIGHT are read and a DAC inter-
rupt is generated.
If DAC FCTL[4] is 1, the internal clock doubler is activated.
10.7 GPIO Registers
GPIO registers, prefix GPIO
Reg Type Reset Abbrev[bits]
Description
0xC017
0xC018
0xC019
rw
r
rw
0
0
0
DDR[3:0]
IDATA[3:0]
ODATA[3:0]
Direction.
Values read from the pins.
Values set to the pins.
GPIO DIR is used to set the direction of the GPIO pins. 1 means output. GPIO ODATA remembers its
values even if a GPIO DIR bit is set to input.
GPIO registers don’t generate interrupts.
Note: Bits 2 and 3 of GPIO DDR and GPIO ODATA are switched in prototypes VS1002b and VS1002c.
Thus, for example, writing 8 to both registers will set pin GPIO2 to 1 instead of GPIO3.
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10. VS1002D REGISTERS
10.8 Interrupt Registers
Interrupt registers, prefix INT
Reg Type Reset Abbrev[bits]
Description
0xC01A
0xC01B
0xC01C
0xC01D
rw
w
w
0
0
0
0
ENABLE[7:0]
GLOB DIS[-]
GLOB ENA[-]
COUNTER[4:0]
Interrupt enable.
Write to add to interrupt counter.
Write to subtract from interript counter.
Interrupt counter.
rw
INT ENABLE controls the interrupts. The control bits are as follows:
INT ENABLE bits
Name
Bits Description
INT EN TIM1
INT EN TIM0
INT EN RX
7
6
5
4
3
2
1
0
Enable Timer 1 interrupt.
Enable Timer 0 interrupt.
Enable UART RX interrupt.
Enable UART TX interrupt.
Enable AD modulator interrupt.
Enable Data interrupt.
INT EN TX
INT EN MODU
INT EN SDI
INT EN SCI
INT EN DAC
Enable SCI interrupt.
Enable DAC interrupt.
Note: It may take upto 6 clock cycles before changing INT ENABLE has any effect.
Writing any value to INT GLOB DIS adds one to the interrupt counter INT COUNTER and effectively
disables all interrupts. It may take upto 6 clock cycles before writing to this register has any effect.
Writing any value to INT GLOB ENA subtracts one from the interrupt counter (unless INT COUNTER
already was 0). If the interrupt counter becomes zero, interrupts selected with INT ENABLE are re-
stored. An interrupt routine should always write to this register as the last thing it does, because in-
terrupts automatically add one to the interrupt counter, but subtracting it back to its initial value is the
responsibility of the user. It may take upto 6 clock cycles before writing this register has any effect.
By reading INT COUNTER the user may check if the interrupt counter is correct or not. If the register
is not 0, interrupts are disabled.
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10. VS1002D REGISTERS
10.9 A/D Modulator Registers
Interrupt registers, prefix AD
Reg Type Reset Abbrev[bits]
Description
0xC01E
0xC01F
rw
rw
0
0
DIV
DATA
A/D Modulator divider.
A/D Modulator data.
AD DIV bits
Bits Description
Name
ADM POWERDOWN
ADM DIVIDER
15 1 in powerdown.
14:0 Divider.
ADM DIVIDER controls the AD converter’s sampling frequency. To gather one sample,
cycles are used ( is value of AD DIV). The lowest usable value is 4, which gives a 48 kHz sample rate
when CLKI is 24.576 MHz. When ADM POWERDOWN is 1, the A/D converter is turned off.
×
clock
AD DATA contains the latest decoded A/D value.
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10. VS1002D REGISTERS
10.10 Watchdog v1.0 2002-08-26
The watchdog consist of a watchdog counter and some logic. After reset, the watchdog is inactive.
The counter reload value can be set by writing to WDOG CONFIG. The watchdog is activated by writ-
ing 0x4ea9 to register WDOG RESET. Every time this is done, the watchdog counter is reset. Every
65536’th clock cycle the counter is decremented by one. If the counter underflows, it will activate vs-
dsp’s internal reset sequence.
Thus, after the first 0x4ea9 write to WDOG RESET, subsequent writes to the same register with the
same value must be made no less than every
×WDOG CONFIG clock cycles.
Once started, the watchdog cannot be turned off. Also, a write to WDOG CONFIG doesn’t change the
counter reload value.
After watchdog has been activated, any read/write operation from/to WDOG CONFIG or WDOG DUMMY
will invalidate the next write operation to WDOG RESET. This will prevent runaway loops from re-
setting the counter, even if they do happen to write the correct number. Writing a wrong value to
WDOG RESET will also invalidate the next write to WDOG RESET.
Reads from watchdog registers return undefined values.
10.10.1 Registers
Watchdog, prefix WDOG
Reg Type Reset Abbrev
Description
0xC020
0xC021
0xC022
w
w
w
0
0
0
CONFIG
RESET
DUMMY[-] Dummy register
Configuration
Clock configuration
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10. VS1002D REGISTERS
10.11 UART v1.0 2002-04-23
RS232 UART implements a serial interface using rs232 standard.
Start
bit
Stop
bit
D0
D4
D1
D2
D3
D5
D6
D7
Figure 15: RS232 Serial Interface Protocol
When the line is idling, it stays in logic high state. When a byte is transmitted, the transmission begins
with a start bit (logic zero) and continues with data bits (LSB first) and ends up with a stop bit (logic
high). 10 bits are sent for each 8-bit byte frame.
10.11.1 Registers
UART registers, prefix UARTx
Reg Type Reset Abbrev
Description
STATUS[3:0] Status
DATA[7:0] Data
DATAH[15:8] Data High
DIV Divider
0xC028
r
0
0
0
0
0xC029 r/w
0xC02A r/w
0xC02B r/w
10.11.2 Status UARTx STATUS
A read from the status register returns the transmitter and receiver states.
UARTx STATUS Bits
Name
Bits Description
UART ST RXORUN
UART ST RXFULL
UART ST TXFULL
UART ST TXRUNNING
3
2
1
0
Receiver overrun
Receiver data register full
Transmitter data register full
Transmitter running
UART ST RXORUN is set if a received byte overwrites unread data when it is transferred from the
receiver shift register to the data register, otherwise it is cleared.
UART ST RXFULL is set if there is unread data in the data register.
UART ST TXFULL is set if a write to the data register is not allowed (data register full).
UART ST TXRUNNING is set if the transmitter shift register is in operation.
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10. VS1002D REGISTERS
10.11.3 Data UARTx DATA
A read from UARTx DATA returns the received byte in bits 7:0, bits 15:8 are returned as ’0’. If there is
no more data to be read, the receiver data register full indicator will be cleared.
A receive interrupt will be generated when a byte is moved from the receiver shift register to the receiver
data register.
A write to UARTx DATA sets a byte for transmission. The data is taken from bits 7:0, other bits in the
written value are ignored. If the transmitter is idle, the byte is immediately moved to the transmitter shift
register, a transmit interrupt request is generated, and transmission is started. If the transmitter is busy,
the UART ST TXFULL will be set and the byte remains in the transmitter data register until the previous
byte has been sent and transmission can proceed.
10.11.4 Data High UARTx DATAH
The same as UARTx DATA, except that bits 8..15 are used.
10.11.5 Divider UARTx DIV
UARTx DIV Bits
Name
Bits Description
UART DIV D1
UART DIV D2
15:8 Divider 1 (0..255)
7:0 Divider 2 (6..255)
The divider is set to 0x0000 in reset. The ROM boot code must initialize it correctly depending on the
master clock frequency to get the correct bit speed. The second divider ( 2) must be from 6 to 255.
The communication speed
TX/RX speed in bps.
, where
)
2
is the master clock frequency, and is the
(
1+1)×(
Divider values for common communication speeds at 26 MHz master clock:
Example UART Speeds,
Comm. Speed [bps] UART DIV D1 UART DIV D2
4800
9600
85
42
42
51
42
25
1
63
63
42
26
21
26
226
226
14400
19200
28800
38400
57600
115200
0
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10. VS1002D REGISTERS
10.11.6 Interrupts and Operation
Transmitter operates as follows: After an 8-bit word is written to the transmit data register it will be
transmitted instantly if the transmitter is not busy transmitting the previous byte. When the transmission
begins a TX INTR interrupt will be sent. Status bit [1] informs the transmitter data register empty (or
full state) and bit [0] informs the transmitter (shift register) empty state. A new word must not be written
to transmitter data register if it is not empty (bit [1] = ’0’). The transmitter data register will be empty
as soon as it is shifted to transmitter and the transmission is begun. It is safe to write a new word to
transmitter data register every time a transmit interrupt is generated.
Receiver operates as follows: It samples the RX signal line and if it detects a high to low transition, a
start bit is found. After this it samples each 8 bit at the middle of the bit time (using a constant timer),
and fills the receiver (shift register) LSB first. Finally if a stop bit (logic high) is detected the data in
the receiver is moved to the reveive data register and the RX INTR interrupt is sent and a status bit[2]
(receive data register full) is set, and status bit[2] old state is copied to bit[3] (receive data overrun). After
that the receiver returns to idle state to wait for a new start bit. Status bit[2] is zeroed when the receiver
data register is read.
RS232 communication speed is set using two clock dividers. The base clock is the processor master
clock. Bits 15-8 in these registers are for first divider and bits 7-0 for second divider. RX sample
frequency is the clock frequency that is input for the second divider.
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10. VS1002D REGISTERS
10.12 Timers v1.0 2002-04-23
There are two 32-bit timers that can be initialized and enabled independently of each other. If enabled,
a timer initializes to its start value, written by a processor, and starts decrementing every clock cycle.
When the value goes past zero, an interrupt is sent, and the timer initializes to the value in its start value
register, and continues downcounting. A timer stays in that loop as long as it is enabled.
A timer has a 32-bit timer register for down counting and a 32-bit TIMER1 LH register for holding the
timer start value written by the processor. Timers have also a 2-bit TIMER ENA register. Each timer is
enabled (1) or disabled (0) by a corresponding bit of the enable register.
10.12.1 Registers
Timer registers, prefix TIMER
Reg Type Reset Abbrev
Description
0xC030 r/w
0xC031 r/w
0
0
CONFIG[7:0] Timer configuration
ENABLE[1:0] Timer enable
0xC034 r/w
0xC035 r/w
0xC036 r/w
0xC037 r/w
0xC038 r/w
0xC039 r/w
0xC03A r/w
0xC03B r/w
0
0
0
0
0
0
0
0
T0L
T0H
T0CNTL
T0CNTH
T1L
T1H
T1CNTL
T1CNTH
Timer0 startvalue - LSBs
Timer0 startvalue - MSBs
Timer0 counter - LSBs
Timer0 counter - MSBs
Timer1 startvalue - LSBs
Timer1 startvalue - MSBs
Timer1 counter - LSBs
Timer1 counter - MSBs
10.12.2 Configuration TIMER CONFIG
TIMER CONFIG Bits
Bits Description
7:0 Master clock divider
Name
TIMER CF CLKDIV
TIMER CF CLKDIV is the master clock divider for all timer clocks. The generated internal clock
frequency +1, where is the master clock frequency and is TIMER CF CLKDIV. Example:
With a 12 MHz master clock, TIMER CF DIV=3 divides the master clock by 4, and the output/sampling
12
3+1
clock would thus be
.
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10. VS1002D REGISTERS
10.12.3 Configuration TIMER ENABLE
TIMER ENABLE Bits
Bits Description
Enable timer 1
Enable timer 0
Name
TIMER EN T1
TIMER EN T0
1
0
10.12.4 Timer X Startvalue TIMER Tx[L/H]
The 32-bit start value TIMER Tx[L/H] sets the initial counter value when the timer is reset. The timer
interrupt frequency where is the master clock obtained with the clock divider (see Chap-
+1
ter 10.12.2 and is TIMER Tx[L/H].
Example: With a 12 MHz master clock and with TIMER CF CLKDIV=3, the master clock
.
3
If TIMER TH=0, TIMER TL=99, then the timer interrupt frequency
99+1
.
10.12.5 Timer X Counter TIMER TxCNT[L/H]
TIMER TxCNT[L/H] contains the current counter values. By reading this register pair, the user may get
knowledge of how long it will take before the next timer interrupt. Also, by writing to this register, a
one-shot different length timer interrupt delay may be realized.
10.12.6 Interrupts
Each timer has its own interrupt, which is asserted when the timer counter underflows.
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10. VS1002D REGISTERS
10.13 System Vector Tags
The System Vector Tags are tags that may be replaced by the user to take control over several decoder
functions.
10.13.1 AudioInt, 0x20
Normally contains the following VS DSP assembly code:
jmpi DAC_INT_ADDRESS,(i6)+1
The user may, at will, replace the first instruction with a
interrupt.
command to gain control over the audio
10.13.2 SciInt, 0x21
Normally contains the following VS DSP assembly code:
jmpi SCI_INT_ADDRESS,(i6)+1
The user may, at will, replace the instruction with a
command to gain control over the SCI interrupt.
10.13.3 DataInt, 0x22
Normally contains the following VS DSP assembly code:
jmpi SDI_INT_ADDRESS,(i6)+1
The user may, at will, replace the instruction with a
command to gain control over the SDI interrupt.
10.13.4 ModuInt, 0x23
Normally contains the following VS DSP assembly code:
jmpi MODU_INT_ADDRESS,(i6)+1
The user may, at will, replace the instruction with a
lator interrupt.
command to gain control over the AD Modu-
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10. VS1002D REGISTERS
10.13.5 TxInt, 0x24
Normally contains the following VS DSP assembly code:
jmpi EMPTY_INT_ADDRESS,(i6)+1
The user may, at will, replace the instruction with a
interrupt.
command to gain control over the UART TX
command to gain control over the UART
command to gain control over the Timer
command to gain control over the Timer
10.13.6 RxInt, 0x25
Normally contains the following VS DSP assembly code:
jmpi RX_INT_ADDRESS,(i6)+1
The user may, at will, replace the first instruction with a
RX interrupt.
10.13.7 Timer0Int, 0x26
Normally contains the following VS DSP assembly code:
jmpi EMPTY_INT_ADDRESS,(i6)+1
The user may, at will, replace the first instruction with a
0 interrupt.
10.13.8 Timer1Int, 0x27
Normally contains the following VS DSP assembly code:
jmpi EMPTY_INT_ADDRESS,(i6)+1
The user may, at will, replace the first instruction with a
1 interrupt.
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10. VS1002D REGISTERS
10.13.9 UserCodec, 0x0
Normally contains the following VS DSP assembly code:
jr
nop
If the user wants to take control away from the standard decoder, the first instruction should be replaced
with an appropriate command to user’s own code.
Unless the user is feeding MP3 data at the same time, the system activates the user program in less than
1 ms. After this, the user should steal interrupt vectors from the system, and insert user programs.
10.14 System Vector Functions
The System Vector Functions are pointers to some functions that the user may call to help implementing
his own applications.
10.14.1 WriteIRam(), 0x2
VS DSP C prototype:
void WriteIRam(register i0 u int16 *addr, register a1 u int16 msW, register a0 u int16 lsW);
This is the only supported way to write to the User Instruction RAM. This is because Instruction RAM
cannot be written when program control is in RAM. Thus, the actual implementation of this function is
in ROM, and here is simply a tag to that routine.
10.14.2 ReadIRam(), 0x4
VS DSP C prototype:
u int32 ReadIRam(register i0 u int16 *addr);
This is the only supported way to read from the User Instruction RAM. This is because Instruction RAM
cannot be read when program control is in RAM. Thus, the actual implementation of this function is in
ROM, and here is simply a tag to that routine.
A1 contains the MSBs and a0 the LSBs of the result.
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10. VS1002D REGISTERS
10.14.3 DataBytes(), 0x6
VS DSP C prototype:
u int16 DataBytes(void);
If the user has taken over the normal operation of the system by switching the pointer in UserCodec
to point to his own code, he may read data from the Data Interface through this and the following two
functions.
This function returns the number of data bytes that can be read.
10.14.4 GetDataByte(), 0x8
VS DSP C prototype:
u int16 GetDataByte(void);
Reads and returns one data byte from the Data Interface. This function will wait until there is enough
data in the input buffer.
10.14.5 GetDataWords(), 0xa
VS DSP C prototype:
void GetDataWords(register i0 y u int16 *d, register a0 u int16 n);
Read data byte pairs and copy them in big-endian format (first byte to MSBs) to . This function will
wait until there is enough data in the input buffer.
10.14.6 Reboot(), 0xc
VS DSP C prototype:
void Reboot(void);
Causes a software reboot.
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11. VS1002 VERSION CHANGES
11 VS1002 Version Changes
This chapter describes changes between different generations of VS1002.
11.1 Changes Between VS1002c and VS1002d, 2004-05-13
• ADPCM recording now works without software patches.
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12. DOCUMENT VERSION CHANGES
12 Document Version Changes
This chapter describes the most important changes to this document.
12.1 Version 1.0 for VS1002d, 2005-04-27
• RX should be connected to VDD if UART is not used.
• Limits updated
• Qualified production version
12.2 Version 0.71 for VS1002d, 2004-07-20
• Added instructions to add 100 k pull-down resistor to unused GPIOs to Chapter 5.2.
12.3 Version 0.70 for VS1002d, 2004-05-13
• Updated document for VS1002d.
• Removed SM JUMP.
12.4 Version 0.62 for VS1002c, 2004-03-24
• Redrew Figure 3 to include new microphone connection and serial port.
• Rewrote and clarified Chapter 8.2, Supported Audio Codecs.
12.5 Version 0.61 for VS1002c, 2004-03-11
• Added samplerate and bitrate tables to Chapter 8.6.9.
12.6 Version 0.6 for VS1002c, 2004-02-13
• A/D Modulator powerdown bit explained in (Chapter 10.9).
• Added BGA-49 to Packages and Pin Descriptions (Chapter 5).
• Added new Chapter 8.2, Supported Audio Codecs.
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13. CONTACT INFORMATION
13 Contact Information
VLSI Solution Oy
Hermiankatu 6-8 C
FIN-33720 Tampere
FINLAND
Fax: +358-3-316 5220
Phone: +358-3-316 5230
Email: sales@vlsi.fi
URL: http://www.vlsi.fi/
Note: If you have questions, first see the Frequently Asked Questions at http://www.vlsi.fi/ .
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