W42C31-09G [ETC]
Clock Driver ; 时钟驱动器\n
ETC 
W42C31-09
Spread Spectrum Frequency Timing Generator
to pass increasingly difficult EMI testing without resorting to
costly shielding or redesign.
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Generates a spread spectrum copy of the provided
input
• Integrated loop filter components
• Operates with a 3.3V or 5V supply
• Low-power CMOS design
• Available in 8-pin SOIC (Small Outline Integrated
Circuit)
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram shows a simple implementation.
Table 1. Frequency Spread Selection
W42C31-09
Input Frequency
(MHz)
Output Frequency
(MHz)
FS1
0
FS0
0
Overview
30 to 55
30 to 55
30 to 55
30 to 55
f
f
f
f
±0.625%
±1.25%
±2.5%
IN
IN
IN
IN
The W42C31-09 incorporates the latest advances in PLL
spread spectrum frequency synthesizer techniques. By fre-
quency modulating the output with a low-frequency carrier,
EMI is greatly reduced. Use of this technology allows systems
0
1
1
0
1
1
–3.75%
Simplified Block Diagram
Pin Configuration
VDD
SOIC
CLKIN
NC
SSON#
CLKOUT
FS0
1
2
3
4
8
7
6
5
GND
FS1
VDD
Oscillator or Reference
Input
Spread Spectrum
W42C31-09
Output
(EMI suppressed)
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
January 25, 2000, rev. *B
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W42C31-09
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
CLKOUT
7
O
Output Modulated Frequency: Frequency modulated copy of the unmodulated input
clock.
CLKIN
NC
1
2
8
I
I
I
External Reference Frequency Input
No Connect: This pin must be left unconnected.
SSON#
Spread Spectrum Control (Active LOW): Pulling this input signal LOW turns the
internal modulation waveform on. This pin has an internal pull-down resistor.
FS0:1
6, 4
I
Frequency Selection Bit 0: These pins select the frequency spreading
characteristics. Refer to Table 1. These pins have internal pull-up resistors.
VDD
GND
5
3
P
Power Connection: Connected to 3.3V or 5V power supply.
G
Ground Connection: This should be connected to the common ground plane.
Frequency Selection With SSFTG
Functional Description
In Spread Spectrum Frequency Timing Generation, EMI re-
The W42C31-09 uses a phase-locked loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
times the reference frequency. (Note: For the W42C31-09 the
output frequency is equal to the input frequency.) The unique
feature of the Spread Spectrum Frequency Timing Generator
is that a modulating waveform is superimposed at the input to
the VCO. This causes the VCO output to be slowly swept
across a predetermined frequency band.
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed, the modula-
tion percentage may be varied.
Using frequency select bits (FS1:0 pins), various spreading
percentages can be chosen (see Table 1).
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentages between ±0.5% and ±2.5% are most
common.
The W42C31 features the ability to select from various spread
spectrum characteristics. Selections specific to the
W42C31-09 are shown in Table 1. Other spreading character-
istics are available (see separate data sheets) or can be cre-
ated with a custom mask. Also, other devices in the W42C31
family offer frequency multiplication in addition to the spread
spectrum function. This will allow the use of less expensive
fundamental mode crystals.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
VDD
Clock Input
CLKOUT
Freq.
Divider
Q
Phase
Detector
Charge
Pump
Post
Dividers
Reference Input
(EMI suppressed)
VCO
Σ
Modulating
Waveform
Feedback
Divider
P
PLL
GND
Figure 1. System Block Diagram (Concept, not actual implementation)
2
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W42C31-09
Cypress frequency selection tables express the modulation
percentage in two ways. The first method displays the spread-
ing frequency band as a percent of the programmed average
output frequency, symmetric about the programmed average
frequency. This method is always shown using the expression
Spread Spectrum Frequency Timing
Generation
The benefits of using Spread Spectrum Frequency Timing
Generation are depicted in Figure 2. An EMI emission profile
of a clock harmonic is shown.
±
f
X
% in the frequency spread selection table.
Center
MOD
The second approach is to specify the maximum operating
frequency and the spreading band as a percentage of this fre-
quency. The output signal is swept from the lower edge of the
band to the maximum frequency. The expression for this ap-
Contrast the typical clock EMI with the Cypress Spread Spec-
trum Frequency Timing Generation EMI. Notice the spike in
the typical clock. This spike can make systems fail quasi-peak
EMI testing. The FCC and other regulatory agencies test for
peak emissions. With spread spectrum enabled, the peak en-
ergy is much lower (at least 8 dB) because the energy is
spread out across a wider bandwidth.
–
proach is f
X
%. Whenever this expression is used,
MAX
MOD
Cypress has taken care to ensure that f
will never be ex-
MAX
ceeded. This is important in applications where the clock
drives components with tight maximum clock speed specifica-
tions.
Modulating Waveform
The shape of the modulating waveform is critical to EMI reduc-
tion. The modulation scheme used to accomplish the maxi-
mum reduction in EMI is shown in Figure 3. The period of the
modulation is shown as a percentage of the period length
along the X axis. The amount that the frequency is varied is
shown along the Y axis, also shown as a percentage of the
total frequency spread.
SSON# Pin
An internal pull-down resistor defaults the chip into a spread
spectrum mode. The SSON# pin enables the spreading fea-
ture when set LOW. The SSON# pin disables the spreading
feature when set HIGH (V ).
DD
5dB/div
EMI Reduction
SSFTG
Typical Clock
Spread
Non-
Spread
Spectrum
Spectrum
Enabled
Frequency Span (MHz)
-SS%
+SS%
Figure 2. Typical Clock and SSFTG Comparison
100%
80%
60%
40%
20%
0%
–20%
–40%
–60%
–80%
–100%
Time
Figure 3. Modulation Waveform Profile
3
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W42C31-09
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Parameter
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
0 to +70
Unit
V
V
, V
DD IN
T
°C
°C
°C
W
STG
T
Operating Temperature
A
T
Ambient Temperature under Bias
Power Dissipation
–55 to +125
0.5
B
P
D
DC Electrical Characteristics: 0°C < T < 70°C, V = 3.3V ±10%
A
DD
Parameter
Description
Supply Current
Test Condition
Min
Typ
Max
Unit
mA
ms
I
t
18
32
5
DD
Power Up Time
First locked clockcycle after
Power Good
ON
V
V
V
V
V
V
(Logic Inputs)
(CLKIN)
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Capacitance
Input Pull-Up Resistor
0.8
.4
V
V
IL
IL
(Logic Inputs)
(CLKIN)
2.4
2.8
V
IH
IH
V
[1]
I
I
= 21.6 mA
= 31.5 mA
0.4
V
OL
OL
[1]
2.5
V
OH
OH
I
I
I
I
Note 2
Note 2
–100
µA
µA
mA
mA
pF
pF
kΩ
Ω
IL
10
IH
@ 0.4V, V = 3.3V
15
15
OL
OH
DD
@ 2.4V, V = 3.3V
DD
C
C
R
All pins except CLKIN
CLKIN pin only
7
I
6
10
I
500
25
P
Z
Clock Output Impedance
OUT
Notes:
1. Output driver is full CMOS.
2. Inputs FS1:0 have a pull-up resistor, Input SSON# has a pull-down resistor.
4
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W42C31-09
DC Electrical Characteristics: 0°C < T < 70°C, V = 5V ±10%
A
DD
Parameter
Description
Supply Current
Test Condition
Min
Typ
Max
45
5
Unit
mA
ms
I
t
30
DD
Power Up Time
First locked clockcycle after
Power Good
ON
V
V
V
V
V
V
(Logic Inputs)
(CLKIN)
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Capacitance
Input Pull-Up Resistor
0.15V
0.4
V
V
IL
DD
IL
(Logic Inputs)
(CLKIN)
0.7V
V
IH
IH
DD
4.2
V
I
I
= 25.7mA
= 118.mA
0.4
V
OL
OL
2.5
V
OH
OH
I
I
I
I
Note 2
Note 2
–100
µA
µA
mA
mA
pF
pF
kΩ
Ω
IL
10
IH
@ 0.4V, V = 5V
24
24
OL
OH
DD
@ 2.4V, V = 5V
DD
C
C
R
All pins except CLKIN
CLKIN pin only
7
I
6
10
I
500
25
P
Z
Clock Output Impedance
OUT
AC Electrical Characteristics: T = 0°C to +70°C, V = 3.3V±10%
A
DD
Symbol
Parameter
Input Frequency
Test Condition
Min
30
Typ
40
40
2
Max
Unit
f
Input Clock
55
55
5
MHz
MHz
ns
IN
f
t
t
t
t
t
Output Frequency
Output Rise Time
Output Fall Time
Spread Off
30
OUT
R
V, 15-pF load 0.8 – 2.4
V, 15-pF load 2.4 – 0.8
15-pF load
2
5
ns
F
Output Duty Cycle
Input Duty Cycle
40
40
60
60
300
%
OD
ID
%
Jitter, Cycle-to-Cycle
Harmonic Reduction
250
ps
JCYC
f
= 40 MHz, third harmonic
8
dB
out
measured, reference board,
15-pF load
AC Electrical Characteristics: T = 0°C to +70°C, V = 5V±10%
A
DD
Symbol
Parameter
Input Frequency
Test Condition
Min
30
Typ
40
40
2
Max
55
55
5
Unit
MHz
MHz
ns
f
Input Clock
IN
f
t
t
t
t
t
Output Frequency
Output Rise Time
Output Fall Time
Spread Off
30
OUT
R
V, 15-pF load 0.8 – 2.4
V, 15-pF load 2.4 – 0.8
15-pF load
2
5
ns
F
Output Duty Cycle
Input Duty Cycle
40
40
60
60
300
%
OD
ID
%
Jitter, Cycle-to-Cycle
Harmonic Reduction
250
ps
JCYC
f
= 40 MHz, third harmonic
8
dB
out
measured, reference board,
15-pF load
5
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W42C31-09
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
Application Information
Recommended Circuit Configuration
type. For further EMI protection, the V
made via a ferrite bead, as shown.
connection can be
DD
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
Recommended Board Layout
V
decoupling is important to both reduce phase jitter and
DD
Figure 5 shows a recommended 2-layer board layout.
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V
pin as possible, otherwise the in-
DD
Reference Input
1
2
3
4
8
7
6
5
NC
Clock Output
GND
R1
VDD
C1
0.1
µF
5V or 3.3V System Supply
FB
C2
10
µF Tantalum
Figure 4. Recommended Circuit Configuration
C1 =
C2 =
High frequency supply decoupling
µF recommended).
capacitor (0.1-
Common supply low frequency
µF tantalum
decoupling capacitor (10-
recommended).
R1 =
Match value to line impedance
Ferrite Bead
FB
=
G
=
Via To GND Plane
Reference Input
NC
R1
Clock Output
G
C1
G
G
C2
Power Supply Input
(3.3V or 5V)
FB
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Freq. Mask
Package
Name
Ordering Code
Code
Package Type
W42C31
09
G
8-pin Plastic SOIC (150-mil)
Document #: 38-00799-B
6
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W42C31-09
Package Diagram
8-Pin Small Outline Integrated Circuit (SOIC, 150-mil)
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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