W5360120P [ETC]
;
| 型号： | W5360120P |
| 厂家： | 
ETC |
| 描述： |
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| 文件： | 总10页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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GENERAL DESCRIPTION
The W536XXXP, a member of ViewTalkTM family, is a high-performance 4-bit micro-controller (uC)
with built-in 8KW uC program. The 4-bit uC core contains dual clock source, 4-bit ALU, two 8-bit
timers, one 14 bits divider, maximum 32 pads for input or output, 8 interrupt sources and 8-level
nesting for subroutine/interrupt applications. Speech unit, integrated as a single chip with maximum
128 seconds (based on 6.4K sample rate with 5 bits MDPCM) , is capable of expanding to 512
seconds speech addressed by external memory W55XXX with serial bus interface. It can be
implemented with Winbond Power Speech using MDPCM algorithm. Melody unit provides dual tone
output and can store up to 1k notes. Power reduction mode is also built in to minimize power
dissipation. It is ideal for educational toys, remote controllers and other application products which
incorporate both melody and speech.
Body
Voice
W536030P
30 sec
W536060P
60 sec
W536090P
90 sec
W536120P
120 sec
8I/O, 12I, 12O
(RA/RB/RC/RD/RE/RF (RA/RB/RC/RD/RE/RF
/RG/RH)
8I/O, 12I, 12O
I/O pad
8I/O, 8I
8I/O, 8I
(RA/RB/RC/RD) (RA/RB/RC/RD)
/RG/RH)
WDT disable/Enable
(Mask Option)
Sub-clock
RC/XTAL mode
(Mask Option)
Y
Y
Y
Y
Y
Y
Y
Y
Tri-state serial bus
(Mask Option)( 1)
Cascaded Voice
through serial bus (2)
Y
Y
Y
Y
Y
N
Y
Y
(1) Tri-state serial bus mask option can float serial bus while voice playing is no active. Let
this mask option is disabled to get minimum power consumption in general.
(2) Cascaded Voice ROM user option help to expand voice up to 512 sec through serial bus
by W55XXX chip.
FEATURESꢀ
•
•
•
Operating voltage: 2.4 volt ~ 5.5 volt
Watch dog disabled/enabled by mask option
Dual clock operating system
− Main clock with RC/Crystal (400 KHz to 4 MHz)
− Sub-clock with 32.768 KHz RC/Crystal by mask option
Memory
− Program ROM (P-ROM): 8 K × 20 (ROM Bank0)
− Data RAM (W-RAM): 1K × 4 bit
(RAM Bank 0 is 512 nibbles from 0:000~0:1FF and 0:380~0:3FF are mapped to special register.
RAM Bank F is 512 nibbles from F:200~F:3FF either data RAM or dedicated to script kernel )
Maximum 32 input/output pads
•
•
− Ports for input only: 12 pads (RC, RD and RG port ; RG for W536090P/120P only)
− Ports for output only: 12 pads (RE, RF and RH port; RH for W536090P/120P only)
− Ports for Input/output: 8 pads
Publication Release Date: April 2000
- 1 -
Revision A2
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•
•
Power-down mode
− Hold mode (except for 32kHz oscillator)
− Stop mode (including 32kHz oscillator and release by RD or RC port)
Eight types of interrupts
− Five internal interrupts (Divider, Timer 0, Timer 1, Speech, Melody )
− Three external interrupts (Port RC, RD, RA)
One built-in 14-bit clock frequency divider circuit
Two built-in 8-bit programmable countdown timers
− Timer 0: one of two clock sources (FOSC/4 or FOSC/1024) can be selected
− Timer 1: built-in auto-reload function includes internal timer, external event counter from
RC.0
•
•
•
•
•
•
Built-in 18/14-bit watchdog timer for system reset.
Powerful instruction sets.
8-level subroutine (including interrupt) nesting
Speech function
− Provided 1M / 2M/ 3M/ 4M bits Voice ROM for W536030P/060P/090P/120P based on 5 bits
MDPCM algorithm
− Voice ROM (V-ROM) available for uC data.
− Maximum 8*256 Label/Interrupt vector (voice section number) available
− Provide two types of speech busy flag to either each GO or each trigger
− Maximum up to 16M bits speech address capability interface with external memory W55XXX
through serial bus.
•
Melody function
− Provide 1K notes (22bits/note) dedicated melody ROM
− Provide two types of melody busy flag to uC either each note or each song
− Provide 6 kinds of beat, 16 kinds of tempo, and pitch range from G3# to C7
− Tremolo, triple frequency and 3 kinds of percussion available
− Maximum 31 songs available
•
•
•
•
Can mix speech with melody
Multi-engine controller
Direct driving speaker/buzzer or DAC output
Chip On Board available
Publication Release Date:April 2000
- 2 -
Revision A2
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BLOCK DIAGRAM
PORT RA
RA0~3
RB0~3
RAM
1K* 4Bit
TONE
PORT RB
PORT RC
PORT RD
PORT RE
RC0~3
RD0~3
ACC
ALU
ROM
8K*20Bit
RE0~3
RF0~3
PORT RF
PORT RG
PC
Special Register
RG0~3
RH0~3
IEF
HCF
HEF PEF
EVF
PORT RH
SPC MLD FLAG0
WRP
RDP
Parallel
to
Serial
STACK
(8 Levels)
FLAG1 PM0 MR0
LPX0 LPX1 LPX2
LPX4 LPX5 LPY0
PSR0
LPX3
LPY1
SPDATA
VDDA
SPC_busy
SPC_play
LPXY
Speech
MDPCM
core
ROSC
Shared_ROM Data
VSSA
VSSP
PWM1/DAC
PWM2
Interrupt ,Hold
& Stop Control
Voice ROM
(1M /2M/3M/4M
bits)
Timer 1
(8 Bit)
Timer 0
(8 Bit)
PWM/
DAC
Mix
MLD_busy
MLD_play
VDDP
VDD
Block
VSS
Dual Tone
Melody
(1K notes)
Divider
(14/10 Bit)
Watch Dog Timer
(18/14 Bit)
TEST
RES
Timing Generator
XIN XOUT X32I X32O
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Publication Release Date:April 2000
Revision A2
- 3 -
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PAD DESCRIPTION
SYMBOL
I/O
FUNCTION
XIN/RXIN
I
Input pad for main clock oscillator. It can be connected to crystal when crystal
mode is selected (SCR0.2=1), otherwise connect a resistor to VDD to generate
main system clock while RC mode is selected (SCR0.2=0 and default). Oscillator
can be enabled or stopped by set SCR0.1 to 1 or clear to 0 separately. External
capacitor connects to start oscillation while crystal mode
XOUT
O
I
Output pad for oscillator which is connected to another crystal pad when in crystal
mode. External capacitor connects to start oscillation when in crystal mode.
X32I/RSUB1
32.768 KHz crystal input pad or external resistor node 1 by mask option.
External 15~20pF capacitor connects to get more accurate clock when in crystal
mode.
X32O/RSUB2
O
32.768 KHz crystal output pad or external resistor node 2 by mask option.
External 15~20pF capacitor connects to get more accurate clock when in crystal
mode.
RA0 ~ RA3/TONE I/O
General Input/Output port specified by PM1 register. If output mode is selected,
PM0 register bit 0 can be used to specify CMOS/NMOS driving capability option.
Initial state is input mode. RA3 may be uses as TONE if bit 0 of MR0 special
register is set to logic 1. An interrupt source.
RB0 ~ RB3
RC0 ~ RC3
I/O
I
General Input/Output port specified by PM2 register. If output mode is selected,
PM0 register bit 1 can be used to specify CMOS/NMOS driving capability option.
Initial state is input mode.
4-bit schmitter input with internal pull high option specified by PM3 register bit 2.
Each pad has an independent interrupt capability specified by PEFL special
register. Interrupt and STOP mode wake up source. RC0 is also the external
event counter source of Timer1.
RD0 ~ RD3
I
4-bit schmitter input port with internal pull high option specified by PM3 register
bit 3. Each pad has an independent interrupt capability specified by PEFH
special register. Interrupt and STOP mode wake up source.
RE0~RE3
RF0~RF3
O
O
I
Output port only. PM3 register bit 0 can be used to specify CMOS/NMOS driving
capability option.
Output port only. PM3 register bit 1 can be used to specify CMOS/NMOS driving
capability option.
RG0 ~ RG3
RH0 ~ RH3
Input port with internal pull high option specified by PM6 register bit 0.
(W536090P/W536120P only)
O
I
Output port only. PM6 register bit 1 can be used to specify CMOS/NMOS driving
capability option. (W536090P/W536120P only)
System reset pad, active low with internal pull-high resistor.
RES
TEST
I
Test pad. Active high with internal pull low resistor.
ROSC
I
Connect resistor to VDD pad to generate speech or melody playing clock source.
PWM1/DAC
O
While speech or melody is active, PWM1/DAC is speaker direct driving output or
DAC output controlled by voice output file.
PWM2
WRP
O
O
While speech or melody is active, PWM2 is another speaker direct driving output.
External serial memory address write clock for voice extension.
Publication Release Date:April 2000
- 4 -
Revision A2
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RDP
O
External serial memory address read clock for voice extension.
External serial memory data in/out for voice extension.
Chip ground.
SPDATA
VSS
I/O
I
I
I
I
I
I
VSSP
Chip ground for PWM or DAC playing output.
Chip ground. (W536090P/120P only)
Power source.
VSSA (3)
VDD
VDDP
VDDA (3)
Power source for PWM or DAC playing output.
Power source. (W536090P/120P only)
(3) VDDA, VSSA for W536090P/120P only. To sure chip operation properly, please bond all
VDD, VDDA, VDDP, VSS, VSSA and VSSP pads, and connect VSS, VSSP form chip external
PCB circuit.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
-0.3 to +7.0
-0.3 to +7.0
120
0 to +70
-55 to +150
UNIT
V
V
mW
°C
°C
Supply Voltage to Ground Potential
Applied Input/Output Voltage
Power Dissipation
Ambient Operating Temperature
Storage Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely
affect the life and reliability of the device.
DC CHARACTERISTICS
(VDD−VSS = 3.0V, FM = 4 MHz with RC mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C unless
otherwise specified)
PARAMETER
Op. Voltage
Op. Current
(No Load, no Voice, no
Melody)
SYM. CONDITIONS
VDD
MIN TYP
2.4
MAX UNIT
5.5
500
500
30
V
uA
IOP1
Dual clock with crystal
-
400
400
15
Dual clock with RC type
Sub-clock only
Hold Mode Current
Stop Mode Current
RDP/WRP Output High
Current
RDP/WRP Output low
Current
IOP2
IOP3
IoH1
Sub-clock active only
4
6
1
-0.8
uA
uA
mA
Vout =2.7V
Vout =0.4V
IoL1
0.8
mA
Input Low Voltage
Input High Voltage
Port RA, RB, RE,RF and RH VABL IOL = 2.0 mA
Output Low Voltage
VIL
VIH
-
-
VSS
0.7
-
-
-
-
0.3
1
0.4
VDD
VDD
V
Port RA, RB, RE,RF and RH VABH IOH = -2.0 mA
Output High Voltage
2.4
-
-
V
Publication Release Date:April 2000
Revision A2
- 5 -
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Pull-up Resistor
RCD
RRES
ISPH
Port RC, RD, RG
-
200
50
300
100
-20
-70
400
200
KΩ
KΩ
mA
RES Pull-up Resistor
PWM1/2 Source Current (4)
Volume Option =00
Volume Option =01
(R
=8Ω between PWM1
LOAD
And PWM2 )
Volume Option =10
Volume Option =11
Volume Option =00
Volume Option =01
-110
-135
20
PWM1/2 Sink Current (4)
ISPL
mA
mA
70
(R
=8Ω between PWM1
LOAD
And PWM2 )
Volume Option =10
Volume Option =11
VDD=3v, RL=100ohm
110
135
-5
DAC output Current
IDAC
-4
-6
(4) PWM current deviation will be ±20%.
AC CHARATERISTICS
(VDD−VSS = 3.0V, FM = 4 MHz with RC mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C unless
otherwise specified)
PARAMETER
SYM.
CONDITIONS
MIN. TYP.
MAX. UNIT
Sub-clock Frequency
FSUB
Crystal type and X32IN
and X32O with 17pF
external cap.
32768
Hz
Main-clock Frequency
Chip Operation Frequency
FM
FOSC
RC type/Crystal type
SCR0.0=1,FSYS= FSUB
400K
-
4M
Hz
Hz
32768
SCR0.0=0;FSYS= FMAIN 400K
-
4M
Instruction Cycle Time
Reset Active Width
Interrupt Active Width
Main clock RC frequency
TCYC
TRAW
TIAW
One machine cycle
FOSC = 32.768 KHz
FOSC = 32.768 KHz
RXIN =680KΩ
RXIN =330K Ω
RXIN =200KΩ
RXIN =130KΩ
RSUB=680KΩ
RSUB=680KΩ
-
1
1
4/FOSC
-
-
1M
2M
3M
4M
32
-
-
-
S
µS
µS
Hz
FRXIN
Sub-Clock Ring Oscillator
Sub-Clock Oscillation
FRSUB
FSTOP
KHz
S
0.8
1
Stable Time @ Cold Start
Frequency Deviation of
main-clock FRXIN ≤ 2 MHz
10
%
%
%
f(3V) − f(2.4V)
f(3V)
∆f
f
Frequency Deviation of
main-clock FRXIN = 3 MHz
15
20
f(3V) − f(2.4V)
f(3V)
∆f
f
Frequency Deviation of
main-clock FRXIN = 4 MHz
f(3V) − f(2.4V)
f(3V)
∆f
f
ROSC Frequency
Frequency Deviation of
FROSC = 3MHz
FROSC
3
MHz
%
ROSC=680KΩ
f(3V) − f(2.4V)
7.5
∆f
f
f(3V)
(5) The deviation will be +20% while VDD drops from 5.5V to 2.4V based on same resistor
Publication Release Date:April 2000
Revision A2
- 6 -
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Iop Vs. Main clock RC mode
800
600
400
200
0
3V
Iop (uA)
4.5V
1
2
3
4
Freq (MhZ)
Oscillation Freq Vs. Sub-Clock
44
40
36
32
28
24
20
3V
4.5V
Fsub (KhZ)
560 620 680 750 820
1K
Rsub (Kohm)
Publication Release Date:April 2000
Revision A2
- 7 -
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Main Freq Vs. Rxin
6
5
4
3
2
1
0
2.4V
3v
Fmain
(MhZ)
4.5V
5.5V
130 150 160 200 330 680 2K 3K
RXIN (Kohm)
Voice Operating Freq. Vs. ROSC
4.5
4
3.5
3
3V
Freq (MhZ)
4.5V
2.5
2
470
560
680
910
ROSC (Kohm)
Publication Release Date:April 2000
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APPLICATION CIRCUIT--1: Sub clock with RC mode
VDDP
RA0~3
RB0~3
RC0~3
RD0~3
RE0~3
RF0~3
470
VDD
R5
RES
(*2)
( *1)
PWM1/DAC
PWM2
C3
Battery
VDDP
W536XXXP
R4
VDDA
VDD
C2
C1
WRP
R1
ROSC
XIN
RDP
W55M08
R3
SPDATA
RG0~3
RH0~3
X32IN
R2
X32O
Component C1
C2
C3
R1
R2
R3
R4
Value
0.1uF 4.7uF 0.1uF 680K 680K 680Kohm/1Mhz 100
330Kohm/2Mhz
200Kohm/3Mhz
130Kohm/4Mhz
Note:
(1) Option R5 equals to 100Ω if high noise immunity is needed.
(2) For DAC option application
(3) To sure chip operation properly, please bond all VDDP, VDD, VDDA, VSSP, VSSA and VSS
(4) VDDA, VSSA are only for W536090P/120P.
Publication Release Date:April 2000
- 9 -
Revision A2
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APPLICATION CIRCUIT--2: Sub clock with Xtal mode
VDDP
RA0~3
RB0~3
RC0~3
RD0~3
RE0~3
RF0~3
470
VDD
R5
( *1)
(*2)
RES
PWM1/DAC
PWM2
C3
Battery
VDDP
VDDA
C2
C1
R4
R1
VDD
W536XXXP
WRP
ROSC
RDP
W55M08
R3
XIN
SPDATA
C4
X32IN
RG0~3
RH0~3
32.768kHz
C5
X32O
Component
Value
C1
0.1uF
C2
C3
C4~C5
R1
R3
R4
4.7uF 0.1uF 17pF~20pF 680K 680Kohm/1Mhz 100
330Kohm/2Mhz
200Kohm/3Mhz
130Kohm/4Mhz
Note:
(1) Option R5 equals to 100Ω if high noise immunity is needed.
(2) For DAC option application.
(3) To sure chip operation properly, please bond all VDDP, VDD, VDDA, VSSP , VSSA and VSS .
(4) VDDA and VSSA are only for W536090P/120P.
Publication Release Date:April 2000
- 10 -
Revision A2
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