WED9LC6816V-BC_技术文档

WED9LC6816V

White Electronic Designs

256Kx32 SSRAM/4Mx32 SDRAM

External Memory Solution for Texas Instruments

TMS320C6000 DSP

DESCRIPTION

FEATURES

The WED9LC6816V is a 3/3V, 256K x 32 Synchronous

Pipeline SRAM and a 4Mx32 Synchronous DRAM array

constructed with one 256K x 32 SBSRAM and two 4Mx16

SDRAM die mounted on a multilayer laminate sub-

strate/ The device is packaged in a 153 lead, 14mm by

22mm, BGA/

n Clock speeds:

SSRAM: 200, 166,150, and 133 MHz

SDRAMs: 125 and 100 MHz

n DSP Memory Solution

Texas Instruments TMS320C6201

Texas Instruments TMS320C6701

n Packaging:

The WED9LC6816V provides a total memory solution

for the Texas Instruments TMS320C6201 and the

TMS320C6701 DSPs The Synchronous Pipeline SRAM

is available with clock speeds of 200, 166,150,v and

133 MHz, allowing the user to develop a fast external

memory for the SSRAM interface port /

153 pin BGA, JEDEC MO-163

n 3/3V Operating supply voltage

n Direct control interface to both the SSRAM and

The SDRAM is available in clock speeds of 125 and

100 MHz, allowing the user to develop a fast external

memory for the SDRAM interface port/

SDRAM ports on the C6x

n Common address and databus

n 65% space savings vs/ monolithic solution

n Reduced system inductance and capacitance

The WED9LC6816V is available in both commercial

and industrial temperature ranges/

FIGꢀ 1 PIN CONFIGURATION

PIN DESCRIPTION

TOP VIEW

A_0-17

Address Bus

Data Bus

1

2

DQ₂₃

DQ₂₂

VCCQ

DQ₂₁

DQ₂₀

VCCQ

NC

3

VCC

NC

4

VSS

5

6

7

8

9

DQ_0-31

SSCLK

A

B

C

D

E

F

DQ₁₉

DQ₁₈

VCCQ

DQ₁₇

DQ₁₆

VCCQ

NC

VSS

NC

VSS

NC

VSS

NC

VCC

A₂

DQ₂₄DQ₂₈

DQ₂₅DQ₂₉

SSRAM Clock

VSS

SDCE

SDA₁₀

VSS

SSADC SSRAM Address Status Control

SDWE

VSS

VCCQ

SSWE

SSOE

SSRAM Write Enable

SSRAM Output Enable

SDRAM Clock

DQ₂₆DQ₃₀

DQ₂₇DQ₃₁

VSS

SDCLK

VSS

SDCLK

SDRAS

VSS

VCCQ

A₄

VCCQ

A₅

SDRAM Row Address Strobe

G

H

J

SDRAS

VSS

SDCAS

VSS

SDCAS SDRAM Column Address Strobe

SDWE SDRAM Write Enable

SDA₁₀SDRAM Address10/auto precharge

NC

A₈

A₁

A₃

A₁₀

A₆

A₇

A₉

VSS

A₀

A₁₁

A₁₂

K

L

A₁₇

NC/A₁₈

NC

NC/A₁₉

NC

VSS

NC

VCC

A₁₃

A₁₄

BWE_0-3

SSRAM Byte Write Enables

SDRAM SDQM 0-3

NC

BWE₂

BWE₀

VSS

BWE₃

BWE₁

VSS

A₁₅

A₁₆

M

N

P

R

T

VCCQ

DQ₁₂

DQ₁₃

VCCQ

DQ₁₄

DQ₁₅

VCCQ

DQ₁₁

DQ₁₀

VCCQ

DQ₉

DQ₈

VCC

VCCQ

DQ₄

DQ₅

VCCQ

DQ₆

DQ₇

VCCQ

DQ₀

DQ₁

VCCQ

DQ₂

DQ₃

SSCE

SDCE

VCC

Chip Enable SSRAM Device

Chip Enable SDRAM Device

Power Supply pins, 3:3V

VSS

SSCLK

VSS

V^CCQ

Data Bus Power Supply pins,

3:3V (2:5V future)

SSADC

SSOE

SSWE

SSCE

VSS

Ground

U

NC

No Contact

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FIGꢀ 2 BLOCK DIAGRAM

A

0-17

A

0

1

A

0

1

2

3

4

DQ0-7

5

DQ1-8

6

DQ8-15

DQ9-16

7

8

DQ16-23

DQ17-24

9

DQ24-31

10

11

12

13

14

15

16

DQ25-32

SSWE

BWE

0

1

2

3

BW1

BW2

BW3

BW4

SSCE

SSOE

CE

OE

2

SSADC

ADSC

CLK

SSCLK

DQ0-31

A

0

1

2

3

4

5

6

7

8

DQ0-7

9

11

DQ8-15

SDA10

10/AP

A

12

13

BA

0

1

LDQM

UDQM

CS

RAS

CAS

WE

SDCE

SDRAS

SDCAS

SDWE

SDCLK

CLK

A

0

1

2

3

4

5

6

7

8

DQ16-23

DQ24-31

DQ0-7

9

11

DQ8-15

10/AP

A

12

13

BA

0

1

LDQM

UDQM

CS

RAS

CAS

WE

CLK

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OUTPUT FUNCTIONAL DESCRIPTIONS

Symbol

Type

Signal

Polarity

Function

SSCLK

Input

Pulse Positive Edge

The system clock input: All of the SSRAM inputs are sampled on the rising edge of the clock:

SSADS

SSOE

SSWE

When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define

the operation to be executed by the SSRAM:

Input

Pulse

Active Low

SSCE

SDCLK

SDCE

Input

SSCE disable or enable SSRAM device operation:

Pulse Positive Edge

The system clock input: All of the SDRAM inputs are sampled on the rising edge of the clock:

SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3:

Pulse

Active Low

SDRAS

SDCAS

SDWE

When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define

the operation to be executed by the SDRAM:

Input

Pulse

Active Low

Address bus for SSRAM and SDRAM

A⁰and A1 are the burst address inputs for the SSRAM

During a Bank Active command cycle, A^0-11, SDA10 defines the row address (RA0-10)

when sampled at the rising clock edge:

During a Read or Write command cycle, A^0-7defines the column address (CA0-7) when

sampled at the rising clock edge: In addition to the row address, SDA¹⁰is used to invoke

Autoprecharge operation at the end of the Burst Read or Write Cycle: If SDA¹⁰is high,

autoprecharge is selected and A¹²and A13 define the bank to be precharged: If SDA10 is

low, autoprecharge is disabled:

A^0-17,

SDA10

Input

Level

During a Precharge command cycle, SDA¹⁰is used in conjunction with A12 and A13 to

control which bank(s) to precharge: If SDA10 is high, all banks will be precharged regardless

of the state of A12 and A13: If SDA10 is low, then A12 and A13 are used to define which

bank to precharge:

Input

Output

DQ^0-31

Level

Pulse

Data Input/Output are multiplexed on the same pins:

BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the

SDRAM: BWE0 is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3

with DQ24-31:

BWE^0-3

Input

VCC, VSS Supply

V^CCQSupply

Power and ground for the input buffers and the core logic:

Data base power supply pins, 3:3V (2:5V future):

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ABSOLUTE MAXIMUM RATINGS

RECOMMENDED DC OPERATING CONDITIONS

(VCC = 3ꢀ3V -5% / +10% UNLESS OTHERWISE NOTED; 0°C £ TA £ 70°C,

C^OMMERCIAL; -40°C£ TA £ 85°C, INDUSTRIAL)

Voltage on VCC Relative to VSS

Vin (DQx)

-0:5V to +4:6V

-0:5V to Vcc +0:5V

-55°C to +125°C

+150°C

Parameter

Symbol Min

Max

Units

V

Storage Temperature (BGA)

Junction Temperature

Supply Voltage (1)

Input High Voltage (1,2)

Input Low Voltage (1,2)

VCC

VIH

VIL

IL^I

3:135

3:6

2:0 VCC +0:3

V

Short Circuit Output Current

100 mA

-0:3

-10

0:8

10

V

*Stress greater than those listed under "Absolute Maximum Ratings"

may cause permanent damage to the deviceꢀ This is a stress rating

only and functional operation of the device at these or any other

conditions greater than those indicated in operational sections of

this specifications is not impliedꢀ Exposure to absolute maximum

rating conditions for extended periods may affect reliabilityꢀ

Input Leakage Current

µA

0 £ VIN £ VCC

Output Leakage (Output Disabled)

ILO

-10

10

µA

0 £ VIN £ VCC

SSRAM Output High (IOH = -4mA) (1)

SSRAM Output Low (IOL = 8mA) (1)

SDRAM Output High (IOH = -2mA)

SDRAM Output Low (I^OL= 2mA)

VOH

VOL

VOH

VOL

2:4

0:4

V

2:4

0:4

NOTES:

1ꢀ All voltages referenced to V^SS(GND)ꢀ

2ꢀ Overshoot: V^IH£ +6ꢀ0V for t £ tKC/2

Underershoot: V^IL³ -2ꢀ0V for t £ tKC/2

DC ELECTRICAL CHARACTERISTICS

(VCC = 3ꢀ3V -5% / +10% UNLESS OTHERWISE NOTED; 0°C £ TA £ 70°C, COMMERCIAL; -40°C £ TA £ 85°C, INDUSTRIAL)

Description

Conditions

Symbol Frequency

Typ

Max

Units

133MHz

150MHz

166MHz

200MHz

500

550

600

625

650

700

800

Power Supply Currentꢀ

Operating (1,2,3)

SSRAM Active / DRAM Auto Refresh

I^CC1

mA

133MHz

325

350

400

450

425

450

495

585

Power Supply Current

Operating (1,2,3)

150MHz

I^CC2

SSRAM Active / DRAM Idle

SSRAM Active / SSRAM Idle

166MHz

mA

200MHz

83MHz

100MHz

125MHz

500

550

625

650

700

Power Supply Current

Operating (1,2,3)

I^CC3

ISB1

SSCE and SDCE £ V^CC-0:2V,

All other inputs at V^SS+0:2 £ VIN or

VIN £ VCC -0:2V, Clk frequency = 0

CMOS Standby

20:0

40:0

SSCE and SDCE £ V^IHmin

TTL Standby

Auto Refresh

All other inputs at VIL max £ VIN or

VIN £ VCC -0:2V, Clk frequency = 0

ISB2

I^CC5

30:0

250

55:0

300

mA

NOTES:

1ꢀ I^CC(operating) is specified with no output currentꢀ ICC (operating) increases with faster cycle times and greater output loadingꢀ

2ꢀ "Device idle" means device is deselected (CE = V^IH) Clock is running at max frequency and Addresses are switching each cycleꢀ

3ꢀ Typical values are measured at 3ꢀ3V, 25°Cꢀ I^CC(operating) is specified at specified frequencyꢀ

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SSRAM AC CHARACTERISTICS

(VCC = 3ꢀ3V -5% / +10% UNLESS OTHERWISE NOTED; 0°C £ TA £ 70°C, COMMERCIAL; -40°C £ TA £ 85°C, INDUSTRIAL)

Symbol

200MHz

166MHz

150MHz

Min Max

133MHz

Parameter

Min

Max

Min

Max

Min

Max Units

Clock Cycle Time

tKHKH

tKLKH

tKHKL

tKHQV

tKHQX

tKQLZ

tKQHZ

tOELQV

tOELZ

tOEHZ

tS

5

6

7

8

ns

Clock HIGH Time

1:6

2:4

2:6

2:8

Clock LOW Time

Clock to output valid

2:5

3:5

3:8

4:0

ns

Clock to output invalid

1:5

0

1:5

0

1:5

0

1:5

0

Clock to output on Low-Z

Clock to output in High-Z

Output Enable to output valid

Output Enable to output in Low-Z

Output Enable to output in High-Z

Address, Control, Data-in Setup Time to Clock

Address, Control, Data-in Hold Time to Clock

1:5

3

1:5

3:5

1:5

3:8

1:5

4:0

2:5

0

3:0

3:5

3:8

1:5

0:5

1:5

0:5

1:5

0:5

1:5

0:5

t^H

BGACAPACITANCE

Conditions

Description

Symbol

CI

Typ

Max

8

Units

Address Input Capacitance (1)

Input/Output Capacitance (DQ) (1)

Control Input Capacitance (1)

Clock Input Capacitance (1)

TA = 25°C; f = 1MHz

T^A= 25°C; f = 1MHz

5

8

5

4

pF

CO

10

8

CA

CCK

6

NOTE:

1ꢀ This parameter is sampledꢀ

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SSRAM OPERATION TRUTH TABLE

Operation

Address Used

None

SSCE

SSADS

SSWE

SSOE

DQ

High-Z

D

Deselected Cycle, Power Down

WRITE Cycle, Begin Burst

READ Cycle, Begin Burst

READ Cycle, Suspend Burst

WRITE Cycle, Suspend Burst

H

L

X

L

X

L

External

Current

L

H

L

Q

L

H

L

High-Z

Q

X

H

X

H

L

High-Z

Q

H

X

High-Z

D

L

D

NOTE:

1ꢀ X means dont care, H means logic HIGHꢀ L means logic LOWꢀ

2ꢀ All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLKꢀ

3ꢀ Suspending burst generates wait cycle

4ꢀ For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and

staying HIGH through out the input data hold timeꢀ

5ꢀ This device contains circuitry that will ensure the outputs will be in High-Z during power-upꢀ

SSRAM PARTIAL TRUTH TABLE

Function

SSWE BWE0 BWE1 BWE2 BWE3

READ

H

L

X

L

X

H

L

X

H

L

X

H

L

WRITE one Byte (DQ0-7)

WRITE all Bytes

L

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FIGꢀ 3 SSRAM READ TIMING

t

KHKL

tKLKH

t

KHKH

SSCLK

t

S

tH

SSADS

SSCE

t

S

tH

t

S

A1

A5

A2

A3

A4

ADDR

SSOE

t_H

t_OEHZ

t_OELQV

SSWE

DQ

t_KHQX

t_KHQV

t_KQLZ

Q(A1)

Q(A2)

Q(A3)

Q(A4)

Q(A5)

FIGꢀ 4 SSRAM WRITE TIMING

t

t_KHKH

K

H

K

L

K

L

K

H

SSCLK

t_S

t_H

SSADS

t_H

SSCE

t_H

tS

A4

A1

A2

A3

A5

ADDR

tH

tOEHZ

Must be HIGH

SSOE

SSWE

KHGWX

tS

t_H

t_S

D(A2)

D(A3)

D(A5)

D(A1)

D(A4)

DQ

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SDRAM AC CHARACTERISTICS

(VCC = 3ꢀ3V -5% / +10% UNLESS OTHERWISE NOTED; 0°C£ TA£ 70°C, COMMERCIAL; -40°C£ TA£ 85°C, INDUSTRIAL)

Symbol

125MHz

Min

100MHz

83MHz

Parameter

Max

1000

6

Min

Max

1000

7

Min

Max

1000

8

Units

CL = 3

CL = 2

t^CC

tCC

8

10

12

15

Clock Cycle Time (1)

ns

10

Clock to valid Output delay (1,2)

Output Data Hold Time (2)

tSAC

tOH

ns

3

2

1

2

3

2

1

2

3

2

1

2

Clock HIGH Pulse Width (3)

Clock LOW Pulse Width (3)

Input Setup Time (3)

tCH

ns

tCL

ns

tSS

ns

Input Hold Time (3)

tSH

ns

CLK to Output Low-Z (2)

tSLZ

tSHZ

tRRD

tRCD

tRP

ns

CLK to Output High-Z

7

8

ns

Row Active to Row Active Delay (4)

RAS\ to CAS\ Delay (4)

20

50

70

1

20

50

80

1

24

60

90

1

ns

Row Precharge Time (4)

ns

Row Active Time (4)

tRAS

tRC

10,000

ns

Row Cycle Time - Operation (4)

Row Cycle Time - Auto Refresh (4,8)

Last Data in to New Column Address Delay (5)

Last Data in to Row Precharge (5)

Last Data in to Burst Stop (5)

Column Address to Column Address Delay (6)

Number of Valid Output Data (7)

ns

tRFC

tCDL

tRDL

tBDL

tCCD

ns

CLK

1

1:5

2

1:5

2

1:5

2

ea

1

2

1

NOTES:

1ꢀ Parameters depend on programmed CAS latencyꢀ

2ꢀ If clock rise time is longer than 1ns (t^rise/2 -0ꢀ5)ns should be added to the parameterꢀ

3ꢀ Assumed input rise and fall time = 1nsꢀ If t^riseof tfall are longer than 1nsꢀ [(trise = tfall)/2] - 1ns should be added to the parameterꢀ

4ꢀ The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up

to the next higher integerꢀ

5ꢀ Minimum delay is required to complete writeꢀ

6ꢀ All devices allow every cycle column address changesꢀ

7ꢀ In case of row precharge interrupt, auto precharge and read burst stopꢀ

8ꢀ A new command may be given t^RFCafter self-refresh exitꢀ

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CLOCK FREQUENCY AND LATENCY PARAMETERS - 125MHZ SDRAM

(UNIT = NUMBER OF CLOCK)

Frequency

tRC

70ns

9

tRAS

tRP

20ns

3

tRRD

tRCD

tCCD

tCDL

tRDL

CAS

Latency

50ns

20ns

10ns

125MHz (8:0ns)

100MHz (10:0ns)

83MHz (12:0ns)

3

2

6

5

4

2

3

2

1

7

2

6

2

CLOCK FREQUENCY AND LATENCY PARAMETERS - 100MHZ SDRAM

(UNIT = NUMBER OF CLOCK)

Frequency

tRC

70ns

7

tRAS

50ns

5

tRP

20ns

2

tRRD

20ns

2

tRCD

20ns

2

tCCD

10ns

1

tCDL

10ns

1

tRDL

10ns

1

CAS

Latency

100MHz (12:0ns)

83MHz (12:0ns)

3

2

6

5

2

1

REFRESH CYCLE PARAMETERS

-10

-12

Parameter

Symbol

Min

Max

Min

Max

64

Units

ms

Refresh Period (1,2)

t^REF

64

NOTES:

1ꢀ 4096 cycles

2ꢀ Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the deviceꢀ

SDRAM COMMAND TRUTH TABLE

SDCE

SDRAS

SDCAS

SDWE

BWE

A¹², A13

OP CODE

SDA10

A11-0

Function

Notes

Mode Register Set

Auto Refresh (CBR)

L

H

X

L

H

L

X

L

X

BA

X

Precharge

Single Bank

Precharge all Banks

L

H

L

2

L

H

Bank Activate

Write

L

H

L

BA

X

Row Address

2

3

H

X

L

H

L

Write with Auto Precharge

Read

L

Read with Auto Precharge

Burst Termination

L

H

L

H

X

H

X

No Operation

H

X

Device Deselect

X

Data Write/Output Disable

Data Mask/Output Disable

X

4

H

X

NOTES:

1ꢀ All of the SDRAM operations are defined by states of SDCE\, SDWE\, SDRAS\, SDCAS\, and BWE^0-3at the positive rising edge of the clockꢀ

2ꢀ Bank Select (BA), A¹²(BA0) and A13 (BA1) select between different banksꢀ

3ꢀ During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latencyꢀ

4ꢀ The BWE has two functions for the data DQ Read and Write operationsꢀ During a Read cycle, when BWE goes high at a clock timing the data

outputs are disabled and become high impedance after a two clock delayꢀ BWE also provides a data mask function for Write cyclesꢀ When it

activates, the Write operation at the clock is prohibited (zero clock latency)ꢀ

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MODE REGISTER SET TABLE

A11

A10

A

9

A8

A

7

A6

A

5

A4

A3

A

2

A1

A0

Address Bus

Mode Register (Mx)

Reserved* WB Op Mode CAS Latency BT

Burst Length

*Should program

M11, M10 = "0, 0"

to ensure compatibility

with future devices.

Burst Length

M2 M1 M0

M3 = 0

M3 = 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

1

2

4

8

Reserved

Full Page

Reserved

Burst Type

M3

0

Sequential

Interleaved

1

CAS Latency

M6 M5 M4

Reserved

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

Reserved

M8

0

M7

0

M6-M0

Defined

-

Operating Mode

Standard Operation

All other states reserved

-

Write Burst Mode

M9

0

Programmed Burst Length

Single Location Access

1

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SDRAM CURRENT STATE TRUTH TABLE

Command

Current State

Action

Notes

SDCE SDRAS SDCAS SDWE

A12 & A13

A11-A0

Description

(BA)

L

H

L

H

L

H

L

H

L

H

L

H

L

OP Code

Mode Register Set

Auto or Self Refresh

Precharge

Set the Mode Register

Start Auto

1

X

L

H

L

X

No Operation

L

H

L

BA

X

Row Address

Bank Activate

Write w/o Precharge

Read w/o Precharge

Burst Termination

No Operation

Device Deselect

Mode Register Set

Auto or Self Refresh

Precharge

Activate the specified bank and row

ILLEGAL

Idle

H

X

L

Column

2

1

L

H

L

Column

ILLEGAL

H

X

L

X

No Operation

H

X

L

X

No Operation

X

No Operation

OP Code

ILLEGAL

L

H

L

X

ILLEGAL

L

H

L

X

Precharge

3

1

L

H

L

BA

X

Row Address

Bank Activate

Write

ILLEGAL

Row Active

H

X

L

Column

Start Write; Determine if Auto Precharge

Start Read; Determine if Auto Precharge

No Operation

4,5

L

H

L

Column

Read

H

X

L

X

Burst Termination

No Operation

Device Deselect

Mode Register Set

Auto or Self Refresh

Precharge

H

X

L

X

No Operation

X

No Operation

OP Code

ILLEGAL

L

H

L

X

ILLEGAL

L

H

L

X

Terminate Burst; Start the Precharge

ILLEGAL

L

H

L

BA

X

Row Address

Bank Activate

Write

2

Read

H

X

L

Column

Terminate Burst; Start the Write cycle

Terminate Burst; Start a new Read cycle

Terminate the Burst

Continue the Burst

ILLEGAL

5,6

L

H

L

Column

Read

H

X

L

X

Burst Termination

No Operation

Device Deselect

Mode Register Set

Auto or Self Refresh

Precharge

H

X

L

X

OP Code

L

H

L

X

ILLEGAL

L

H

L

X

Terminate Burst; Start the Precharge

ILLEGAL

L

H

L

BA

X

Row Address

Bank Activate

Write

2

Write

H

X

L

Column

Terminate Burst; Start a new Write cycle

Terminate Burst; Start the Read cycle

Terminate the Burst

Continue the Burst

ILLEGAL

5,6

L

H

L

Column

Read

H

X

L

X

Burst Termination

No Operation

Device Deselect

Mode Register Set

Auto or Self Refresh

Precharge

H

X

L

X

OP Code

L

H

L

X

ILLEGAL

L

H

L

X

ILLEGAL

2

Read with

L

H

L

BA

X

Row Address

Bank Activate

Write

ILLEGAL

Auto Precharge

H

X

Column

ILLEGAL

L

H

L

Column

Read

ILLEGAL

H

X

Burst Termination

No Operation

Device Deselect

ILLEGAL

H

X

Continue the Burst

X

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WED9LC6816V

White Electronic Designs

SDRAM CURRENT STATE TRUTH TABLE (CONTꢀ)

Command

Current State

Action

Notes

SDCE SDRAS SDCAS SDWE

A12 & A13

A11-A0

Description

(BA)

L

H

L

H

L

H

L

H

L

H

L

H

L

OP Code

Mode Register Set

Auto or Self Refresh

Precharge

ILLEGAL

X

ILLEGAL

L

H

L

X

ILLEGAL

2

Write with

L

H

L

BA

X

Row Address

Bank Activate

Write

ILLEGAL

Auto Precharge

H

X

L

Column

ILLEGAL

L

H

L

Column

Read

H

X

L

X

Burst Termination

No Operation

Device Deselect

Mode Register Set

Auto or Self Refresh

Precharge

ILLEGAL

H

X

L

X

Continue the Burst

ILLEGAL

X

OP Code

L

H

L

X

ILLEGAL

L

H

L

X

No Operation; Bank(s) idle after tRP

ILLEGAL

L

H

L

BA

X

Row Address

Bank Activate

Write w/o Precharge

Read w/o Precharge

Burst Termination

No Operation

Device Deselect

Mode Register Set

Auto or Self Refresh

Precharge

2

Precharging

H

X

L

Column

ILLEGAL

L

H

L

Column

ILLEGAL

20

H

X

L

X

No Operation; Bank(s) idle after tRP

ILLEGAL

H

X

L

X

OP Code

L

H

L

X

ILLEGAL

L

H

L

X

ILLEGAL

2

L

H

L

BA

X

Row Address

Bank Activate

Write

ILLEGAL

Row Activating

H

X

L

Column

ILLEGAL

L

H

L

Column

Read

ILLEGAL

H

X

L

X

Burst Termination

No Operation

Device Deselect

Mode Register Set

Auto orSelf Refresh

Precharge

No Operation; Row active after tRCD

ILLEGAL

H

X

L

X

OP Code

L

H

L

X

ILLEGAL

L

H

L

X

ILLEGAL

2

6

L

H

L

BA

X

Row Address

Bank Activate

Write

ILLEGAL

Write Recovering

H

X

L

Column

Start Write; Determine if Auto Precharge

Start Read; Determine if Auto Precharge

No Operation; Row active after tDPL

ILLEGAL

L

H

L

Column

Read

H

X

L

X

Burst Termination

No Operation

Device Deselect

Mode Register Set

Auto orSelf Refresh

Precharge

H

X

L

X

OP Code

L

H

L

X

ILLEGAL

L

H

L

X

ILLEGAL

2

Write Recovering

with Auto

L

H

L

BA

X

Row Address

Bank Activate

Write

ILLEGAL

H

X

Column

ILLEGAL

2,6

Precharge

L

H

L

Column

Read

ILLEGAL

H

X

Burst Termination

No Operation

Device Deselect

No Operation; Precharge after tDPL

H

X

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12

WED9LC6816V

White Electronic Designs

SDRAM CURRENT STATE TRUTH TABLE (CONTꢀ)

Command

Current State

Action

Notes

SDCE SDRAS SDCAS SDWE

A12 & A13

A11-A0

Description

(BA)

L

H

L

H

L

H

L

OP Code

Mode Register Set

Auto or Self Refresh

Precharge

ILLEGAL

X

ILLEGAL

L

H

L

X

ILLEGAL

L

H

L

BA

X

Row Address

Bank Activate

Write

ILLEGAL

Refreshing

H

X

L

Column

L

H

L

Column

Read

ILLEGAL

H

X

L

X

Burst Termination

No Operation

Device Deselect

Mode Register Set

Auto or Self Refresh

Precharge

No Operation; Idle after tRC

ILLEGAL

H

X

L

X

OP Code

L

H

L

X

ILLEGAL

L

H

L

X

ILLEGAL

Mode Register

Accessing

L

H

L

BA

X

Row Address

Bank Activate

Write

ILLEGAL

H

X

Column

ILLEGAL

L

H

L

Column

Read

ILLEGAL

H

X

Burst Termination

No Operation

Device Deselect

ILLEGAL

H

X

No Operation; Idle after two clock cycles

X

NOTES:

1ꢀ Both Banks must be idle otherwise it is an illegal actionꢀ

2ꢀ The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegalꢀ If BA selects the bank not being

referenced by the Current State then the action may be legal depending on the state of that bankꢀ

3ꢀ The minimum and maximum Active time (t^RAS) must be satisfiedꢀ

4ꢀ The RAS to CAS Delay (t^RCD) must occur before the command is givenꢀ

5ꢀ Address SDA¹⁰is used to determine if the Auto Precharge function is activatedꢀ

6ꢀ The command must satisfy any bus contention, bus turn around, and/or write recovery requirementsꢀ

The command is illegal if the minimum bank to bank delay time (t^RRD) is not satisfiedꢀ

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WED9LC6816V

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FIGꢀ 5 SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @

CAS LATENCY = 3, BURST LENGTH = 1

6

0

1

2

3

4

5

7

8

9

10

11

12

13

14

15

16

17

18

19

SDCLK

tCH

t

CL

t

CC

t

RCD

t

RAS

SDCE

t

SS

tSH

t

RP

t

RCD

t

SH

t

SS

SDRAS

t

CCD

tSS

tSH

SDCAS

ADDR

t

SS

t

SH

tSH

t

SS

Cb

BS

Cc

Ra

Ca

Rb

BA^{0, 1}

BS

Rb

BS

Ra

BS

[A12,A13

]

SDA¹⁰

t

RAC

t

SS

t

SH

t

SAC

Qa

Db

Qc

DQ

t

SLZ

tOH

t

tSH

SDWE

t

SH

BWE

Read

Write

Row Active

DON’T CARE

Precharge

Contact factory for ordering informationꢀ

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14

WED9LC6816V

White Electronic Designs

FIGꢀ 6 SDRAM POWER UP SEQUENCE

6

0

1

2

3

4

5

7

8

9

10

11

12

13

14

15

16

17

18

19

SDCLK

SDCE

tRFC

t

RP

SDRAS

SDCAS

ADDR

Key

RAa

BA^0,1

[A12,A13

]

RAa

SDA¹⁰

DQ

HIGH-Z

SDWE

BWE

High level is necessary

Auto Refresh

Mode Register Set

Precharge

(All Banks)

Auto Refresh

Row Active

(A-Bank)

DON’T CARE

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WED9LC6816V

White Electronic Designs

FIGꢀ 7 SDRAM READ & WRITE CYCLE AT SAME BANK @

BURST LENGTH = 4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

SDCLK

SDCE

Note 1

t

RC

tRCD

SDRAS

SDCAS

ADDR

Ra

Ca0

Rb

Cb0

BA0, 1

[A12,A13

]

Ra

Rb

SDA10

CL=2

t

SHZ Note 4

t

RAC

t

RDL

t

OH

Note 3

t

SAC

Qa0 Qa1 Qa2 Qa3

Db0 Db1 Db2 Db3

tSHZ Note 4

t

RAC

DQ

t

RDL

tOH

Note 3

tSAC

Qa3

Db0 Db1 Db2 Db3

Qa0 Qa1 Qa2

CL=3

SDWE

BWE

Row Active

(A-Bank)

Write

(A-Bank)

Read

(A-Bank)

Row Active

(A-Bank)

Precharge

(A-Bank)

Precharge

(A-Bank)

DON’T CARE

NOTES:

1ꢀ Minimum row cycle times are required to complete internal DRAM operationꢀ

2ꢀ Row precharge can interrupt burst on any cycleꢀ (CAS Latency - 1) number of valid output data is available after Row prechargeꢀ Last

valid output will be Hi-Z (t^SHZ) after the clockꢀ

3ꢀ Access time from Row active commandꢀ t^CC*(tRCD + CAS Latency - 1) + tSACꢀ

4ꢀ Output will be Hi-Z after the end of burstꢀ (1, 2, 4, 8 & Full page bit burst)

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WED9LC6816V

White Electronic Designs

FIGꢀ 8 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @

BURST LENGTH = 4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

SDCLK

SDCE

t

RCD

SDRAS

Note 2

SDCAS

ADDR

Ra

Ca0

Cb0

Cc0

Cd0

BA0, 1

[A12,A13

]

Ra

SDA10

CL=2

tRDL

Qa0

Qa1

Qb1

Qb2

Dc0

Dc1

Dd1

Qb0

Dd0

DQ

t

CDL

Qa3

Dc1

Dd0 Dd1

Qa0 Qa1 Qa2

CL=3

SDWE

BWE

Note 3

Note 1

Read

(A-Bank)

Read

(A-Bank)

Write

(A-Bank)

Write

(A-Bank)

Row Active

(A-Bank)

Precharge

(A-Bank)

DON’T CARE

NOTES:

1ꢀ To write data before burst read endsꢀ BWE should be asserted three cycle prior to write command to avoid bus contentionꢀ

2ꢀ Row precharge will interrupt writingꢀ Last data input, t^RDLbefore Row precharge will be writtenꢀ

3ꢀ BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burstꢀ Input data after

Row precharge cycle will be masked internallyꢀ

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WED9LC6816V

White Electronic Designs

FIGꢀ 9 SDRAM PAGE READ CYCLE AT DIFFERENT BANK @

BURST LENGTH = 4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

SDCLK

Note 1

SDCE

SDRAS

SDCAS

ADDR

Note 2

RAa

CAa RBb

CBb

CAc

CAe

CBd

BA0, 1

[A12,A13]

RAa

RBb

SDA¹⁰

CL=2

QAa0 QAa1 QAa2

QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

QAa3

DQ

QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 Qbb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

CL=3

SDWE

BWE

Read

(B-Bank)

Read

(A-Bank)

Read

(B-Bank)

Read

(A-Bank)

Row Active

(A-Bank)

Row Active

(B-Bank)

Precharge

(A-Bank)

DON’T CARE

Read

(A-Bank)

NOTES:

1ꢀ SDCE can be dont care when SDRAS, SDCAS and SDWE are high at the clock going high edgeꢀ

2ꢀ To interrupt a burst read by Row precharge, both the read and the precharge banks must be the sameꢀ

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WED9LC6816V

White Electronic Designs

FIGꢀ 10 SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @

BURST LENGTH = 4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

SDCLK

SDCE

SDRAS

Note 2

SDCAS

ADDR

RAa

CAa RBb

CBb

CAc

CBb

BA0, 1

[A12,A13

]

SDA10

DQ

RAa

RBb

tCDL

t

RDL

DAa3

DBb1 DBb2 DBb3 DAc0 DAc1

DBd1

DAa0 DAa1 DAa2

DBb0

DBd0

SDWE

BWE

Note 1

Row Active

(A-Bank)

Write

(A-Bank)

Row Active

(A-Bank)

Write

(B-Bank)

Precharge

(Both Banks)

Write

(B-Bank)

Write

(A-Bank)

DON’T CARE

NOTES:

1ꢀ To interrupt burst write by Row precharge, BWE should be asserted to mask invalid input dataꢀ

2ꢀ To interrupt a burst read by Row precharge, both the read and the precharge banks must be the sameꢀ

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WED9LC6816V

White Electronic Designs

FIGꢀ 11 SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @

BURST LENGTH = 4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

SDCLK

SDCE

SDRAS

SDCAS

ADDR

RAa

CAa

RBb

CBb

RAc

CAc

BA0, 1

[A12,A13]

RAa

RBb

RAc

SDA10

tCDL

Note 1

QAa0

DBb0 DBb1

DBb3

QAc0 QAc1 QAc2

QAc0 QAc1

QAa1 QAa2

QAa0 QAa1

DBb2

QAa3

QAa2

CL=2

DQ

CL=3

QAa3

SDWE

BWE

Write

(B-Bank)

Row Active

(A-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

Read

(A-Bank)

DON’T CARE

Row Active

(A-Bank)

Row Active

(A-Bank)

NOTES:

1ꢀ t^CDLshould be met to complete writeꢀ

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WED9LC6816V

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FIGꢀ 12 SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @

BURST LENGTH = 4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

SDCLK

SDCE

SDRAS

SDCAS

ADDR

BA0, 1

Ra

Rb

Ca

Cb

[A12,A13

]

Ra

Rb

SDA10

CL=2

Qa0

Db0

Db1 Db2

Db3

Qa1 Qa2 Qa3

DQ

CL=3

Qa0 Qa1

Qa3

Db1

Db3

Qa2

Db2

SDWE

BWE

Row Active

(A-Bank)

Auto Precharge

Start Point

(B-Bank)

Write with

Auto Precharge

(B-Bank)

Read with

Auto Precharge

(A-Bank)

Auto Precharge

Start Point

(A-Bank)

Row Active

(B-Bank)

DON’T CARE

NOTES:

1ꢀ t^CDLshould be controlled to meet minimum tRAS before internal precharge startꢀ

(In the case of Burst Length = 1 & 2 and BRSW mode)

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FIGꢀ 13 SDRAM READ INTERRUPTED BY PRECHARGE COMMAND &

READ BURST STOP @ BURST LENGTH = FULL PAGE

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

SDCLK

SDCE

SDRAS

SDCAS

ADDR

BA0, 1

RAa

CAa

CAb

[A12,A13

]

RAa

SDA10

Note 2

1

QAb2 QAb3 QAb4 QAb5

QAb0

QAb1

QAa0 QAa1

QAa3 QAa4

QAa2

CL=2

CL=3

DQ

2

QAa0 QAa1 QAa2 QAa3 QAa4

QAb0 QAb1 QAb2 QAb3 QAb4 QAb5

SDWE

BWE

Read

(A-Bank)

Precharge

(A-Bank)

Read

(A-Bank)

Row Active

(A-Bank)

Burst Stop

DON’T CARE

NOTES:

1ꢀ At full page mode, burst is end at the end of burstꢀ So auto precharge is possibleꢀ

2ꢀ About the valid DQs after burst stop, it is the same as the case of SDRAS interruptꢀ Both cases are illustrated in the above timing

diagramꢀ See the label 1, 2 on each of themꢀ But at burst write, burst stop and SDRAS interrupt should be compared carefullyꢀ Refer

to the timing diagram of Full page write burst stop cycleꢀ

3ꢀ Burst stop is valid at every burst lengthꢀ

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22

WED9LC6816V

White Electronic Designs

FIGꢀ 14 SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND &

WRITE BURST STOP @ BURST LENGTH = FULL PAGE

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

SDCLK

SDCE

SDRAS

SDCAS

ADDR

BA0, 1

RAa

CAa

CAb

[A12,A13

]

RAa

SDA¹⁰

DQ

tBDL

tRDL

Note 2

DAb0 DAb1 DAb2 DAb3 DAB4 DAb5

DAa0 DAa1 DAa2 DAa3 DAa4

SDWE

BWE

Write

(A-Bank)

Row Active

(A-Bank)

Burst Stop

Precharge

(A-Bank)

Write

(A-Bank)

DON’T CARE

NOTES:

1ꢀ At full page mode, burst is end at the end of burstꢀ So auto precharge is possibleꢀ

2ꢀ Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cellꢀ It is defined by AC parameter

of t^RDLꢀ BWE at write interrupt by precharge command is needed to prevent invalid writeꢀ

BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burstꢀ Input data after Row

precharge cycle will be masked internallyꢀ

3ꢀ Burst stop is valid at every burst lengthꢀ

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FIGꢀ 15 SDRAM BURST READ SINGLE BIT WRITE CYCLE @

BURST LENGTH = 2

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

SDCLK

SDCE

SDRAS

SDCAS

ADDR

RAa

CAa

RBb CAb

RAc

CBc

CAd

BA0, 1

[A12,A13]

RAa

RBb

RAc

SDA10

DAa0

QAb0

DBc0

QAd1

QAb1

QAd0

CL=2

DQ

CL=3

QAd0 QAd1

QAa1 QAb1

SDWE

BWE

Row Active

(A-Bank)

Precharge

(Both Banks)

Row Active

(A-Bank)

Read

(A-Bank)

Write with

Auto Precharge

(B-Bank)

Row Active

(B-Bank)

Read with

Write

Auto Precharge

(A-Bank)

DON’T CARE

NOTES:

1ꢀ BRSW modes enabled by setting A9 High at MRS (Mode Register Set)ꢀ

At the BRSW Mode, the burst length at Write is fixed to 1 regardless of programmed burst lengthꢀ

2ꢀ When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violatedꢀ Auto precharge is

executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the prechargeꢀ

Contact factory for ordering informationꢀ

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WED9LC6816V

White Electronic Designs

FIGꢀ 16

SDRAM MODE REGISTER

SET CYLE

SDRAM AUTO REFRESH CYCLE

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

9

10

SDCLK

HIGH

SDCE

Note 2

t

RFC

SDRAS

Note 1

Note 3

SDCAS

ADDR

Key

Ra

DQ

HI-Z

SDWE

BWE

MRS

New

Command

Auto Refresh

New Command

DON'T CARE

*Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycleꢀ

NOTES:

MODE REGISTER SET CYCLE

1ꢀ SDCE, SDRAS, SDCAS & SDWE activation at the same clock cycle with address key will set internal mode registerꢀ

2ꢀ Minimum 2 clock cycles should be met before new SDRAS activationꢀ

3ꢀ Please refer to Mode Register Set Tableꢀ

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PACKAGE DESCRIPTION: 153 LEAD BGA (17 X 9 BALL ARRAY)

JEDEC MP-163

3.50 (0.138)

MAX

14.00 (0.551)

BSC

A

B

C

D

E

F

PIN 1 INDEX

G

H

J

22.00 (0.866)

BSC

K

L

M

N

P

R

T

U

1.27 (0.050) TYP

ALL LINEAR DIMENSIONSARE MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTE:

Ball attach pad for above BGA package is 480 microns in diameterꢀ Pad is solder mask definedꢀ

ORDERING INFORMATION

COMMERCIAL (0°C £ TA £ 70°C)

INDUSTRIAL (-40°C £ TA £ 85°C)

Part Number

SSRAM Access

200MHz

SDRAM Access

125MHz

Part Number

SSRAM Access

SDRAM Access

125MHz

WED9LC6816V2012BI

WED9LC6816V2010BI

WED9LC6816V1612BI

WED9LC6816V1610BI

WED9LC6816V1512BI

WED9LC6816V1510BI

WED9LC6816V1312BI

WED9LC6816V1310BI

WED9LC6816V2012BC

WED9LC6816V2010BC

WED9LC6816V1612BC

WED9LC6816V1610BC

WED9LC6816V1512BC

WED9LC6816V1510BC

WED9LC6816V1312BC

WED9LC6816V1310BC

200MHz

166MHz

150MHz

133MHz

200MHz

100MHz

166MHz

125MHz

166MHz

100MHz

150MHz

125MHz

150MHz

100MHz

133MHz

125MHz

133MHz

100MHz

Contact factory for ordering informationꢀ

White Electronic Designs Corporation Westborough, MA (508) 366-5151

26

WED9LC6816V

White Electronic Designs

INTERFACING THE TEXAS INSTRUMENTS TMS 320C6x WITH THE

WED9LC6816V (256Kx32 SSRAM/4Mx32 SDRAM)

Address Bus

EDI9LC644V

128K x 32 SSRAM

1M x 32 SDRAM

EA^2-21

EA

2

3

A

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

DQ0-7

DQ8-15

Texas Instruments

TMS320C6x

DSP

DQ16-23

DQ24-31

SSWE\

SSCE\

SSOE\

SSADC\

SSCLK

SSWE\

CE

SSOE\

SSADS\

SSCLK

2

\

SSRAM

Control

BWE

0

1

2

3

\

BE0

BE1

BE2

BE3

\

Shared

Controls

SDA¹⁰

CE

SDRAS\

SDCAS\

SDWE\

SDCLK

SDCE\

SDRAS\

SDCAS\

SDWE\

SDCLK

0

\

SDRAM

Control

Data Bus

ED^0-31

Contact factory for ordering informationꢀ

27

White Electronic Designs Corporation (508) 366-5151 wwwꢀwhiteedcꢀcom


型号：	WED9LC6816V-BC
厂家：	ETC
描述：	SSRAM/SDRAM MCP SSRAM / SDRAM MCP\n 静态存储器动态存储器
文件：	总27页 (文件大小：357K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

WED9LC6816V-BC [ETC]

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