WS512K32-17G2TM [ETC]
x32 SRAM Module ; X32 SRAM模块\n
| 型号： | WS512K32-17G2TM |
| 厂家： | 
ETC |
| 描述： | x32 SRAM Module
|
| 文件： | 总9页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WS512K32-XXX / EDI8C32512CA
HI-RELIABILITY PRODUCT
512Kx32 SRAM MODULE, SMD 5962-94611
FEATURES
■ Access Times of 15*, 17, 20, 25, 35, 45, 55ns
■ 5 Volt Power Supply
■ Low Power CMOS
■ Packaging
• 66 pin, PGA Type, 1.075" square, Hermetic Ceramic HIP
(Package 400).
■ Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
• 68 lead, 40mm Hermetic Low Profile CQFP, 3.5mm (0.140")
(Package 502), Package to be developed.
■ Weight
WS512K32-XH1X - 13 grams typical
WS512K32-XG2TX / EDI8C32512CA-E - 13 grams typical
WS512K32-XG4TX - 20 grams typical
• 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square
(Package 509) 4.57mm (0.180") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3).
NOTE: For non-SMD new designs, please use the WS512K32-
XXX part number for inquiries and orders.
■ Organized as 512Kx32, User Configurable as 1Mx16 or 2Mx8
■ Commercial, Industrial and Military Temperature Ranges
■ TTL Compatible Inputs and Outputs
*
15ns Access Time available only in Commercial and Industrial Temperature.
This speed is not fully characterized and is subject to change without notice.
FIG. 1 PIN CONFIGURATION FOR WS512K32N-XH1X
TOP VIEW
PIN DESCRIPTION
1
12
23
34
45
56
I/O0-31 Data Inputs/Outputs
I/O
I/O
8
9
WE
2
I/O15
I/O14
I/O13
I/O12
OE
I/O24
I/O25
I/O26
V
CC
I/O31
I/O30
I/O29
I/O28
A0-18
WE1-4
CS1-4
OE
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
CS
2
CS
4
I/O10
GND
I/O11
WE
4
A13
A14
A15
A16
A17
A
A
6
7
I/O27
VCC
A
A
A
V
10
11
12
CC
A
3
4
5
3
3
A
A
A
0
1
2
GND
NC
Not Connected
A
18
NC
A
WE1
A
A
8
9
A
BLOCK DIAGRAM
WE3 CS3
WE4 CS4
WE1 CS1
WE2 CS2
I/O
I/O
I/O
I/O
7
WE
CS
I/O23
I/O22
I/O21
I/O20
OE
A0-18
I/O
I/O
I/O
0
1
2
CS
NC
I/O
1
6
I/O16
I/O17
I/O18
512K x 8
512K x 8
512K x 8
512K x 8
5
4
GND
I/O19
3
8
8
8
8
11
22
33
44
55
66
I/O16-23
I/O24-31
I/O0-7
I/O8-15
June 1999 Rev. 4
1
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WS512K32-XXX /
EDI8C32512CA
FIG. 2 PIN CONFIGURATION FOR WS512K32-XG4TX
TOP VIEW
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-18
WE
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
9
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
CS1-4
OE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
VCC
GND
NC
Not Connected
GND
I/O
I/O
8
9
BLOCK DIAGRAM
CS1
CS2
CS3
CS4
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
WE
OE
0-18
A
512K x 8
512K x 8
512K x 8
512K x 8
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
FIG. 3 PIN CONFIGURATION FOR WS512K32-XG2TX
AND EDI8C32512CA-E
PIN DESCRIPTION
TOP VIEW
I/O0-31 Data Inputs/Outputs
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
A0-18
WE1-4
CS1-4
OE
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
0.940"
VCC
GND
NC
The White 68 lead G2T CQFP
GND
Not Connected
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2T has the TCE
and lead inspection advantage
of the CQFP form.
I/O
I/O
8
9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
BLOCK DIAGRAM
WE3 CS3
WE4 CS4
WE1 CS1
WE2 CS2
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
OE
A0-18
512K x 8
512K x 8
512K x 8
512K x 8
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
2
WS512K32-XXX /
EDI8C32512CA
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
CS
H
L
OE
X
WE
X
Mode
Standby
Read
Data I/O
Power
Standby
Active
Parameter
Symbol
TA
Min
-55
-65
-0.5
Max
+125
+150
Vcc+0.5
150
Unit
°C
°C
V
High Z
Data Out
High Z
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
L
H
TSTG
VG
L
H
H
Out Disable
Write
Active
L
X
L
Data In
Active
TJ
°C
V
VCC
-0.5
7.0
CAPACITANCE
(TA = +25°C)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
COE
Conditions
IN = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
Max Unit
Parameter
Symbol
VCC
Min
4.5
Max
5.5
Unit
V
OE capacitance
V
50
pF
pF
Supply Voltage
WE1-4 capacitance
HIP (PGA)
CWE
Input High Voltage
Input Low Voltage
Operating Temp (Mil)
VIH
2.2
VCC + 0.3
+0.8
V
20
50
20
VIL
-0.5
-55
V
CQFP G4T
CQFP G2T/E
TA
+125
°C
CS1-4 capacitance
CCS
CI/O
CAD
V
IN = 0 V, f = 1.0 MHz
I/O = 0 V, f = 1.0 MHz
IN = 0 V, f = 1.0 MHz
20
20
50
pF
pF
pF
Data I/O capacitance
Address input capacitance
V
V
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
Conditions
Units
Min
Max
Input Leakage Current
Output Leakage Current
ILI
ILO
VCC = 5.5, VIN = GND to VCC
10
µA
µA
mA
mA
V
CS = VIH, OE = VIH, VOUT = GND to VCC
CS = VIL, OE = VIH, f = 5MHz, Vcc = 5.5
CS = VIH, OE = VIH, f = 5MHz, Vcc = 5.5
10
540
80
Operating Supply Current x 32 Mode
Standby Current
ICC x 32
ISB
Output Low Voltage
VOL
IOL = 8mA for 15 - 35ns,
0.4
IOL = 2.1mA for 45 - 55ns, Vcc = 4.5
Output High Voltage
VOH
IOH = -4.0mA for 15 - 35ns,
2.4
V
IOH = -1.0mA for 45 - 55ns, Vcc = 4.5
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
DATA RETENTION CHARACTERISTICS
(TA = -55°C to +125°C)
Parameter
Symbol
Conditions
Units
Min
Typ
Max
Data Retention Supply Voltage
Data Retention Current
VDR
CS ≥ VCC -0.2V
2.0
5.5
V
ICCDR1
VCC = 3V
3.2
28*
mA
* Also available in Low Power version, please call factory for information.
3
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WS512K32-XXX /
EDI8C32512CA
AC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Read Cycle
Symbol
-15*
-17
-20
-25
-35
-45
-55
Units
Min Max Min Max
Min Max Min Max Min
Max Min Max
Min Max
Read Cycle Time
tRC
tAA
15
0
17
0
20
0
25
0
35
0
45
55
55
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
15
17
20
25
35
45
Output Hold from Address Change
Chip Select Access Time
tOH
0
tACS
tOE
15
8
17
9
20
10
25
12
35
25
45
25
55
25
4
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
tCLZ1
tOLZ1
tCHZ1
tOHZ1
2
0
2
0
2
0
2
0
4
0
4
0
0
12
12
12
12
12
12
12
12
15
15
20
20
20
20
*
15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice.
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
-15*
-17
-20
-25
-35
-45
-55
Units
Write Cycle
Min Max Min Max
Min Max
Min Max Min
Max Min
Max Min Max
Write Cycle Time
tWC
tCW
tAW
tDW
tWP
15
13
13
10
13
2
17
15
15
11
15
2
20
15
15
12
15
2
25
17
17
13
17
2
35
25
25
20
25
2
45
35
35
25
35
2
55
50
50
25
40
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
tAS
tAH
0
0
0
0
0
5
5
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
tOW1
tWHZ1
tDH
2
2
3
4
4
5
5
8
9
11
13
15
20
20
0
0
0
0
0
0
0
*
15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice.
1. This parameter is guaranteed by design but not tested.
2. The Address Setup Time of minimum 2ns is for the G2T and H1 packages. tAS minimum for the G4T package is 0ns.
AC TEST CONDITIONS
FIG. 4
AC TEST CIRCUIT
IOL
Parameter
Typ
Unit
V
Current Source
Input Pulse Levels
VIL = 0, VIH = 3.0
Input Rise and Fall
5
ns
V
Input and Output Reference Level
Output Timing Reference Level
1.5
1.5
V
VZ
≈ 1.5V
D.U.T.
(Bipolar Supply)
Ceff = 50 pf
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
IOH
Current Source
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
4
WS512K32-XXX /
EDI8C32512CA
FIG. 5
tRC
TIMING WAVEFORM - READ CYCLE
ADDRESS
CS
tAA
tRC
tCHZ
tACS
tCLZ
ADDRESS
tAA
OE
tOE
tOLZ
tOH
tOHZ
DATA I/O
DATA I/O
PREVIOUS DATA VALID
DATA VALID
DATA VALID
HIGH IMPEDANCE
READ CYCLE 1 (CS = OE = V , WE = V
IL
)
IH
READ CYCLE 2 (WE = V
IH
)
FIG. 6
WRITE CYCLE - WE CONTROLLED
tWC
ADDRESS
tAW
tAH
tCW
CS
tAS
tWP
WE
tOW
tDH
tWHZ
tDW
DATA I/O
DATA VALID
WRITE CYCLE 1, WE CONTROLLED
FIG. 7
WRITE CYCLE - CS CONTROLLED
tWC
ADDRESS
WS32K32-XHX
tAW
tAH
tAS
tCW
CS
tWP
WE
tDW
tDH
DATA I/O
DATA VALID
WRITE CYCLE 2, CS CONTROLLED
5
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WS512K32-XXX /
EDI8C32512CA
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
27.3 (1.075) ± 0.25 (0.010) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
4.34 (0.171)
MAX
3.81 (0.150)
± 0.13 (0.005)
1.42 (0.056) ± 0.13 (0.005)
0.76 (0.030) ± 0.13 (0.005)
2.54 (0.100)
TYP
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
25.4 (1.0) TYP
0.46 (0.018) ± 0.05 (0.002) DIA
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 502: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G4T)
3.56 (0.140) MAX
39.6 (1.56) ± 0.38 (0.015) SQ
PIN 1 IDENTIFIER
Pin 1
12.7 (0.500)
± 0.5 (0.020)
4 PLACES
5.1 (0.200)
± 0.25 (0.010)
4 PLACES
0.25 (0.010)
0.38 (0.015)
± 0.08 (0.003)
± 0.05 (0.002)
1.27 (0.050)
TYP
68 PLACES
38 (1.50) TYP
4 PLACES
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
6
WS512K32-XXX /
EDI8C32512CA
PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T/E)
25.15 (0.990) ± 0.26 (0.010) SQ
4.57 (0.180) MAX
22.36 (0.880) ± 0.26 (0.010) SQ
0.27 (0.011) ± 0.04 (0.002)
Pin 1
0.25 (0.010) REF
R 0.25
24.03 (0.946)
(0.010)
± 0.26 (0.010)
0.19 (0.007)
± 0.06 (0.002)
1° / 7°
1.0 (0.040)
± 0.127 (0.005)
23.87
(0.940) REF
DETAIL A
1.27 (0.050) TYP
SEE DETAIL "A"
0.38 (0.015) ± 0.05 (0.002)
20.3 (0.800) REF
The White 68 lead G2T CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2T has the TCE
and lead inspection advantage
of the CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
7
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WS512K32-XXX /
EDI8C32512CA
ORDERING INFORMATION
NOTE: For non-SMD new designs, please use the WS128K32-XXX part number for inquiries and orders.
W S 512K 32 X - XXX X X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
Q = MIL-STD-883 Compliant
M= Military Screened-55°C to +125°C
I = Industrial
-40°C to 85°C
0°C to +70°C
C = Commercial
PACKAGE TYPE:
H1 = Ceramic Hex-In-line Package, HIP (Package 400)
G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509)
G4T = 40mm Low Profile CQFP (Package 502)
ACCESS TIME (ns)
IMPROVEMENT MARK:
N = No Connect at pin 21 and 39 in HIP for Upgrades
ORGANIZATION, 512Kx32
User configurable as 1Mx16 or 2Mx8
SRAM
WHITE ELECTRONIC DESIGNS CORP.
EDI 8 C 32 512 CA X E X
WHITE ELECTRONIC DESIGNS
SRAM
CERAMIC MCM
ORGANIZATION, 512Kx32
TECHNOLOGY:
CA = CMOS Standard Power
LPA = Low Power *
ACCESS TIME (ns)
PACKAGE TYPE:
E = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 509)
DEVICE GRADE:
B = MIL-STD-883 Compliant
M= Military Screened
I = Industrial
C = Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
* Low Power Data Retention only available in G2T/E Package Type
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
8
WS512K32-XXX /
EDI8C32512CA
DEVICE TYPE
SPEED
PACKAGE
SMD NO.
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
55ns
45ns
35ns
25ns
20ns
17ns
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
5962-94611 05HTX
5962-94611 06HTX
5962-94611 07HTX
5962-94611 08HTX
5962-94611 09HTX
5962-94611 10HTX
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
55ns
45ns
35ns
25ns
20ns
17ns
68 lead CQFP Low Profile (G4T)
68 lead CQFP Low Profile (G4T)
68 lead CQFP Low Profile (G4T)
68 lead CQFP Low Profile (G4T)
68 lead CQFP Low Profile (G4T)
68 lead CQFP Low Profile (G4T)
5962-94611 05HYX
5962-94611 06HYX
5962-94611 07HYX
5962-94611 08HYX
5962-94611 09HYX
5962-94611 10HYX
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
55ns
45ns
35ns
25ns
20ns
17ns
68 lead CQFP/J (G2T)
68 lead CQFP/J (G2T)
68 lead CQFP/J (G2T)
68 lead CQFP/J (G2T)
68 lead CQFP/J (G2T)
68 lead CQFP/J (G2T)
5962-94611 05HMX
5962-94611 06HMX
5962-94611 07HMX
5962-94611 08HMX
5962-94611 09HMX
5962-94611 10HMX
9
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
相关型号：
WS512K32-17G2UC
SRAM Module, 512KX32, 17ns, CMOS, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WS512K32-17G2UCA
SRAM Module, 512KX32, 17ns, CMOS, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WS512K32-17G2UI
SRAM Module, 512KX32, 17ns, CMOS, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WS512K32-17G2UM
SRAM Module, 512KX32, 17ns, CMOS, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WS512K32-17G4TCA
SRAM Module, 512KX32, 17ns, CMOS, CQFP68, 40 X 40 MM, 3.50 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
©2020 ICPDF网 联系我们和版权申明