WSF2816-39H1X [ETC]
SRAM/Flash MCP ; SRAM /闪存MCP
| 型号： | WSF2816-39H1X |
| 厂家： | 
ETC |
| 描述： | SRAM/Flash MCP
|
| 文件： | 总15页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WSF2816-39XX
128KX16 SRAM/512KX16 FLASH MODULE
■ Built-in Decoupling Caps and Multiple Ground Pins for
FEATURES
■ Access Times of 35ns (SRAM) and 90ns (FLASH)
Low Noise Operation
■ Weight:
■ Packaging
WSF2816-39G2UX - 8 grams typical
WSF2816-39H1X - 13 grams typical
• 66 pin, PGA Type, 1.075" square HIP, Hermetic
Ceramic HIP (Package 400)
FLASH MEMORY FEATURES
■ 100,000 Erase/Program Cycles
■ Sector Architecture
• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880") square
(Package 510) 3.56mm (0.140") height. Designed to fit
JEDEC 68 lead 0.990” CQFJ footprint (Fig. 2)
■ 128Kx16 SRAM
• 8 equal size sectors of 64K bytes each
■ 512Kx16 5V FLASH
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
■ Organized as 128Kx16 of SRAM and 512Kx16 of Flash
Memory with separate Data Buses
■ 5 Volt Programming; 5V ± 10% Supply
■ Embedded Erase and Program Algorithms
■ Hardware Write Protection
■ Both blocks of memory are User Configurable as 256Kx8
■ Low Power CMOS
■ Commercial, Industrial and Military Temperature Ranges
■ TTL Compatible Inputs and Outputs
Note: For programming information refer to Flash Programming 4M5
Application Note.
FIG. 1 PIN CONFIGURATION FOR WSF2816-39H1X
TOP VIEW
PIN DESCRIPTION
1
12
23
34
45
56
FD0-15 Flash Data Inputs/Outputs
SD0-15 SRAM Data Inputs/Outputs
SD
8
9
SWE
2
SD15
SD14
SD13
SD12
OE
FD
8
9
V
CC
FD15
FD14
FD13
FD12
A0-18
SWE1-2
SCS1-2
OE
Address Inputs
SRAM Write Enable
SRAM Chip Selects
Output Enable
SD
SCS
GND
SD11
2
FD
FCS
2
2
SD10
FD10
FWE
A
A
A
A
A
13
14
15
16
18
A
A
6
7
FD11
VCC
Power Supply
A
A
A
V
10
11
12
CC
A
A
3
4
5
1
1
A
0
1
2
7
6
5
4
GND
NC
Ground
A
17
NC
A
Not Connected
Flash Write Enable
Flash Chip Select
SWE
1
A
A
8
9
0
1
2
A
A
FWE1-2
FCS1-2
SD7
SD6
SD5
SD4
FWE
FCS
FD
FD
FD
FD
SD0
SD1
SD2
SCS
NC
1
FD
FD
FD
BLOCK DIAGRAM
GND
FD
SD3
3
11
22
33
44
55
66
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
November 2003 Rev. 5
WSF2816-39XX
FIG. 2 PIN CONFIGURATION FOR WSF2816-39G2UX
TOP VIEW
PIN DESCRIPTION
FD0-15 Flash Data Inputs/Outputs
SD0-15 SRAM Data Inputs/Outputs
A0-18
Address Inputs
SWE1-2 SRAM Write Enable
SCS1-2 SRAM Chip Selects
OE
VCC
GND
NC
Output Enable
Power Supply
Ground
The White 68 lead G2U CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2U has the TCE
and lead inspection advantage
of the CQFP form.
Not Connected
FWE1-2 Flash Write Enable
FCS1-2 Flash Chip Select
BLOCK DIAGRAM
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2
WSF2816-39XX
ABSOLUTE MAXIMUM RATINGS
SRAM TRUTH TABLE
Parameter
Symbol
TA
Min
-55
-65
-0.5
Max
+125
+150
7.0
Unit
°C
°C
V
SCS
H
OE
X
SWE
X
Mode
Standby
Read
Data I/O
High Z
Power
Standby
Active
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
L
L
H
Data Out
High Z
TSTG
VG
L
H
H
Read
Active
L
X
L
Write
Data In
Active
TJ
150
°C
V
VCC
-0.5
7.0
CAPACITANCE
Parameter
(TA = +25°C)
Flash Data Retention
20 years
100,000
Flash Endurance (write/erase cycles)
Test
Symbol
COE
Condition
Max Unit
OE Capacitance
VIN = 0V, f = 1.0MHz 50
pF
pF
pF
pF
pF
NOTES:
1. Stresses above the absolute maximum rating may cause permanent damage
to the device. Extended operation at the maximum levels may degrade
performance and affect reliability.
WE Capacitance
CWE
VIN = 0V, f = 1.0MHz 20
VIN = 0V, f = 1.0MHz 20
VIN = 0V, f = 1.0MHz 20
VIN = 0V, f = 1.0MHz 50
CS Capacitance
CCS
Data I/O Capacitance
Address Line Capacitance
CI/O
CAD
RECOMMENDED OPERATING CONDITIONS
This parameter is guaranteed by design but not tested.
Parameter
Symbol
VCC
Min
4.5
Max
5.5
Unit
V
Supply Voltage
Input High Voltage
Input Low Voltage
VIH
2.2
VCC + 0.3
+0.8
V
VIL
-0.5
V
DC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
Conditions
Min
Max
Unit
Input Leakage Current
ILI
VCC = 5.5, VIN = GND to VCC
10
µA
Output Leakage Current
ILO
ICCx16
ISB
SCS = VIH, OE = VIH, VOUT = GND to VCC
SCS = VIL, OE = FCS = VIH, f = 5MHz, VCC = 5.5
FCS = SCS = VIH, OE = VIH, f = 5MHz, VCC = 5.5
IOL = 8.0mA, VCC = 4.5
10
325
20
µA
mA
mA
V
SRAM Operating Supply Current x 16 Mode
Standby Current
SRAM Output Low Voltage
VOL
VOH
ICC1
ICC2
0.4
SRAM Output High Voltage
Flash VCC Active Current for Read (1)
IOH = -4.0mA, VCC = 4.5
2.4
V
FCS = VIL, OE = SCS = VIH
120
140
mA
mA
Flash VCC Active Current for Program or
Erase (2)
FCS = VIL, OE = SCS = VIH
Flash Output Low Voltage
Flash Output High Voltage
Flash Output High Voltage
Flash Low VCC Lock Out Voltage
NOTES:
VOL
VOH1
VOH2
VLKO
IOL = 8.0mA, VCC = 4.5
IOH = -2.5 mA, VCC = 4.5
IOH = -100 µA, VCC = 4.5
0.45
V
V
V
V
0.85 x VCC
VCC -0.4
3.2
1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
3
WhiteElectronicDesignsCorporation•(602)437-1520•www.whiteedc.com
WSF2816-39XX
SRAM AC CHARACTERISTICS
(VCC = 5.0V, TA = -55°C to +125°C)
SRAM AC CHARACTERISTICS
(VCC = 5.0V, TA = -55°C to +125°C)
Parameter
Read Cycle
Symbol
-35
Unit
Parameter
Write Cycle
Symbol
-35
Unit
Min
35
25
25
20
25
0
Max
Min
Max
Write Cycle Time
tWC
tCW
tAW
tDW
tWP
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
tRC
tAA
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Access Time
35
Output Hold from Address Change
Chip Select Access Time
tOH
tACS
tOE
0
35
20
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
1
Address Setup Time
tCLZ
3
0
1
Address Hold Time
tAH
0
tOLZ
1
1
Output Active from End of Write
Write Enable to Output in High Z
Data Hold from Write Time
tOW
4
tCHZ
20
20
1
1
tWHZ
20
tOHZ
tDH
0
1. This parameter is guaranteed by design but not tested.
1. This parameter is guaranteed by design but not tested.
FIG. 3
AC TEST CIRCUIT
AC TEST CONDITIONS
UNIT
PARAMETER
TYP
Input Pulse Levels
VIL = 0, VIH = 3.0
V
ns
V
Input Rise and Fall
5
Input and Output Reference Level
Output Timing Reference Level
1.5
1.5
V
˜
˜
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOHare adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
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4
WSF2816-39XX
FIG. 4 SRAM
tRC
TIMING WAVEFORM - READ CYCLE
ADDRESS
SCS
tAA
tRC
tCHZ
tACS
tCLZ
ADDRESS
tAA
SOE
tOE
tOLZ
tOH
tOHZ
DATA I/O
DATA I/O
DATA VALID
PREVIOUS DATA VALID
DATA VALID
HIGH IMPEDANCE
READ CYCLE 2, (SWE = V
)
READ CYCLE 1, (SCS = OE = V , SWE = V
IL IH
)
IH
FIG. 5 SRAM
WRITE CYCLE - SWE CONTROLLED
tWC
ADDRESS
tAW
tAH
tCW
SCS
SWE
tAS
tWP
tOW
tDH
tWHZ
tDW
DATA I/O
DATA VALID
WRITE CYCLE 1, SWE CONTROLLED
FIG. 6 SRAM
WRITE CYCLE - SCS CONTROLLED
t
CW
WS32K32-XHX
ADDRESS
t
WA
t
t
AS
AH
t
CW
SCS
t
WP
SWE
t
t
DH
DW
DATA I/O
DATA VALID
WRITE CYCLE 2, SCS CONTROLLED
5
WhiteElectronicDesignsCorporation•(602)437-1520•www.whiteedc.com
WSF2816-39XX
FLASH AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, FWE CONTROLLED
(VCC = 5.0V, TA = -55°C to +125°C)
Parameter
Symbol
-90
Unit
Min
90
0
Max
Write Cycle Time
tAVAV
tELWL
tWC
tCS
ns
ns
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
tWLWH
tAVWL
tDVWH
tWHDX
tWLAX
tWHEH
tWHWL
tWHWH1
tWHWH2
tGHWL
tWP
tAS
45
0
ns
ns
Data Setup Time
tDS
45
0
ns
Data Hold Time
tDH
tAH
tCH
tWPH
ns
Address Hold Time
45
0
ns
Chip Select Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time Before Write
VCC Set-up Time
ns
20
ns
300
15
µs
sec
µs
µs
sec
ns
0
tVCS
50
Chip Programming Time
Output Enable Setup Time
Output Enable Hold Time (4)
Chip Erase Time
11
64
tOES
tOEH
0
10
ns
sec
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH1 is 1sec.
3. Typical value for Chip Erase Time is 8sec.
4. For Toggle and Data Polling.
FLASH AC CHARACTERISTICS – READ ONLY OPERATIONS
(VCC = 5.0V, TA = -55°C TO +125°C)
Parameter
Symbol
-90
Unit
Min
Max
Read Cycle Time
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tRC
tACC
tCE
tOE
tDF
90
ns
ns
ns
ns
ns
ns
ns
Address Access Time
90
90
35
20
20
Chip Select Access Time
OE to Output Valid
Chip Select to Output High Z (1)
OE High to Output High Z (1)
Output Hold from Address, CS or OE Change, whichever is first
1. Guaranteed by design, not tested.
tDF
tOH
0
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6
WSF2816-39XX
FLASH AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, FCS CONTROLLED
(VCC = 5.0V, TA = -55°C TO +125°C)
Parameter
Symbol
-90
Unit
Min
90
0
Max
Write Cycle Time
tAVAV
tWC
tWS
tCP
ns
ns
FWE Setup Time
tWLEL
tELEH
FCS Pulse Width
45
0
ns
Address Setup Time
tAVEL
tAS
ns
Data Setup Time
tDVEH
tEHDX
tELAX
tDS
45
0
ns
Data Hold Time
tDH
tAH
tWH
tCPH
ns
Address Hold Time
45
0
ns
FWE Hold from FWE High
FCS Pulse Width High
Duration of Byte Programming Operation (1)
Duration of Erase Operation (2)
Read Recovery before Write
Chip Programming Time
Chip Erase Time (3)
tEHWH
tEHEL
ns
20
ns
tWHWH1
tWHWH2
tGHEL
300
15
ms
sec
ns
0
11
sec
sec
64
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH1 is 1sec.
3. Typical value for Chip Erase Time is 8sec.
7
WhiteElectronicDesignsCorporation•(602)437-1520•www.whiteedc.com
WSF2816-39XX
FIG. 7
AC WAVEFORMS FOR FLASH MEMORY READ
OPERATIONS
WhiteElectronicDesignsCorporation•(602)437-1520•www.whiteedc.com
8
WSF2816-39XX
FIG. 8
WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE CONTROLLED
NOTES:
1. PA is the address of the memory location to be
programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the output of the complement of the data
written to the device.
4. DOUT is the output of the data written to
the device.
5. Figure indicates last two bus cycles of four bus
cycle sequence.
9
WhiteElectronicDesignsCorporation•(602)437-1520•www.whiteedc.com
WSF2816-39XX
FIG. 9
AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FLASH MEMORY
NOTES:
1. SA is the sector address for
Sector Erase.
WhiteElectronicDesignsCorporation•(602)437-1520•www.whiteedc.com
10
WSF2816-39XX
FIG. 10
AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS
FOR FLASH MEMORY
11
WhiteElectronicDesignsCorporation•(602)437-1520•www.whiteedc.com
WSF2816-39XX
FIG. 11
WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS CONTROLLED
NOTES:
1. PArepresentstheaddressofthememorylocationtobeprogrammed.
2. PDrepresentsthedatatobeprogrammedatbyteaddress.
3. D7istheoutputofthecomplementofthedatawrittentothedevice.
4. DOUTistheoutputofthedatawrittentothedevice.
5. Figureindicatesthelasttwobuscyclesofafourbuscyclesequence.
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12
WSF2816-39XX
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
13
WhiteElectronicDesignsCorporation•(602)437-1520•www.whiteedc.com
WSF2816-39XX
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
The White 68 lead G2U CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2U has the TCE
and lead inspection advantage
of the CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
WhiteElectronicDesignsCorporation•(602)437-1520•www.whiteedc.com
14
WSF2816-39XX
ORDERING INFORMATION
W S F 2816 - 39 X X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
M = Military Screened -55°C to +125°C
I
=
Industrial
-40°C to +85°C
0°C to +70°C
C = Commercial
PACKAGE TYPE:
H1= 1.075" sq. Ceramic Hex In-line Package, HIP (Package 400)
G2U = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 510)
ACCESS TIME (ns)
39 = 35ns SRAM and 90ns FLASH
2Mbit of SRAM and 8Mbit of Flash
ORGANIZATION: 128K x 16 SRAM and
512K x 16 Flash
Flash
SRAM
WHITE ELECTRONIC DESIGNS CORP.
15
WhiteElectronicDesignsCorporation•(602)437-1520•www.whiteedc.com
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