MR1A16AMA35 [EVERSPIN]
128K x 16 MRAM Memory;型号: | MR1A16AMA35 |
厂家: | Everspin Technologies |
描述: | 128K x 16 MRAM Memory |
文件: | 总20页 (文件大小:1066K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MR1A16A
128K x 16 MRAM Memory
FEATURES
• Fast 35 ns Read/Write cycle
• SRAM compatible timing, uses existing SRAM control-
lers without redesign
• Unlimited Read & Write endurance
• Data non-volatile for >20 years at temperature
• One memory replaces Flash, SRAM, EEPROM and
BBSRAM in a system for simpler, more efficient design
• Replaces battery-backed SRAM solutions with MRAM
to improve reliability
44-pin TSOP2
• 3.3 volt power supply
• Automatic data protection on power loss
• Commercial, Industrial, Extended temperatures
• AEC-Q100 Grade 1 option
48-ball BGA
• All products meet MSL-3 moisture sensitivity level
• RoHS-compliant SRAM TSOP2 and BGA Packages
INTRODUCTION
The MR1A16A is a 2,097,152-bit magnetoresistive random access memory (MRAM) device orga-
nized as 131,072 words of 16 bits. The MR1A16A offers SRAM compatible 35 ns read/write timing
with unlimited endurance. Data is always non-volatile for greater than 20 years. Data is automati-
cally protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of
specification.
The MR1A16A is the ideal memory solution for applications that must permanently store and re-
trieve critical data and programs quickly.
The MR1A16A is available in a small footprint 48-pin ball grid array (BGA) package and a 44-pin thin
small outline package (TSOP Type 2). These packages are compatible with similar low-power SRAM
products and other nonvolatile RAM products.
The MR1A16A provides highly reliable data storage over a wide range of temperatures. The prod-
uct is offered with Commercial (0 to +70 °C), Industrial (-40 to +85 °C), Extended (-40 to +105 °C),
and AEC-Q100 Grade 1 (-40 to +125 °C) operating temperature range options.
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MR1A16A Rev. 1.1 03/2020
MR1A16A
TABLE OF CONTENTS
FEATURES .............................................................................................................................................1
INTRODUCTION ...................................................................................................................................1
BLOCK DIAGRAM AND PIN ASSIGNMENTS.......................................................................................4
Figure 1 – Block Diagram........................................................................................................................................... 4
Table 1 – Pin Functions............................................................................................................................................... 4
Figure 2 – Pin Diagrams for Available Packages (Top View).......................................................................... 5
Table 2 – Operating Modes....................................................................................................................................... 5
ABSOLUTE MAXIMUM RATINGS.........................................................................................................6
Table 3 – Absolute Maximum Ratings................................................................................................................... 6
OPERATING CONDITIONS ...................................................................................................................7
Power Up and Power Down Sequencing .......................................................................................8
Figure 3 – Power Up and Power Down Diagram............................................................................................... 8
DC CHARACTERISTICS.........................................................................................................................9
Table 4 – DC Characteristics...................................................................................................................................... 9
Table 5 – Power Supply Characteristics................................................................................................................ 9
TIMING SPECIFICATIONS ................................................................................................................. 10
Table 6 – Capacitance ...............................................................................................................................................10
Table 7 – AC Measurement Conditions ..............................................................................................................10
Figure 4 – Output Load Test Low and High.......................................................................................................10
Figure 5 – Output Load Test All Others...............................................................................................................10
Read Mode .................................................................................................................................... 11
Table 8 – Read Cycle Timing ...................................................................................................................................11
Figure 6 – Read Cycle 1.............................................................................................................................................11
Figure 7 – Read Cycle 2.............................................................................................................................................11
Write Mode.................................................................................................................................... 12
Table 9 – Write Cycle Timing 1 (W Controlled).................................................................................................12
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MR1A16A
TABLE OF CONTENTS (CONT’D)
Figure 8 – Write Cycle Timing 1 (W Controlled) ...............................................................................................12
Table 10 – Write Cycle Timing 2 (E Controlled) ................................................................................................13
Figure 9 – Write Cycle Timing 2 (E Controlled).................................................................................................13
Table 11 – Write Cycle Timing 3 (LB / UB Controlled)....................................................................................14
Figure 10 – Write Cycle Timing 3 (LB / UB Controlled)..................................................................................14
ORDERING INFORMATION ............................................................................................................... 15
Table 12 – Ordering Part Number System for Parallel I/O MRAM..............................................................15
Table 13 – MR1A16A Ordering Part Numbers..................................................................................................16
PACKAGE OUTLINE DRAWINGS....................................................................................................... 17
Figure 11 – 44-TSOP2 Package Outline...............................................................................................................17
Figure 12 – 48-FBGA Packge Outline...................................................................................................................18
REVISION HISTORY ........................................................................................................................... 19
HOW TO CONTACT US....................................................................................................................... 20
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MR1A16A
BLOCK DIAGRAM AND PIN ASSIGNMENTS
Figure 1 – Block Diagram
ꢆꢇꢀꢄꢈ0ꢉ
ꢀꢊ
ꢅ
ꢀ2ꢁꢂ ꢃ ꢀꢄ
Table 1 – Pin Functions
Signal Name
Function
A
Address Input
E
Chip Enable
W
G
Write Enable
Output Enable
Upper Byte Enable
Lower Byte Enable
Data I/O
UB
LB
DQ
VDD
VSS
DC
NC
Power Supply
Ground
Do Not Connect
No Connection
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MR1A16A
Figure 2 – Pin Diagrams for Available Packages ꢀTop Viewꢁ
Aꢀ
Aꢁ
Aꢂ
Aꢃ
Aꢇ
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Aꢁꢈ
Aꢁꢉ
Aꢁꢇ
G
3
4
ꢀ
2
ꢁ
ꢂ
ꢃ
ꢄ
5
UB
ꢅꢆ
ꢇ
ꢈ0
ꢈꢀ
ꢈ2
ꢉC
ꢈ
ꢆ
C
ꢊ
E
6
E
LB
7
DQL0
DQL1
DQL2
DQL3
DQU15
DQU14
DQU13
DQU12
ꢊꢋꢌꢍ
ꢊꢋꢌꢎ
ꢊꢋꢅ0
ꢊꢋꢅ2
ꢌꢆ
ꢈꢁ
ꢈꢃ
8
ꢈꢂ
ꢈꢄ
E
9
10
11
12
13
14
15
16
17
18
19
20
21
22
ꢊꢋꢌꢀ0
ꢊꢋꢌꢀꢀ
ꢊꢋꢌꢀ2
ꢊꢋꢌꢀꢁ
ꢉC
ꢊꢋꢅꢀ
ꢊꢋꢅꢁ
V
DD
VSS
V
SS
VDD
ꢏꢐꢐ
ꢏꢊꢊ
ꢈꢀꢄ
ꢈꢀꢂ
ꢈꢀꢁ
ꢈꢀꢀ
ꢈꢎ
ꢈꢀꢃ
ꢉC
DQL4
DQL5
DQL6
DQL7
W
Aꢉ
Aꢈ
Aꢄ
Aꢅ
DQU11
DQU10
DQU9
DQU8
DC
VDD
Aꢁꢃ
Aꢁꢂ
Aꢁꢁ
ꢏꢊꢊ
ꢊꢋꢅꢂ
ꢊꢋꢅꢃ
ꢏꢐꢐ
ꢑ
ꢊꢋꢌꢀꢂ
ꢊꢋꢌꢀꢃ
ꢉC
ꢊꢋꢅꢄ
ꢊꢋꢅꢓ
ꢊC
ꢈꢀ2
ꢈꢀ0
ꢈꢍ
ꢇ
ꢔ
ꢒ
ꢈꢓ
ꢏꢊꢊ
Aꢆ
Aꢁꢀ
44-Pin TSOP Type2
48-Pin BGA
Table 2 – Operating Modes
E 1 G1 W 1 LB 1 UB1
Mode
VDD Current DQL[7:0]2 DQU[15:8]2
H
L
L
L
L
L
L
L
L
X
H
X
L
X
H
X
H
H
H
L
X
X
H
L
X
X
H
H
L
Not selected
ISB1, ISB2
Hi-Z
Hi-Z
Hi-Z
DOut
Hi-Z
DOut
Din
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DOut
DOut
Hi-Z
Din
Output disabled
Output disabled
Lower Byte Read
Upper Byte Read
Word Read
IDDR
IDDR
IDDR
L
H
L
IDDR
L
L
IDDR
X
X
X
L
H
L
Lower Byte Write
Upper Byte Write
Word Write
IDDW
IDDW
IDDW
L
H
L
Hi-Z
Din
L
L
Din
Notes:
1. H = high, L = low, X = don’t care
2. Hi-Z = high impedance
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MR1A16A
ABSOLUTE MAXIMUM RATINGS
Table 3 – Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it
is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these
high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any
1
magnetic field more intense than the maximum field intensity specified in the maximum ratings.
Symbol Parameter
Temp Range
Package
Value
Unit
VDD
VIN
Supply voltage 2
-
-
-0.5 to 4.0
V
Voltage on any pin 2
Output current per pin
Package power dissipation 3
-
-
-
-0.5 to VDD + 0.5
V
mA
W
-
IOUT
PD
-
20
Note 3
0.600
Commercial
Industrial
-
-
-
-
-10 to 85
-45 to 95
-45 to 110
-45 to 130
TBIAS
Temperature under bias
°C
Extended
AEC-Q100 Grade 1
Tstg
Storage Temperature
-
-
-
-55 to 150
260
°C
°C
Lead temperature during solder
(3 minute max)
TLead
-
Commercial
TSOP2, BGA
BGA
2,000
2,000
10,000
2,000
8,000
8,000
10,000
8,000
Maximum magnetic field during
write
Hmax_write
Industrial, Extended
A/m
A/m
TSOP2
AEC-Q100 Grade 1
Commercial
TSOP2
TSOP2, BGA
BGA
Maximum magnetic field during
read or standby
Hmax_read
Industrial, Extended
AEC-Q100 Grade 1
TSOP2
TSOP2
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted
to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability.
2. All voltages are referenced to VSS.
3. Power dissipation capability depends on package characteristics and use environment.
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MR1A16A
OPERATING CONDITIONS
Parameter
Symbol
Min
3.0
Typical
Max
3.6
3.0 1
Unit
Power supply voltage 1
Write inhibit voltage
Input high voltage
Input low voltage
3.3
2.7
-
V
V
V
V
VDD
VWI
VIH
VIL
2.5
2.2
-0.5 3
VDD + 0.3 2
-
0.8
Temperature under bias
MR1A16A (Commercial)
MR1A16AC (Industrial)
0
70
85
105
125
TA
-40
-40
-40
°C
MR1A16AV (Extended)
MR1A16AM (AEC-Q100 Grade 1) 4
Notes:
1. There is a 2 ms startup time once VDD exceeds VDD,(max). See “Power Up and Power Down Sequencing”on page 8.
2. VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
3. VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
4. AEC-Q100 Grade 1 temperature profile assumes 10% duty cycle at maximum temperature (2 years out of 20 years life.)
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MR1A16A
Power Up and Power Down Sequencing
The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds
VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory
power supplies to stabilize.
The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and
remain high for the startup time. In most systems, this means that these signals should be pulled up with a
resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and
W should hold the signals high with a power-on reset signal for longer than the startup time.
During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be
observed when power returns above VDD(min).
Figure 3 – Power Up and Power Down Sequencing Timing Diagram
VDD
V
WI
BROWNOUT or POWER LOSS
2 ms
2 ms
STARTUP
RECOVER
NORMAL
OPERATION
NORMAL
OPERATION
READ/WRITE
INHIBITED
READ/WRITE
INHIBITED
VIH
VIH
E
W
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MR1A16A
DC CHARACTERISTICS
Table 4 – DC Characteristics
Parameter
Symbol
Min
Typical
Max
Unit
I
Input leakage current
-
-
1
μA
lkg(I)
I
Output leakage current
-
-
-
-
1
μA
V
lkg(O)
Output low voltage
(IOL = +4 mA)
(IOL = +100 μA)
0.4
VSS + 0.2
V
OL
Output high voltage
(IOH = -4 mA)
(IOH = -100 μA)
2.4
VDD - 0.2
-
-
V
V
OH
Table 5 – Power Supply Characteristics
Parameter
Symbol
Typical
Max
Unit
AC active supply current - read modes1
(IOUT= 0 mA, VDD= max)
55
80
mA
I
DDR
AC active supply current - write modes1
(VDD= max)
Commercial Grade
Industrial Grade
Extended Grade
AEC-Q100 Grade
105
105
105
105
155
165
165
165
mA
mA
mA
I
DDW
AC standby current
(VDD= max, E = VIH)
no other restrictions on other inputs
18
9
28
12
I
SB1
CMOS standby current
(E ≥ VDD - 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDD - 0.2 V)
(VDD = max, f = 0 MHz)
I
SB2
Notes:
1. All active current measurements are measured with one address transition per cycle and at minimum cycle time.
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MR1A16A
TIMING SPECIFICATIONS
Table 6 – Capacitance
Parameter 1
Symbol
Typical
Max
Unit
C
Address input capacitance
-
6
pF
In
C
Control input capacitance
-
-
6
8
pF
pF
In
C
Input/Output capacitance
I/O
Notes:
1. f = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.
Table 7 – AC Measurement Conditions
Parameter
Value
1.5
Unit
V
Logic input timing measurement reference level
Logic output timing measurement reference level
Logic input pulse levels
1.5
V
0 or 3.0
2
V
Input rise/fall time
ns
Output load for low and high impedance parameters
Output load for all other timing parameters
See Figure 4
See Figure 5
Figure 4 – Output Load Test Low and High
ZD= 50 Ω
Output
RL = 50 Ω
VL = 1.5 V
Figure 5 – Output Load Test All Others
3.3 V
590 Ω
Output
5 pF
435 Ω
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MR1A16A
Read Mode
Table 8 – Read Cycle Timing
Parameter 1
Symbol
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Read cycle time
AVAV
35
-
-
tAVQV
tELQV
tGLQV
tBLQV
tAXQX
tELQX
tGLQX
tBLQX
tEHQZ
tGHQZ
tBHQZ
Address access time
Enable access time2
35
35
15
15
-
-
Output enable access time
Byte enable access time
Output hold from address change
Enable low to output active3
Output enable low to output active3
Byte enable low to output active3
Enable high to output Hi-Z3
Output enable high to output Hi-Z3
Byte high to output Hi-Z3
-
-
3
3
0
0
0
0
0
-
-
-
15
10
10
Notes:
1. W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must
be minimized or eliminated during read or write cycles.
2. Addresses valid before or at the same time E goes low.
3. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage.
Figure 6 – Read Cycle 1
tAVAV
A (ADDRESS)
tAXQX
Previous Data Valid
Data Valid
Q (DATA OUT)
tAVQV
Note: Device is continuously selected (E ≤ VIL, G ≤ VIL).
Figure 7 – Read Cycle 2
tAVAV
A (ADDRESS)
E (CHIP ENABLE)
tAVQV
tELQV
tEHQZ
tELQX
G (OUTPUT ENABLE)
LB, UB (BYTE ENABLE)
tGHQZ
tGLQV
tGLQX
tBHQZ
tBLQV
tBLQX
Data Valid
Q (DATA OUT)
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MR1A16A
Write Mode
Table 9 – Write Cycle Timing 1 ꢀW Controlledꢁ
Parameter 1
Symbol
tAVAV
tAVWL
tAVWH
tAVWH
Min
35
0
Max
Unit
ns
2
Write cycle time
-
-
-
-
Address set-up time
ns
Address valid to end of write (G high)
Address valid to end of write (G low)
18
20
ns
ns
tWLWH
Write pulse width (G high)
Write pulse width (G low)
15
15
-
-
ns
ns
tWLEH
tWLWH
tWLEH
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
Data valid to end of write
Data hold time
Write low to data Hi-Z 3
Write high to output active 3
Write recovery time
10
0
-
-
ns
ns
ns
ns
ns
0
12
-
3
12
-
Notes:
1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must
remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being
asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
2. All write cycle timings are referenced from the last valid address to the first transition address.
3. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given
voltage or temperate, tWLQZ(max) < tWHQX(min)
Figure 8 – Write Cycle Timing 1 ꢀW Controlledꢁ
t
AVAV
A (ADDRESS)
t
t
AVWH
WHAX
E (CHIP ENABLE)
t
t
WLEH
WLWH
W (WRITE ENABLE)
t
AVWL
UB, LB (BYTE ENABLED)
D (DATA IN)
t
t
WHDX
DVWH
DATA VALID
t
WLQZ
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MR1A16A
Table 10 – Write Cycle Timing 2 ꢀE Controlledꢁ
Parameter 1
Write cycle time 2
Symbol
tAVAV
tAVEL
Min
35
0
Max
Unit
ns
-
-
-
-
Address set-up time
ns
tAVEH
Address valid to end of write (G high)
Address valid to end of write (G low)
18
20
ns
tAVEH
ns
tELEH
15
15
-
-
ns
ns
Enable to end of write (G high)
Enable to end of write (G low) 3
tELWH
tELEH
tELWH
tDVEH
tEHDX
tEHAX
Data valid to end of write
Data hold time
10
0
-
-
-
ns
ns
ns
Write recovery time
Notes:
12
1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must
remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being
asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
2. All write cycle timings are referenced from the last valid address to the first transition address.
3. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the
same time or before W goes high, the output will remain in a high-impedance state.
Figure 9 – Write Cycle Timing 2 ꢀE Controlledꢁ
tAVAV
A (ADDRESS)
tEHAX
tAVEH
tELEH
E (CHIP ENABLE)
tAVEL
tELWH
W (WRITE ENABLE)
UB, LB (BYTE ENABLE)
D (DATA IN)
tEHDX
tDVEH
Data Valid
Hi-Z
Q (DATA OUT)
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MR1A16A
Table 11 – Write Cycle Timing 3 ꢀLB / UB Controlledꢁ
Parameter 1
Symbol
tAVAV
tAVBL
Min
35
0
Max
Unit
ns
Write cycle time 2
-
-
-
-
Address set-up time
ns
Address valid to end of write (G high)
Address valid to end of write (G low)
tAVBH
tAVBH
18
20
ns
ns
tBLEH
15
15
-
-
ns
ns
Write pulse width (G high)
Write pulse width (G low)
tBLWH
tBLEH
tBLWH
Data valid to end of write
Data hold time
tDVBH
tBHDX
tBHAX
10
0
-
-
-
ns
ns
ns
Write recovery time
Notes:
12
1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W, E or LB/UB has been brought high, the signal must
remain in steady-state high for a minimum of 2 ns. If both byte control signals are asserted, the two signals must have no
more than 2 ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in
a subsequent cycle is the same as the minimum cycle time allowed for the device.
2. All write cycle timings are referenced from the last valid address to the first transition address.
Figure 10 – Write Cycle Timing 3 ꢀLB / UB Controlledꢁ
t
AVAV
A (ADDRESS)
t
t
AVEH
BHAX
E (CHIP ENABLE)
W (WRITE ENABLE)
t
t
t
AVBL
BLEH
BLWH
UB, LB (BYTE ENABLED)
D (DATA IN)
t
t
BHDX
DVBH
Data Valid
Hi -Z
Hi -Z
Q (DATA OUT)
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MR1A16A
ORDERING INFORMATION
Table 12 – Ordering Part Number System for Parallel I/O MRAM
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MR1A16A
Table 13 – MR1A16A Ordering Part Numbers
Temp Grade
Temp
Package
Shipping
Tray
Ordering Part Number
MR1A16AYS35
44-TSOP2
Tape and Reel
Tray
MR1A16AYS35R
Commercial
0 to +70 °C
MR1A16AMA35
48-BGA
Tape and Reel
Tray
MR1A16AMA35R
MR1A16ACYS35
MR1A16ACYS35R
MR1A16ACMA35
MR1A16ACMA35R
MR1A16AVYS35
MR1A16AVYS35R
MR1A16AVMA35
MR1A16AVMA35R
MR1A16AMYS35
44-TSOP2
Tape and Reel
Tray
Industrial
Extended
-40 to +85 °C
48-BGA
44-TSOP2
48-BGA
Tape and Reel
Tray
Tape and Reel
Tray
-40 to +105 °C
-40 to +125 °C
Tape and Reel
Tray
Automotive AEC-
Q100 Grade 1
44-TSOP2
Tape and Reel
MR1A16AMYS35R
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PACKAGE OUTLINE DRAWINGS
Figure 11 – 44-TSOP2 Package Outline
44 PLACES
Print Version Not To Scale
1. Dimensions and tolerances per ASME Y14.5M - 1994.
2. Dimensions in Millimeters.
3. Dimensions do not include mold protrusion.
4. Dimension does not include DAM bar protrusions.
DAM Bar protrusion shall not cause the lead width to exceed 0.58.
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Figure 12 – 48-FBGA Packge Outline
Notes:
1.
2.
Dimensions in Millimeters.
Dimensions and tolerances per ASME Y14.5M
- 1994.
3.
4.
5.
Maximum solder ball diameter measured paral-
lel to DATUM A
DATUM A, the seating plane is determined by
the spherical crowns of the solder balls.
Parallelism measurement shall exclude any ef-
fect of mark on top surface of package.
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REVISION HISTORY
Revision
Date
Description of Change
1.0
October 1, 2019 Initial data sheet release
1.1
March 10, 2020 Updated Table 12 to correct temperature designator
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www.everspin.com
Information in this document is provided solely to enable system and
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are no express or implied licenses granted hereunder to design or
fabricate any integrated circuit or circuits based on the information
in this document. Everspin Technologies reserves the right to make
changes without further notice to any products herein. Everspin makes
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products for any particular purpose, nor does Everspin Technologies as-
sume any liability arising out of the application or use of any product or
circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical”parameters,
which may be provided in Everspin Technologies data sheets and/
or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters including
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spin Technologies was negligent regarding the design or manufacture
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Technologies, Inc. All other product or service names are the property
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of their respective owners.
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