XR16C850CP_技术文档

XR16C850

UART with 128-byte FIFO’s

FIFO Counters and Half-duplex Control

June 1999-1

GENERAL DESCRIPTION

PLCC Package

The XR16C850^*1(850) is a universal asynchronous

receiver and transmitter (UART) and is pin compatible

with the ST16C550,ST16C650A, and TI’s TL16C750

UART. The 850 is an enhanced UART with 128 byte

FIFOs, automatichardware/softwareflowcontrol, and

data rates up to 1.5Mbps. It includes transmit/receive

FIFO counters to increase data loading and unloading

throughput.Onboardstatusregistersprovideerrorindi-

cations and operational status. Modem interface con-

trol is included and can be optionally configured to

operatewiththeInfrared(IrDA)encoder/decoder.Inter-

nal loopback allows onboard diagnostics. The 850 is

available in 40-pin PDIP, 44-pin PLCC, 48-pin TQFP,

and 52-pin QFP packages. The 44, 48, and 52 pin

versions provide both the standard (STD) mode or PC

mode.TheSTDmodeiscompatiblewiththeST16C450,

ST16C550, ST16C650A and TL16C750 while the PC

mode supports standard PC COM port connections.

7

39

38

37

36

35

34

33

32

31

30

29

D5

D6

RESET

-OP1

-DTR

-RTS

-OP2

N.C.

INT

8

9

D7

10

11

12

13

14

15

16

17

RCLK

RX

XR16C850CJ

"STD" MODE

CONNECTION

N.C.

TX

CS0

-RXRDY

A0

CS1

-CS2

-BAUDOUT

A1

A2

The 40 PDIP pin package does not offer the PC mode.

FEATURES

• PintopincompatibletoST16C550,ST16C650Aand

TL16C750

7

39

38

37

36

35

34

33

32

31

30

29

D5

D6

RESET

-OP1

-DTR

-RTS

S3

8

• Transmit/receiveFIFOcounters

• 128bytesofTransmit/ReceiveFIFO

• RS-485halfduplexdirectioncontrol

• Automaticsoftware/hardwareflowcontrol

• Programmable, selectable transmit/receive trigger

levels

• Infraredtransmitterandreceiverencoder/decoder

• Up to 1.5Mbps data rate

• Sleepmode(100µAstandby)

• Small 7x7mm TQFP

9

D7

10

11

12

13

14

15

16

17

S2

RX

XR16C850CJ

"PC" MODE

CONNECTION

A4

GND

IRQA

IRQB

A0

TX

A5

A6

A7

A1

-LPT1

A2

• +5 or 3.3 Volts operation

• Windows²driversavailable

ORDERING INFORMATION

Part Number Pins Package Operating Temperature

XR16C850CP 40

XR16C850CJ 44

XR16C850CM 48

XR16C850CQ 52

PDIP

PLCC

TQFP

QFP

0° C to + 70° C

XR16C850IP 40

XR16C850IJ 44

XR16C850IM 48

XR16C850IQ 52

PDIP

PLCC

TQFP

QFP

-40° C to + 85° C

Note*1:CoveredbyU.S.patent#5,649,122andpatentpending.

Note*2:WindowsisatrademarkofMicrosoftCorporation.

Rev. 1.20

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017

XR16C850

SEL

1

2

36

35

34

33

32

31

30

29

28

27

26

25

D11

RESET

-OP1/RS485

-DTR

D5

D6

3

D7

S2 / RCLK

A4

4

-RTS

5

V C C

-RI

D 0

D 1

1

4 0

3 9

3 8

3 7

3 6

3 5

3 4

3 3

3 2

3 1

3 0

2 9

2 8

2 7

2 6

2 5

2 4

-OP2 / S3

INT / IRQA

-RXRDY / IRQB

A0

6

XR16C850CM

7

2

RX

TX

8

-CD

3

D 2

A5 / CS0

A6 / CS1

A7 / -CS2

-LPT1 / -BAUDOUT

9

-DSR

-CTS

R E S E T

- O P 1

-DTR

-RTS

- O P 2

INT

4

D 3

A1

10

11

12

D 4

5

A2

D 5

6

BUS 8/16

D 6

7

8

D 7

9

R C L K

R X

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

TX

-RXRDY

A 0

C S 0

C S 1

A 1

-CS2

- B A U D O U T

X T A L 1

X T A L 2

- I O W

I O W

G N D

A 2

-AS

D11

1

39

38

37

36

35

34

33

32

31

30

29

28

27

SEL

-TXRDY

2

3

RESET

-OP1/RS485

-DTR

D5

D6

2 3 -DDIS

IOR

2 2

2 1

D7

4

5

-RTS

-IOR

S2

/

RCLK

A4

6

-OP2

INT

/

S3

XR16C850CQ

RX

7

/

IRQA

TX

8

-RXRDY*/ IRQB/DRQ

9

A0

A5

A6

/

CS0

CS1

10

11

12

13

A1

A7

/

-CS2

A2

-LPT1

/

-BAUDOUT

TC

BUS 8/16

CLK 8/16

Figure 1. PACKAGE DESCRIPTION, 16C850

Rev. 1.20

2

XR16C850

Transmit

FIFO

Registers

Transmit

Shift

Register

TX

D0-D7

-IOR,IOR

-IOW,IOW

RESET

Flow

Control

Logic

Ir

Encoder

A0-A2

-AS

CS0,CS1

Receive

FIFO

Registers

Receive

Shift

Register

RX

-CS2

-DDIS

Flow

Control

Logic

Ir

Decoder

INT

-RXRDY

-TXRDY

-DTR,-RTS

-OP1/RS485

-OP2

Modem

Control

Logic

-CTS

-RI

XTAL1

RCLK

-CD

-DSR

XTAL2

-BAUDOUT

Figure 2. BLOCK DIAGRAM (STANDARD MODE)

Rev. 1.20

3

XR16C850

Transmit

FIFO

Registers

Transmit

Shift

Register

TX

D0-D7

-IOR

-IOW

Flow

Control

Logic

Ir

Encoder

Receive

FIFO

Registers

Receive

Shift

Register

A0-A9

-AEN

S1, S2,S3

RX

Flow

Control

Logic

Ir

Decoder

-LPT1

-LPT2

-DTR,-RTS

Modem

Control

Logic

-CTS

-RI

-CD

-DSR

Clock

&

Baud Rate

Generator

IRQA

IRQB

IRQC

GND

Figure 3. BLOCK DIAGRAM (PC MODE)

Rev. 1.20

4

XR16C850

SYMBOL DESCRIPTION

Symbol

Signal

type

PinDescription

40

44

48

52

A0

28

31

28

31

I

Address-0 Select Bit - Internal registers address

selection in PC and STD modes.

A1

27

26

22

30

29

25

27

26

20

30

29

22

Address-1 Select Bit Internal registers address

selection in PC and STD modes

A2

Address-2 Select Bit Internal registers address

selection in PC and STD modes

A3 / IOR

Address-3 Select Bit or Input/Output Read (dual

function) - When the PC mode is selected, this pin

is used as 4th address line to decode the COM1-4

andLPTports.DuringSTDmodeoperationthispin

is used as Read strobe. Its function is the same as

-IOR (see -IOR), except it is active high. Either an

active -IOR or IOR is required to transfer data from

850 to CPU during a read operation. Connect this

pin to GND when –IOR is used.

A4

-

12

14

6

9

6

9

I

Address-4 Select Bit (internal pull-up) - When the

PCmodeisselected,thispinisusedas5thaddress

line to decode the COM1-4 and LPT ports. This pin

has no function in the STD mode.

A5 / CS0

12

Address-5SelectBitorChipSelect-0(dualfunction)

-WhenthePCmodeisselected, thispinisusedas

6th address line to decode the COM1-4 and LPT

ports. During STD mode a logical 1 on this pin

providesthechipselect0function.Connectthispin

to VCC when CS1 or –CS2 is used.

A6 / CS1

13

14

15

16

10

11

10

I

Address-6SelectBitorChipSelect-1(dualfunction)

-WhenthePCmodeisselected, thispinisusedas

7th address line to decode the COM1-4 and LPT

ports. During STD mode a logical 1 on this pin

providesthechipselect1function.Connectthispin

to VCC when CS0 or –CS2 is used.

A7 / -CS2

7

Address-7 Select Bit or Chip Select -2 (dual func-

tion) - When the PC mode is selected, this pin is

usedas8thaddresslinetodecodetheCOM1-4and

LPT ports. During STD mode a logical 1 on this pin

providesthechipselect2function.Connectthispin

Rev. 1.20

5

XR16C850

SYMBOL DESCRIPTION

Symbol

Signal

type

PinDescription

40

44

48

52

to GND when CS0 or CS1 is used.

A8 / IOW

19

21

17

18

I

Address-8 Select Bit or Input/Output Write (dual

function) - When the PC mode is selected, this pin

is used as 9th address line to decode the COM1-4

andLPTports.DuringSTDmode,alogic1transition

creates a write strobe. Its function is the same as -

IOW (see -IOW), but it acts as an active high input

signal. Either -IOW or IOW is required to transfer

data from the CPU to 850 during a write operation.

Connect this pin to GND when –IOW is used.

A9

-

1

37

24

40

26

I

Address-9 Select Bit (internal pull-up) - When the

PC mode is selected, this pin is used as 10th

addresslinetodecodetheCOM1-4andLPTports.

This pin has no function in the STD mode.

-AEN / -AS

25

28

AddressEnableorAddressStrobe(dualfunction)-

.DuringPCmodeoperation,validCOM1-4portsare

decodedwhen-AENtransitionstoalogic0.During

theSTDmodealogic0transitionon-ASlatchesthe

stateofthechipselectsandtheregisterselectbits,

A0-A2. This input is used when address and chip

selects are not stable for the duration of a read or

writeoperation,i.e.,amicroprocessorthatneedsto

demultiplex the address and data bits. If not re-

quired, the -AS input can be permanently tied to

GND (it is edge triggered).

-BAUDOUT

D0-D7

(SeeLPT-1)

1-8

2-9

43-47 47-51

2-4

I/O

Data Bus (Bi-directional) - These pins are the eight

bit, threestatedatabusfortransferringinformation

to or from the controlling CPU. D0 is the least

significant bit and the first data bit in a transmit or

receive serial data stream.

D10,D11,

D12

-

48,1

22

52,1

24

O

High order data bus. When 16 bit data bus (BUS8/

16 = logic zero) is selected, received data errors

(parity, framing, break) can be read along with its

data byte on these pins. D10 is parity error bit, D11

Rev. 1.20

6

XR16C850

SYMBOL DESCRIPTION

Symbol

Signal

type

PinDescription

40

44

48

52

is framing error bit and D12 is the break bit.

BUS8/16

-

25

28

I

8 or 16 Bit Bus select (internal pull-up). For normal

8bitdatabusoperationthispinshouldbeconnected

toVCC. ConnectthispintoGNDfor16bitdatabus

operationwhereRXdataerrors(parity,framingand

break) are presented on the data bus as D10, D11

and D12 along with the data byte.

CLK8/16

-

27

I

Transmit / Receive data sampling clock rate (inter-

nalpull-up).Fornormaloperationthispinshouldbe

connected to VCC for 16X sampling clock (stan-

dard).Connect toGNDfor8Xsamplingtodoublethe

data rates.

DRQ

-

32

46

O

I

ReceiveDMARequest.AReceivereadyrequestis

generatedbybringingaRxDRQlinetoahighlevel.

DRQ line is held high until the corresponding DMA

acknowledge (-DACK) line goes low.

-DACK

DMAAcknowledgeBit(internalpull-up).DMAcycle

willstartprocessingwhenCPU/Hostsetsthisinput

to low. Connect this pin to VCC when not used.

-DDIS

GND

INT

(SeeLPT-2)

20

21

18

22

24

20

18

19

16

19

21

17

Pwr

SignalandPowerGround.

(SeeIRQA)

-IOR

I

Input/Output Read (active low strobe). A logic 0 on

thispintransfersthecontentsofthe850databusto

theCPU.ConnectthispintoVCCwhenIORisused.

-IOW

Input/OutputWrite(activelowstrobe)-Alogic0on

this pin transfers the contents of the CPU data bus

to the addressed internal register. Connect this pin

to VCC when IOW is used.

IRQA/INT

30

33

30

33

O

InterruptRequest“A”orInterrupt(threestate,open

source,activehigh)-DuringPCmodeofoperation,

this pin functions as IRQA. IRQA is enabled when

Rev. 1.20

7

XR16C850

SYMBOL DESCRIPTION

Symbol

Signal

type

PinDescription

40

44

48

52

MCR bit-3 is set to a logic 1, interrupts are enabled

in the interrupt enable register (IER), and when an

interrupt condition exists. Interrupt conditions in-

clude:receivererrors,availablereceiverbufferdata,

transmitbufferempty,orwhenamodemstatusflag

is detected. During STD mode operation the three

statemodeisdisabledandthispinfunctionsasINT

(InterruptRequest).

IRQB/-RXRDY

29

24

15

32

27

17

29

23

12

32

25

12

O

InterruptRequest“B”orReceiveReady(threestate,

dual function) -. During PC mode operation, a logic

1 indicates an interrupt IRQB (see further descrip-

tion under the IRQA). During the STD mode a logic

0 indicates receive data ready status, i.e. the RHR

is full or the FIFO has one or more RX characters

available for unloading. This pin goes to a logic 0

when the FIFO/RHR is full or when there are more

characters available in either the FIFO or RHR.

IRQC/-TXRDY

Interrupt Request “C” or Transmit Ready (three

state, dualfunction)-DuringPCmodeoperation, a

logic 1 on this pin indicates an interrupt IRQC (see

furtherdescriptionundertheIRQA).DuringtheSTD

mode buffer ready status is indicated by a logic 0,

i.e., at least one location is empty and available in

the FIFO or THR. This pin goes to a logic 1 when

there are no more empty locations in the FIFO or

THR.

-LPT-1/

-BAUDOUT

Baud Rate Generator Output or Line Printer Port-1

Decode Logic Output. (dual function, active low) -

When the PC mode is selected, the baud rate

generatorclockoutputisinternallyconnectedtothe

RCLK input. This pin then functions as the LPT-1

printerportdecodelogicoutput,seetable2.During

STDmodeoperation,thispinprovidesthe16Xclock

oftheselecteddataratefromthebaudrategenera-

tor. The RCLK pin must be connected externally to

-BAUDOUT when the receiver is operating at the

same data rate.

-LPT2/-DDIS

23

26

22

24

O

Drive Disable or Line Printer Port-2 Decode Logic

Output (dual function, active low) - When the PC

Rev. 1.20

8

XR16C850

SYMBOL DESCRIPTION

Symbol

Signal

type

PinDescription

40

44

48

52

mode is selected, this pin functions as the LPT-2

printerportdecodelogicoutput,seetable2.During

the STD mode this pin goes to a logic 0 when the

external CPU is reading data from the 850. This

signalcanbeusedtodisableexternaltransceivers

or other logic functions. Also, this pin may be D12

signal when BUS16 is selected in 48 and 52 pin

packages.

-OP1/RS485

34

38

34

37

O

Output-1(UserDefined)orRS-485directioncontrol

signal.Generalpurposeoutputduringnormalopera-

tion-Seebit-2ofmodemcontrolregister(MCRbit-

2). RS-485 direction control can be selected when

FCTRBit-3issetto“1”. Duringdatatransmitcycle,

-OP1/RS485 pin is low.

-OP2

(SeeS3)

(SeeS2)

RCLK

RESET

35

39

35

38

I

Reset. (active high) - A logic 1 on this pin will reset

the internal registers and all the outputs. During

reset,theUARTtransmitteroutputandthereceiver

inputaredisabled, thedatabusisstillcontrolledby

CS0,CS1,-CS2and-IOR.(SeeXR16C850External

Reset Conditions for initialization details.)

-RXRDY

S1

(SeeIRQB)

-

23

10

21

5

23

5

I

Port Select-1 (internal pull-up) - When PC mode is

selected, S1isusedinconjunctionwithS2, S3and

A3-A9toselectoneofthePCCOMportaddresses

(see Table 2 Internal Address Decode Function)

This pin has no function in the STD mode.

S2 / RCLK

9

PortSelect-2orReceiveClockInput(dualfunction

input with internal pull-up) - When PC mode is

selected, the RCLK input is connected internally to

-BAUDOUT and S2 is used in conjunction with S1,

S3 and A3-A9 to select one of the PC COM port

addresses. During STD mode operation, this pin is

used as external 16X clock input to the receiver

section, normally it’s connected to -BAUDOUT.

Rev. 1.20

9

XR16C850

SYMBOL DESCRIPTION

Symbol

Signal

type

PinDescription

40

44

48

52

S3 / -OP2

31

35

31

34

I/O

Select-3 or User Defined Output-2 (dual function

with internal pull-up) - When PC mode is selected,

S3 is used in conjunction with S1, S2 and A3-A9 to

select one of the PC COM port addresses. In the

STD mode this pin provides the user a general

purpose output. See bit-3 modem control register

(MCRbit-3).

SEL

TC

-

34

36

39

13

I

Select Mode (internal pull-up) - The PC mode is

selected by a logic 0 (GND) on this pin and STD

modeisselectedwhenthispinisalogic1(leftopen

ortiedtoVCC).Thispinisnotavailableonthe40pin

PDIP packages which operate in the STD mode

only.

-

Terminal Count Bit (internal pull-up). A high pulse

indicates terminal count for any DMA channel is

reached. Connect this pin to GND when not used.

-TXRDY

VCC

(SeeIRQC)

40

16

44

18

42

14

45

15

Pwr

I

PowerSupplyInput.

XTAL1

Crystal or External Clock Input - Functions as a

crystal input or as an external clock input. A crystal

can be connected between this pin and XTAL2 to

form an internal oscillator circuit. An external 1 MΩ

resistorisrequiredbetweentheXTAL1andXTAL2

pins (see figure 9). Alternatively, an external clock

canbeconnectedtothispintoprovidecustomdata

rates(Programming BaudRateGeneratorsection).

XTAL2

-CD

17

38

36

19

42

40

15

40

38

16

43

41

O

I

Output of the Crystal Oscillator or Buffered Clock -

(See also XTAL1). Crystal oscillator output or buff-

ered clock output.

Carrier Detect (active low) - A logic 0 on this pin

indicates that a carrier has been detected by the

modem.

-CTS

I

CleartoSend(activelow)-Alogic0onthe-CTSpin

indicates the modem or data set is ready to accept

transmitdatafromthe850. Statuscanbetestedby

Rev. 1.20

10

XR16C850

SYMBOL DESCRIPTION

Symbol

Signal

type

PinDescription

40

44

48

52

readingMSRbit-4.Thispinonlyaffectsthetransmit

and receive operations when Auto CTS function is

enabled via the Enhanced Feature Register (EFR)

bit-7,forhardwareflowcontroloperation.

-DSR

37

33

41

37

39

33

42

36

I

Data Set Ready (active low) - A logic 0 on this pin

indicatesthemodemordatasetispowered-onand

is ready for data exchange with the UART. This pin

has no effect on the UART’s transmit or receive

operation.

-DTR

O

DataTerminalReady(activelow)-Alogic0onthis

pinindicatesthatthe850ispowered-onandready.

This pin can be controlled via the modem control

register. Writing a logic 1 to MCR bit-0 will set the -

DTRoutputtologic0,enablingthemodem.Thispin

will be a logic 1 after writing a logic 0 to MCR bit-0,

orafterareset.ThispinhasnoeffectontheUART’s

transmitorreceiveoperation.

-RI

39

32

43

36

41

32

44

35

I

Ring Indicator (active low) - A logic 0 on this pin

indicates the modem has received a ringing signal

from the telephone line. A logic 1 transition on this

input pin will generate an interrupt.

-RTS

O

RequesttoSend(activelow)-Alogic0onthe-RTS

pin indicates the transmitter has data ready and

waiting to send. Writing a logic 1 in the modem

controlregister(MCRbit-1)willsetthispintoalogic

0 indicating data is available. After a reset this pin

will be set to a logic 1. This pin only affects the

transmit and receive operations when Auto RTS

functionisenabledviatheEnhancedFeatureReg-

ister(EFR)bit-6,forhardwareflowcontroloperation.

RX/IRRX

10

11

7

I

Receive Data - This pin provides the serial receive

datainputtothe850.Twouserselectableinterface

options are available. The first option supports the

standard serial interface. The second option pro-

videsanInfrareddecoderinterface,seefigures2and

3. When using the standard modem interface, the

RX input must be a logic 1 during idle (no data

Rev. 1.20

11

XR16C850

SYMBOL DESCRIPTION

Symbol

Signal

type

PinDescription

40

44

48

52

or“mark”condition).Theinactivestate(nodata)for

theInfrareddecoderinterfaceisalogic0. MCRbit-

6selectsthestandardmodemorinfraredinterface.

During the local loopback mode, the RX pin is

disconnectedandTXdataisinternallyconnectedto

the RX input, see figure 12.

TX/IRTX

11

13

8

O

TransmitData-Thispinprovidestheserialtransmit

data from the 850. Two user selectable interface

optionsareavailable.Thefirstuseroptionsupports

a standard modem interface. The second option

providesanInfraredencoderinterface,seefigures2

and3.Whenusingthestandardserial interface,the

TXsignalwillbealogic1duringreset,idle(nodata),

or when the transmitter is disabled. The inactive

state(nodata)fortheInfraredencoderinterfaceisa

logic 0. MCR bit-6 selects the standard serial or

infraredinterface. Duringthelocalloopbackmode,

theTXpinisdisconnectedandTXdataisinternally

connected to the RX input, see figure 12.

CLKSEL

-

13

14

I

ClockSelectBit(internalpull-up).-The1Xor4Xpre-

scaleableclockisselectedbythispin.The1Xclock

isselectedwhenCLKSELisalogic1(connectedto

VCC)orthe4XisselectedwhenCLKSELisalogic

0 (connected to GND). MCR bit-7 can override the

state of this pin following reset or initialization (see

MCRbit-7).Thispinisnotavailableon40and44pin

packages which provide MCR bit-7 selection only.

-DMA

-

20

I

DMA mode enable (internal pull-up). DMA mode is

enabled when this pin is connected to GND. TC, -

DACK, DRQ functions are activated when DMA

mode is selected. TX and RX DMA mode can then

be selected by register EMSR bit 2. Connect this

pin to VCC when DMA mode is not used.

Rev. 1.20

12

XR16C850

GENERALDESCRIPTION

TheXR16C850providesserialasynchronousreceive

data synchronization, parallel-to-serial and serial-to-

parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for

convertingtheserialdatastreamintoparalleldatathat

is required with digital data systems. Synchronization

for the serial data stream is accomplished by adding

start and stops bits to the transmit data to form a data

character (character orientated protocol). Data integ-

rity is insured by attaching a parity bit to the data

character. The parity bit is checked by the receiver for

any transmission bit errors. The electronic circuitry to

provide all these functions is fairly complex especially

whenmanufacturedonasingleintegratedsiliconchip.

The XR16C850 represents such an integration with

greatly enhanced features. The 850 is fabricated with

an advanced CMOS process.

The850providesaRS-485half-duplexdirectioncontrol

signal, pin –OP1/RS485, to select the external trans-

ceiver direction. It automatically changes the state of

theoutputpinafterthelaststop-bitofthelastcharacter

hasbeenshiftedoutforreceivestate.Afterward,upon

loadingaTXdatabyteitchangesstateoftheoutputpin

back for transmit state. The RS-485 direction control

pinisnotactivatedafterreset.Toactivatethedirection

control function, user has to set EFR Bit-4, and FCTR

Bit-3 to “1”. This pin is normally high for receive state,

low for transmit state.

Two data bus interfaces are available to the user. The

PC mode allows direct interconnect to the PC ISA bus

while the STD Mode operates similar to the standard

CPU interface available on the 16C450/550/650A.

When the PC mode is selected, the external logic

circuitryrequiredforPCCOMportaddressdecodeand

chipselectiseliminated.Thesefunctionsareprovided

internally in the 850.

The 850 is an upward solution that provides 128 bytes

of transmit and receive FIFO memory, instead of 32

bytesprovidedinthe16C650A,16bytesinthe16C550,

ornoneinthe16C450.The850isdesignedtoworkwith

high speed modems and shared network environ-

ments, that require fast data processing time. In-

creasedperformanceisrealizedinthe850bythelarger

transmit and receive FIFOs. This allows the external

processor to handle more networking tasks within a

giventime. Forexample, theST16C550witha16byte

FIFO,unloads16bytesofreceivedatain1.53ms(This

example uses a character length of 11 bits, including

start/stop bits at 115.2Kbps). This means the external

CPU will have to service the receive FIFO at 1.53 ms

intervals. However with the 128 byte FIFO in the 850,

thedatabufferwillnotrequireunloading/loadingfor12.2

ms. This increases the service interval giving the

externalCPUadditionaltimeforotherapplicationsand

reducing the overall UART interrupt servicing time. In

addition,the4selectablelevelsofFIFOtriggerinterrupt

and automatic hardware/software flow control is

uniquelyprovidedformaximumdatathroughputperfor-

mance especially when operating in a multi-channel

environment. The combination of the above greatly

reduces the bandwidth requirement of the external

controllingCPU,increasesperformance,andreduces

powerconsumption.

The 850 is capable of operation to 1.5Mbps with a 24

MHz crystal or external clock input. With a crystal of

14.7464 MHz and through a software option, the user

can select data rates up to 460.8Kbps or 921.6Kbps.

The rich feature set of the 850 is available through

internal registers. Automatic hardware/software flow

control, selectable transmit and receive FIFO trigger

levels, selectable TX and RX baud rates, infrared en-

coder/decoder interface, modem interface controls,

andasleepmodeareallstandardfeatures.Inaddition

the 44/48/52 pin packages offer the PC Mode, two

additionalthreestateinterruptlinesandoneselectable

opensourceinterruptoutput.Theopensourceinterrupt

scheme allows multiple interrupts to be combined in a

“WIRE-OR” operation, thus reducing the number of

interrupt lines in larger systems. Following a power on

reset or an external reset, the 850 is software compat-

ible with previous generation of UARTs, 16C450,

16C550and16C650A.

Rev. 1.20

13

XR16C850

FUNCTIONALDESCRIPTIONS

InterfaceOptions

Standard16550ModeInterface

The850providesapincompatibleinterfaceforemula-

tion of the 16C550 when in the STD mode. The STD

mode is selected by making the SEL pin a logic 1

(VCC). When the SEL pin is set to a logic 1, the 850

interface is the same as Industry Standard 16C550.

Figure4showsatypicalconnectiontothePCISAbus.

VCC

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

A0

A1

A2

RCLK

-BAUDOUT

IOR*

-IOR

IOW*

-IOW

A3

A4

J1

CS0

CS1

SEL

3F8

2F8

3E8

2E8

1

3

5

7

2

4

6

8

A5

A6

A7

A8

A9

-CS2

HDR2X4

AEN*

-OP2

INT

IOW

IOR

-AS

J2

1

3

2

4

3

2

IRQ3

IRQ4

RESET

U2A

74LS125A

HDR2X2

RESET

Figure 4, STANDARD MODE INTERFACE

Rev. 1.20

14

XR16C850

PC Mode Interface (available on 44/48/52 pin ver-

sionsonly)

function as three state outputs. MCR bit-3 must be set

toalogic1toactivatetheseinterrupts.Themappingfor

the COM port 1-4 and their associated interrupt selec-

tions,IRQxarelistedinTable2,below.Figure5shows

a typical connection to the PC ISA bus.

ThePCmodeisselectedbymakingtheSELpinalogic

0 (GND). When the PC mode is selected, the 850

eliminates the external address decode logic circuitry

that is required. The PC mode is accomplished by

decoding the PC ISA bus address bits, A3 through A9

inside the 850. These addresses select the standard

PC COM ports: COM-1 (3F8-3FF Hex), COM-2 (2F8-

2FF Hex), COM-3 (3E8-3EF Hex), and COM-4 (2E8-

2EF Hex). Three inputs (S1-S3) are generally exter-

nallyjumpered(logic1orlogic0)forselectingtheoper

ating port. The selection bits are also associated with

agivenPCinterrupt.InterruptsIRQA,IRQB,andIRQC

In addition to the COM port addresses, the 850 de-

codestwoadditionalprinteraddresses.Theseaddress

decodesselectLPT-1(printerport-1,378-37FHex),or

LPT-2 (printer port-2, 278-27F Hex). These ports are

intended to be compatible with PC or PC compatible

computerprinterports.

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

-AEN

AEN*

J1

1

3

5

2

4

6

S1

S2

S3

SEL

HDR2X3

IOR*

-IOR

IOW*

-IOW

IRQ4

IRQ3

IRQn

INTA

INTB

INTC

RESET

Figure 5. PC MODE INTERFACE

Rev. 1.20

15

XR16C850

SEL S3 S2 S1

A3-A9

COMPort Selected IRQ *2

0

1

0

1

0

1

3F8-3FF

2F8-2FF

3E8-3EF

2E8-2EF

COM-1

COM-2

COM-3

COM-4

IRQB(IRQ4)

IRQC(IRQ3)

IRQB(IRQ4)

IRQC(IRQ3)

0

1

0

1

0

1

0

1

3F8-3FF

2F8-2FF

3E8-3EF

2E8-2EF

COM-1

COM-2

COM-3

COM-4

IRQA(IRQn)

0

-

278-27F

378-37F

LPT-2

LPT-1

N/A

Table 2. PC MODE INTERNAL ADDRESS DECODE FUNCTIONS

Note *2: All interrupt outputs are inactive (three state mode) except when the selected address range is valid.

Rev. 1.20

16

XR16C850

InternalRegisters

status and control registers (MCR/MSR), program-

mable data rate (clock) control registers (DLL/DLM),

and a user assessable scratchpad register (SPR).

Beyond the general 16C550 features and capabilities,

the 850 offers an enhanced feature register set called

EFR, Xon/Xoff 1-2, TRG, FCTR, and EMSR. Register

functions are more fully described in the following

paragraphs.

The850provides15internalregistersformonitoringand

control. These registers are shown in Table 3 below.

Twelveregistersaresimilartothosealreadyavailablein

thestandard16C550.Theseregistersfunctionasdata

holdingregisters(THR/RHR),interruptstatusandcon-

trol registers (IER/ISR), a FIFO control register (FCR),

line status and control registers, (LCR/LSR), modem

A2

A1

A0

READMODE

WRITEMODE

General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR):

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ReceiveHoldingRegister

InterruptStatusRegister

TransmitHoldingRegister

InterruptEnableRegister

FIFOControlRegister

LineControlRegister

ModemControlRegister

Line Status Register

Modem Status Register

ScratchpadRegister

Baud Rate Register Set (DLL/DLM): Note *3

0

1

LSB of Divisor Latch

MSB of Divisor Latch

LSB of Divisor Latch

MSB of Divisor Latch

Enhanced Register Set (Xon/off 1-2, TRG, FCTR, EFR, EMSR): Note *4

0

1

0

1

0

1

0

1

0

1

0

1

FIFOTriggerRegister

FIFOtriggercounter

FeatureControlRegister

EnhancedFeatureRegister

Xon-1Word

Xon-2Word

Xoff-1Word

EnhancedFeatureRegister

Xon-1Word

Xon-2Word

Xoff-1Word

Xoff-2Word

Enhanced Mode Select Register

Table 3. INTERNAL REGISTERS

Note *3: These registers are accessible only when LCR bit-7 is set to a logic 1.

Note *4: Enhanced Feature Registers are accessible only when the LCR is set to “BF” hex.

Rev. 1.20

17

XR16C850

FIFO Operation

Hardware Flow Control

The 128 byte transmit and receive data FIFO’s are

enabledbytheFIFOControlRegister(FCR)bit-0.With

16C550 devices, the user can only set the receive

trigger level but not the transmit trigger level. The 850

providesindependenttriggerlevelsforbothreceiverand

transmitter. To remain compatible with 16C550, the

transmit interrupt trigger level is set to 16 following a

reset. It should be noted that the user can set the

transmittriggerlevelsbywritingtotheFCRregister,but

activation will not take place until EFR bit-4 is set to a

logic 1. The receiver FIFO section includes a time-out

function to ensure data is delivered to the CPU. An

interrupt is generated whenever the Receive Holding

Register(RHR)hasnotbeenreadfollowingtheloading

of a character or the receive trigger level has not been

reached.(seehardwareflowcontrolforadescriptionof

this timing).

When automatic hardware flow control is enabled, the

850monitorsthe-CTSpinforaremotebufferoverflow

indication and controls the -RTS pin for local buffer

overflows.Automatichardwareflowcontrolisselected

by setting bits 6 (RTS) and 7 (CTS) of the EFR register

to a logic 1. If -CTS transitions from a logic 0 to a logic

1 indicating a flow control request, ISR bit-5 will be set

to a logic 1 (if enabled via IER bit 6-7), and the 850 will

suspendTXtransmissionsassoonasthestopbitofthe

character in process is shifted out. Transmission is

resumed after the -CTS input returns to a logic 0,

indicating more data may be sent.

The 850 has a new feature that provides flow control

trigger hysteresis while maintains compatibility to

16C650A and 16C550. With the Auto RTS function

enabled, an interrupt is generated when the receive

FIFO reaches the programmed RX trigger level. The -

RTSpinwillnotbeforcedtoalogic1(RTSOff),untilthe

receive FIFO reaches the upper limit of the hysteresis

level. The -RTS pin will return to a logic 0 after the RX

data buffer (FIFO) is unloaded to the lower limit of the

hysteresislevel.Undertheabovedescribedconditions

the 850 will continue to accept data until the receive

FIFOgetsfull. TheAutoRTSfunctionisinitiatedwhen

the –RTS output pin is asserted to logic 0 (RTS On).

Below shows the 650A and 850 hysteresis level of “N”

with respect to Auto RTS flow control levels.

FCTR

Bit-1 and 0

Selection (characters)

Trigger

Level

RTS

Hysteresis

(characters) Activation at

INT

-RTS

De-asserted

(characters)

-RTS

Asserted

(characters)

00

01

10

8

16

24

28

N plus 4

N plus 6

0

8

16

24

16

24

28

N

16

24

28

N

+/-4

+/-6

N minus 4

N minus 6

Rev. 1.20

18

XR16C850

Software Flow Control

When software flow control is enabled, the 850 com-

paresoneortwosequentialreceivedatacharacterswith

the programmed Xon or Xoff-1,2 character value(s). If

receive character(s) (RX) match the programmed val-

ues, the 850 will halt transmission (TX) as soon as the

current character(s) has completed transmission.

Whenamatchoccurs,thereceiveready(ifenabledvia

Xoff IER bit-5) flags will be set and the interrupt output

pin (if receive interrupt is enabled) will be activated.

Following a suspension due to a match of the Xoff

charactersvalues,the850willmonitorthereceivedata

streamforamatchtotheXon-1,2charactervalue(s).If

a match is found, the 850 will resume operation and

clear the flags (ISR bit-4).

The 850 compares each incoming receive character

withXoff-2data.Ifamatchexists,thereceiveddatawill

be transferred to FIFO and ISR bit-4 will be set to

indicate detection of special character (see Figure 9).

Although the Internal Register Table shows each X-

Register with eight bits of character information, the

actualnumberofbitsisdependentontheprogrammed

wordlength.LineControlRegister(LCR)bits0-1defines

the number of character bits, i.e., either 5 bits, 6 bits, 7

bits, or 8 bits. The word length selected by LCR bits 0-

1 also determines the number of bits that will be used

for the special character comparison. Bit-0 in the X-

registers corresponds with the LSB bit for the receive

character.

ResetinitiallysetsthecontentsoftheXon/Xoff8-bitflow

control registers to a logic 0. Following reset the user

can write any Xon/Xoff value desired for software flow

control. Different conditions can be set to detect Xon/

Xoff characters and suspend/resume transmissions.

Whendouble8-bitXon/Xoffcharactersareselected,the

850comparestwoconsecutivereceivecharacterswith

twosoftwareflowcontrol8-bitvalues(Xon1,Xon2,Xoff1,

Xoff2)andcontrolsTXtransmissionsaccordingly. Un-

dertheabovedescribedflowcontrolmechanisms,flow

control characters are not placed (stacked) in the user

accessible RX data buffer or FIFO.

Time-outInterrupts

Threespecialinterruptshavebeenaddedtomonitorthe

hardwareandsoftwareflowcontrol. Theinterruptsare

enabled by IER bits 5-7. Care must be taken when

handling these interrupts. Following a reset the trans-

mitterinterruptisenabled,the850willissueaninterrupt

to indicate that transmit holding register is empty. This

interrupt must be serviced prior to continuing opera-

tions. The LSR register provides the current singular

highestpriorityinterruptonly.ItcouldbenotedthatCTS

and RTS interrupts have lowest interrupt priority. A

conditioncanexistwhereahigherpriorityinterruptmay

maskthelowerpriorityCTS/RTSinterrupt(s).Onlyafter

servicing the higher pending interrupt will the lower

priorityCTS/RTSinterrupt(s)bereflectedinthestatus

register. Servicing the interrupt without investigating

further interrupt conditions can result in data errors.

Intheeventthatthereceivebufferisoverfillingandflow

control needs to be executed, the 850 automatically

sendsanXoffmessage(whenenabled)viatheserialTX

outputtotheremotemodem.The850sendstheXoff-1,2

characters as soon as received data passes the pro-

grammed trigger level. To clear this condition, the 850

will transmit the programmed Xon-1,2 characters as

soon as receive data drops below the programmed

triggerlevel.

Whentwointerruptconditionshavethesamepriority,it

is important to service these interrupts correctly. Re-

ceiveDataReadyandReceiveTimeOuthavethesame

interrupt priority (when enabled by IER bit-0). The

receiverissuesaninterruptafterthenumberofcharac-

tershavereachedtheprogrammedtriggerlevel.Inthis

case the 850 FIFO may hold more characters than the

programmed trigger level. Following the removal of a

data byte, the user should recheck LSR bit-0 for

additionalcharacters.AReceiveTimeOutwillnotoccur

if the receive FIFO is empty. The time out counter is

resetatthecenterofeachstopbitreceivedoreachtime

the receive holding register (RHR) is read. The actual

time out value is T (Time out length in bits) = 4 X P

Special Feature Software Flow Control

Aspecialfeatureisprovidedtodetectan8-bitcharacter

when bit-5 is set in the Enhanced Feature Register

(EFR).Whenthischaracterisdetected,itwillbeplaced

on the user accessible data stack along with normal

incomingRXdata.Thisconditionisselectedinconjunc-

tion with EFR bits 0-3. Note that software flow control

should be turned off when using this special mode by

setting EFR bit 0-3 to a logic 0.

Rev. 1.20

19

XR16C850

(Programmedwordlength)+12.Toconvertthetimeout

valuetoacharactervalue, theuserhastoconsiderthe

complete word length, including data information

length, start bit, parity bit, and the size of stop bit, i.e.,

1X, 1.5X, or 2X bit times.

standardmicroprocessorcrystal(parallelresonant/22-

33pFload)isconnectedexternallybetweentheXTAL1

andXTAL2pins,withanexternal500Kto1MΩresistor

acrossit.Theserial50-120ΩresistoronpinXTAL2may

bedeletedforhighfrequencycrystaloperation.Alterna-

tively,anexternalclockcanbeconnectedtotheXTAL1

pintoclocktheinternalbaudrategeneratorforstandard

or custom rates.

Example-A:Iftheuserprogramsawordlengthof7,with

no parity and one stop bit, the time out will be:

T=4X7(programmedwordlength)+12=40bittimes.

The character time will be equal to 40 / 9 = 4.4

characters,orasshowninthefullyworkedoutexample:

T = [(programmed word length = 7) + (stop bit = 1) +

(start bit = 1) = 9]. 40 (bit times divided by 9) = 4.4

characters.

Thegeneratordividestheinput16Xclockbyanydivisor

from 1 to 2¹⁶-1. The 850 divides the basic crystal or

external clock by 16. Further division of this 16X clock

provides two table rates to support low and high data

rate applications using the same system design. The

two rate tables are selectable through the internal

register, MCR bit-7. Setting MCR bit-7 to a logic 1

providesanadditionaldivideby4whereas,settingMCR

bit-7 to a logic 0 only divides by 1. (See Table 4 and

Figure11).Thefrequencyofthe-BAUDOUToutputpin

is exactly 16X (16 times) of the selected baud rate (-

BAUDOUT=16xBaudRate).CustomizedBaudRates

can be achieved by selecting the proper divisor values

for the MSB and LSB sections of baud rate generator.

Example -B: If the user programs the word length = 7,

with parity and one stop bit, the time out will be:

T=4X7(programmedwordlength)+12=40bittimes.

Character time = 40 / 10 [ (programmed word length =

7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4

characters.

Due to limitations involved in servicing a number of

simultaneousinterruptsinPCsandmulti-channelsys-

tems,the850offerssharedwire-orinterruptsbysetting

MCR bit-5 to a logic 1. When using this mode, the

connection of a 200-500 ohm resistor is required be-

tweentheIRQA/INTpinandsignalgroundtoprovidean

acceptable logic 0 level. The other interrupts (IRQB,

IRQC) are inactive when using this mode.

ProgrammingtheBaudRateGeneratorRegistersDLM

(MSB) and DLL (LSB) provides a user capability for

selecting the desired final baud rate. The example in

Table 4 below, shows the two selectable baud rate

tables available when using a 7.3728 MHz crystal.

Programmable Baud Rate Generator

The850supportshighspeedmodemtechnologiesthat

have increased input data rates by employing data

compression schemes. For example a 33.6Kbps mo-

dem that employs data compression may require a

115.2Kbpsinputdatarate. A128.0KbpsISDNmodem

thatsupportsdatacompressionmayneedaninputdata

rateof460.8Kbps.The850cansupportastandarddata

rate of 921.6Kbps with a crystal of 14.7456MHz.

R1

50-120

R2

1M

X1

Asinglebaudrategeneratorisprovidedforthetransmit-

terandreceiver, allowingindependentTX/RXchannel

control. The programmable Baud Rate Generator is

capable of accepting an input clock up to 24 MHz, as

required for supporting a 1.5Mbps data rate. The 850

can be configured for internal or external clock opera-

tion. For internal clock oscillator operation, an industry

1.8432 MHz

C1

22pF

C2

33pF

Rev. 1.20

20

XR16C850

Output

User

DLM

Program

Value

DLL

Program

Value

Baud Rate Baud Rate 16 x Clock 16 x Clock

MCR

BIT-7=1

MCR

Bit-7=0

Divisor

(Decimal)

Divisor

(HEX)

50

75

150

300

600

1200

2400

4800

7200

9600

19.2k

38.4k

57.6k

115.2k

200

300

600

1200

2400

2304

1536

768

384

192

96

48

24

16

12

900

600

300

180

C0

60

30

18

10

0C

06

09

06

03

01

00

80

C0

60

30

18

10

0C

06

03

02

01

4800

9600

19.2K

28.8K

38.4k

76.8k

153.6k

230.4k

460.8k

6

3

2

1

03

02

01

Table4. BAUDRATEGENERATORPROGRAMMINGTABLE(7.3728MHzCLOCK)

MCR

Bit-7=0

Divide

by

1 logic

Clock

Oscillator

Logic

Baudrate

Generator

Logic

XTAL1

XTAL2

-BAUDOUT

Divide

by

4 logic

MCR

Bit-7=1

Figure 11. Baud Rate Generator Circuitry

Rev. 1.20

21

XR16C850

Sleep mode enable during initialization example:

DMA Operation

Write LCR with “BF” hex

Set EFR bit-4 to logic 1

; access to EFR registers

; enable enhanced function bits

The850FIFOtriggerlevelprovidesadditionalflexibility

to the user for block transfer operation. LSR bits 5-6

provide an indication when the transmitter is empty or

has an empty location(s). The user can optionally

operate the transmit and receive FIFOs in the DMA

mode(FCRbit-3).WhenthetransmitandreceiveFIFOs

are enabled and the DMA mode is deactivated (DMA

Mode“0”), the850activatestheinterruptoutputpinfor

each data transmit or receive operation. When DMA

mode is activated (DMA Mode “1”), the user takes the

advantageofblockmodeoperationbyloadingorunload-

ing the FIFO in a block sequence determined by the

preset trigger level. In this mode, the 850 sets the

interrupt output pin when characters in the transmit

FIFOs are below the transmit trigger level, or the

characters in the receive FIFOs are above the receive

trigger level. Transmit or receive DMA operation is

selected by EMSR register bit 2.

Write LCR with op. value ; set LCR with op. parameters

Set IER bit-4 to logic 1

; enable sleep mode.

; It goes to sleep when:

; no pending interrupt,

; no modem port activity then enters

; sleep mode by stopping osc.

For lowest sleep current the following pins should be left at logic

1state:S1,S2,A4,A9,BUS8/16,CLK8/16,CLKSEL,-DMA,-DACK,

SEL, TC and RX.

Loopback Mode

The internal loopback capability allows onboard diag-

nostics.Inthismode,thenormalmodeminterfacepins

are disconnected and reconfigured for loopback inter-

nally. MSR bits 4-7 are also disconnected. However,

MCR register bits 0-3 can be used for controlling

loopback diagnostic testing. In this mode, OP1 and

OP2 in the MCR register (bits 0-1) control the modem

-RIand-CDinputsrespectively.MCRsignals-DTRand

-RTS(bits0-1)areusedtocontrolthemodem-CTSand

-DSR inputs respectively. The transmitter output (TX)

andthereceiverinput(RX)aredisconnectedfromtheir

associated interface pins, and instead are connected

together internally (See Figure 12). The -CTS, -DSR,

-CD, and -RI are disconnected from their normal

modemcontrolinputspins,andinsteadareconnected

internallyto-DTR,-RTS,-OP1and-OP2.Loopbacktest

dataisenteredintothetransmitholdingregisterviathe

user data bus interface, D0-D7. The transmit UART

serializes the data and passes the serial data to the

receiveUARTviatheinternalloopbackconnection.The

receiveUARTconvertstheserialdatabackintoparallel

data that is then made available at the user data

interface, D0-D7. The user optionally compares the

receiveddatatotheinitialtransmitteddataforverifying

errorfreeoperationoftheUARTTX/RXcircuits. Inthis

mode, the receiver, transmitter and modem control

interruptsarefullyoperational.However,theinterrupts

can only be read using lower four bits of the Modem

Control Register (MCR bits 0-3) instead of the four

ModemStatusRegisterbits4-7.Theinterruptsarestill

controlled by the IER.

Sleep Mode

The 850 is designed to operate with low power con-

sumption. A sleep mode is included to further reduce

power consumption when the chip is not being used.

Theoperatingparametersaremaintainedwhileinsleep

mode. With EFR bit-4 and IER bit-4 enabled (set to a

logic 1), the 850 enters the sleep mode when no

interruptispendingandnoactivitiesonthemodemport.

Ifanexternalclockissuppliedtothe850,youmaywant

tostopit.The850resumesnormaloperationwhenaRX

character’s start bit is detected, a change of state on

anyofthemodeminputpinsRX,-RI,-CTS,-DSR,-CD,

or transmit data is loaded into the FIFO by the user. It

typically takes 30us for the crystal oscillator to restart

from sleep mode depending on the crystal properties.

This delay must be taken into consideration during

designasRxcharacter(s)maybelostsinceitdepends

on the operating bit rate. If the sleep mode is enabled

and the 850 is awakened by one of the conditions

described above, it will return to the sleep mode auto-

matically after the last character is transmitted or read

bytheuserandnointerruptispending.Inanycase,the

chipwillnotentersleepmodewhileaninterrupt(s)isstill

pending and the oscillator would still be running. The

850 will stay in the sleep mode of operation until it is

disabled by setting IER bit-4 to a logic 0.

Rev. 1.20

22

XR16C850

Transmit

FIFO

Registers

Transmit

Shift

Register

TX

D0-D7

-IOR,IOR

-IOW,IOW

RESET

Flow

Control

Logic

Ir

Encoder

Receive

FIFO

Receive

Shift

Registers

Register

RX

A0-A2

-AS

CS0,CS1

-CS2

Flow

Control

Logic

Ir

Decoder

-DDIS

-RTS

-CD

-DTR

INT

-RXRDY

-TXRDY

-RI

-OP1

XTAL1

RCLK

XTAL2

-DSR

-OP2

-BAUDOUT

-CTS

Figure 12. INTERNAL LOOPBACK MODE DIAGRAM

Rev. 1.20

23

XR16C850

REGISTER FUNCTIONAL DESCRIPTIONS

The following table delineates the assigned bit functions for the fifteen 850 internal registers. The assigned bit

functions are more fully defined in the following paragraphs.

XR16C850 ACCESSIBLE REGISTERS

A2 A1 A0

Register

[Default]

Note *3

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

General Registers are accessible when LCR bit-7 is not a Logic 1 or "BF" Hex

0

1

RHR[XX]

THR[XX]

IER[00]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-0

0/

-CTS

interrupt

0/

-RTS

interrupt

0/

Xoff

interrupt

0/

Sleep

mode

modem

status

interrupt

receive

line

status

interrupt

transmit

holding

register

receive

holding

register

0

1

0

1

0

1

FCR[00]

ISR [01]

LCR [00]

MCR[00]

LSR [60]

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

0/TX

trigger

(MSB)

0/TX

trigger

(LSB)

DMA

mode

select

XMIT

FIFO

reset

RCVR

FIFO

reset

FIFO

enable

0/

-RTS,

-CTS

0/

Xoff

int

priority

bit-2

int

priority

bit-1

int

priority

bit-0

int

status

FIFO’s

enabled

FIFO’s

enabled

divisor

latch

enable

set

break

set

parity

even

parity

enable

stop

bits

word

length

bit-1

word

length

bit-0

Clock

select

0/

IRRT

enable

0/

Xon

Any

loop

back

-OP2

-OP1

-RTS

-DTR

0/

FIFO

error

trans.

empty

trans.

holding

empty

break

interrupt

framing

error

parity

error

overrun

error

receive

data

ready

1

0

1

MSR [00]

-CD

-RI

-DSR

bit-5

-CTS

bit-4

delta

-CD

delta

-RI

delta

-DSR

delta

-CTS

SCPAD[FF]

bit-7

bit-6

bit-3

bit-2

bit-1

bit-0

Baud rate generator registers are accessible only when LCR bit-7 is set to Logic 1.

0

1

DLL [00]

DLM [00]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-9

bit-0

bit-8

bit-15

bit-14

bit-13

bit-12

bit-11

bit-10

Rev. 1.20

24

XR16C850

A2 A1 A0

Register

[Default]

Note *3

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

Enhanced Registers are accessible only when LCR is set to "BF" Hex.

1

0

1

0

1

0

1

Xon-1[00]

Xon-2[00]

Xoff-1[00]

Xoff-2[00]

bit-7

bit-15

bit-7

bit-6

bit-14

bit-6

bit-5

bit-13

bit-5

bit-4

bit-12

bit-4

bit-3

bit-11

bit-3

bit-2

bit-10

bit-2

bit-1

bit-9

bit-1

bit-9

bit-0

bit-8

bit-0

bit-8

bit-15

bit-14

bit-13

bit-12

bit-11

bit-10

0

1

TRG [00]

Trig/

FC

Trig/

FC

Trig/

FC

Trig/

FC

Trig

FC

Trig/

FC

Trig/

FC

Trig/

FC

FCTR [00]

Rx/Tx

Mode

SCPAD

Swap

Trig

Bit-1

Trig

Bit-0

RS485

Auto

control

IrRx

Inv.

-RTS

Delay

Bit-1

-RTS

Delay

Bit-0

0

1

0

EFR [00]

Auto

-CTS

Auto

-RTS

Special

Char.

Enable

IER

Cont-3

Tx,Rx

Cont-2

Tx,Rx

Cont-1

Tx,Rx

Cont-0

Tx,Rx

select

Bits 4-7, Control Control Control Control

ISR, FCR

Bits 4-5,

MCR

Bits 5-7

1

EMSR [00]

Not

Used

Not

Used

Not

Used

Not

Used

Not

Used

Rx/Tx

DMA

Select

ALT.

Rx/Tx

FIFO

Rx/Tx

FIFO

Count

Note *3: The value represents the register’s initialized Hex value. An “X” signifies a 4-bit un-initialized nibble.

Rev. 1.20

25

XR16C850

Transmit and Receive Holding Register

IERVsReceiveFIFOInterruptModeOperation

The serial transmitter section consists of an 8-bit

TransmitHoldRegister(THR)andTransmitShiftReg-

ister(TSR).ThestatusoftheTHRisprovidedintheLine

StatusRegister(LSR).WritingtotheTHRtransfersthe

contentsofthedatabus(D7-D0)totheTHR, providing

thattheTHRorTSRisempty.TheTHRemptyflaginthe

LSRregisterwillbesettoalogic1whenthetransmitter

is empty or when data is transferred to the TSR. Note

that a write operation can be performed when the

transmit holding register empty flag is set (logic 0 =

FIFOfull,logic1=atleastoneFIFOlocationavailable).

When the receive FIFO (FCR BIT-0 = a logic 1) and

receiveinterrupts(IERBIT-0=logic1)areenabled,the

receive interrupts and register status will reflect the

following:

A)Thereceivedataavailableinterruptsareissuedtothe

external CPU when the FIFO has reached the pro-

grammedtriggerlevel. ItwillbeclearedwhentheFIFO

dropsbelowtheprogrammedtriggerlevel.

B) FIFO status will also be reflected in the user acces-

sibleISRregisterwhentheFIFOtriggerlevelisreached.

Both the ISR register status bit and the interrupt will be

cleared when the FIFO drops below the trigger level.

Theserialreceivesectionalsocontainsan8-bitReceive

HoldingRegister, RHR. Receivedataisremovedfrom

the850andreceiveFIFObyreadingtheRHRregister.

The receive section provides a mechanism to prevent

false starts. On the falling edge of a start or false start

bit, an internal receiver counter starts counting clocks

at 16x clock rate. After 7 1/2 clocks the start bit time

should be shifted to the center of the start bit. At this

time the start bit is sampled and if it is still a logic 0 it

is validated. Evaluating the start bit in this manner

preventsthereceiverfromassemblingafalsecharacter.

Receiver status codes will be posted in the LSR.

C) The data ready bit (LSR BIT-0) is set as soon as a

character is transferred from the shift register to the

receive FIFO. It is reset when the FIFO is empty.

IERVsReceive/TransmitFIFOPolledModeOpera-

tion

When FCR BIT-0 equals a logic 1; resetting IER bits 0-

3enablesthe850intheFIFOpolledmodeofoperation.

Sincethereceiverandtransmitterhaveseparatebitsin

the LSR either or both can be used in the polled mode

byselectingrespectivetransmitorreceivecontrolbit(s).

Device Identification

TheXR16C850providesDeviceidentificationandDe-

viceRevisioncodetodistinguishthepartfromothers.It

is suggested to read the identification and revision

information from the part only during the power on

initialization routine to avoid disturbing the baud rate

generator.

A)LSRBIT-0willbealogic1aslongasthereisonebyte

in the receive FIFO.

B)LSRBIT1-4willindicateifanoverrunerroroccurred

inthereceiver.

To read the identification number from the device, it is

requiredtosetthebaudrategeneratordivisorlatchto“1”

(LCRbit-7=logic1)andsetthecontentofthebaudrate

generatorDLLandDLMregistersto“00”hex.Thenread

the content of DLM for “10” hex for XR16C850 and the

content of DLL for the revision of the part.

C) LSR BIT-5 will indicate when the transmit FIFO is

empty.

D)LSRBIT-6willindicatewhenboththetransmitFIFO

and transmit shift register are empty.

E) LSR BIT-7 will indicate any data errors within the

receive FIFO. This bit will clear when the error byte is

unloaded.

Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the inter-

ruptsfromreceiverready,transmitterempty,linestatus

and modem status registers. These interrupts would

normally be seen on the 850 INT output pin.

IER BIT-0:

Logic 0 = Disable the receiver ready interrupt. (normal

defaultcondition)

Rev. 1.20

26

XR16C850

Logic 1 = Enable the receiver ready interrupt. The

receiver ready interrupt is cleared when LSR is read.

IER BIT-7:

Logic 0 = Disable the CTS interrupt. (normal default

condition)

IER BIT-1:

Logic 1 = Enable the CTS interrupt. The 850 issues an

interrupt when CTS pin transitions from a logic 0 to a

logic 1 as reported in MSR register. The interrupt is

cleared by reading the MSR register.

Logic 0 = Disable the transmitter empty interrupt.

(normaldefaultcondition)

Logic 1 = Enable the transmitter empty interrupt. The

transmitteremptyinterruptisclearedwhenISRisread.

FIFOControlRegister(FCR)

IER BIT-2:

Logic 0 = Disable the receiver line status interrupt.

(normaldefaultcondition)

Logic 1 = Enable the receiver line status interrupt. The

receiver line interrupt is cleared when LSR is read.

This register is used to enable the FIFOs, clear the

FIFOs,setthetransmit/receiveFIFOtriggerlevels,and

select the DMA mode. The DMA, and FIFO modes are

definedasfollows:

IER BIT-3:

DMAMODE

Logic 0 = Disable the modem status register interrupt.

(normaldefaultcondition)

Logic 1 = Enable the modem status register interrupt.

The modem status interrupt is cleared when MSR is

read.

Mode0 Setandenabletheinterruptforeachsingle

transmit or receive operation, and is similar to the

ST16C450mode.TransmitReady(-TXRDY)willgotoa

logic0wheneveranemptytransmitspaceisavailable

intheTransmitHoldingRegister(THR).ReceiveReady

(-RXRDY) will go to a logic 0 whenever the Receive

Holding Register (RHR) is loaded with a character.

IER BIT -4:

Logic 0 = Disable sleep mode. (normal default condi-

tion)

Mode1 Set and enable the interrupt in a block

mode operation. The transmit interrupt is set when the

transmit FIFO is below the programmed trigger level. -

TXRDY remains a logic 0 as long as one empty FIFO

location is available. The receive interrupt is set when

the receive FIFO fills to the programmed trigger level.

However the FIFO continues to fill regardless of the

programmedleveluntiltheFIFOisfull.-RXRDYremains

a logic 0 as long as the FIFO fill level is above the

programmedtriggerlevel.

Logic1=Enablesleepmode.SeeSleepModesection

fordetails.

IER BIT-5:

Logic0=Disablethesoftwareflowcontrol,receiveXoff

interrupt.(normaldefaultcondition)

Logic1=Enablethesoftwareflowcontrol,receiveXoff

interrupt.TheXoffinterruptisclearedbyreadingtheISR

registeroruponreceivingaXoncharacter. Also, when

Special Character mode is enabled (EFR-bit 5 =1)

readingtheISRregisterorafollowingreceivedcharacter

will cleared the interrupt. See Software Flow Control

section for details.

FCR BIT-0:

Logic 0 = Disable the transmit and receive FIFO.

(normaldefaultcondition)

Logic1=EnablethetransmitandreceiveFIFO.Thisbit

mustbea“1”whenotherFCRbitsarewrittentoorthey

will not be programmed.

IER BIT-6:

Logic 0 = Disable the RTS interrupt. (normal default

condition)

Logic 1 = Enable the RTS interrupt. The 850 issues an

interrupt when the RTS pin transitions from a logic 0 to

a logic 1 as reported in MSR bit-register. The interrupt

is cleared by reading the MSR register.

FCR BIT-1:

Logic 0 = No FIFO receive reset. (normal default

condition)

Logic 1 = Clears the FIFO counter and resets the

pointerslogic(thereceiveshiftregisterisnotclearedor

altered).Thisbitwillreturntoalogic0afterclearingthe

FIFO.

Rev. 1.20

27

XR16C850

FCR BIT-2:

transmitemptyinterruptwhenthenumberofcharacters

in FIFO drops below the selected trigger level.

Logic 0 = No FIFO transmit reset. (normal default

condition)

Logic 1 = Clears the FIFO counter and resets the

pointers logic (the transmit shift register is not cleared

or altered). This bit will return to a logic 0 after clearing

the FIFO.

TRIGGERTABLE-A(Transmit)

“Default setting after reset, ST16C550 mode”

BIT-5

BIT-4

FIFO trigger level

FCR BIT-3:

X

None

Logic0=SetDMAmode“0”.(normaldefaultcondition)

Logic 1 = Set DMA mode “1.”

TRIGGERTABLE-B(Transmit)

Transmit operation in mode “0”:

When the 850 is in the ST16C450 mode (FIFOs dis-

abled, FCR bit-0 = logic 0) or in the FIFO mode (FIFOs

enabled, FCR bit-0 = logic 1, FCR bit-3 = logic 0) and

when there are no characters in the transmit FIFO or

transmitholdingregister,the-TXRDYpinwillbealogic

0. Once active the -TXRDY pin will go to a logic 1 after

the first character is loaded into the transmit holding

register.

BIT-5

BIT-4

FIFO trigger level

0

1

0

1

0

1

16

8

24

30

TRIGGERTABLE-C(Transmit)

Receiveoperationinmode“0”:

When the 850 is in mode “0” (FCR bit-0 = logic 0) or in

the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic

0)andthereisatleastonecharacterinthereceiveFIFO,

the -RXRDY pin will be a logic 0. Once active the -

RXRDY pin will go to a logic 1 when there are no more

characters in the receiver.

BIT-5

BIT-4

FIFO trigger level

0

1

0

1

0

1

8

16

32

56

Transmit operation in mode “1”:

Whenthe850isinFIFOmode(FCRbit-0=logic1,FCR

bit-3 = logic 1 ), the -TXRDY pin will be a logic 1 when

the transmit FIFO is completely full. It will be a logic 0

if one or more FIFO locations are empty.

TRIGGERTABLE-D(Transmit)

BIT-5

BIT-4

FIFO trigger level

X

Userprogrammable

Triggerlevels

Receiveoperationinmode“1”:

Whenthe850isinFIFOmode(FCRbit-0=logic1,FCR

bit-3 = logic 1) and the trigger level has been reached,

oraReceiveTimeOuthasoccurred,the-RXRDYpinwill

gotoalogic0.Onceactivated,itwillgotoalogic1after

there are no more characters in the FIFO.

FCRBIT6-7:(logic0orclearedisthedefaultcondition,

RX trigger level =8)

These bits are used to set the trigger level for the

receiver FIFO interrupt. The interrupt will trigger again

when RX data is unloaded below the threshold and

incoming data fills it back up to the trigger level. The

FCTR Bits 4-5 selects one of the following tables.

FCRBIT4-5:(logic0orclearedisthedefaultcondition,

TX trigger level = none)

TheXR16C850provides4userselectabletriggerlevels,

The FCTR Bits 4-5 selects one of the following tables.

These bits are used to set the trigger level for the

transmit FIFO interrupt. The XR16C850 will issue a

Rev. 1.20

28

XR16C850

TRIGGERTABLE-A(Receive)

“Default setting after reset, ST16C550 mode”

interrupt status register is read, the interrupt status is

cleared.Howeveritshouldbenotedthatonlythecurrent

pending interrupt is cleared by the read. A lower level

interrupt may be seen after re-reading the interrupt

statusbits.TheInterruptSourceTable6(below)shows

the data values (bit 0-5) for the six prioritized interrupt

levelsandtheinterruptsourcesassociatedwitheachof

theseinterruptlevels.

BIT-7

BIT-6

FIFO trigger level

0

1

0

1

0

1

4

8

14

TRIGGERTABLE-B(Receive)

BIT-7

BIT-6

FIFO trigger level

0

1

0

1

0

1

8

16

24

28

TRIGGERTABLE-C(Receive)

BIT-7

BIT-6

FIFO trigger level

0

1

0

1

0

1

8

16

56

60

TRIGGERTABLE-D(Receive)

BIT-7

BIT-6

FIFO trigger level

X

Userprogrammable

Triggerlevels

Interrupt Status Register (ISR)

The 850 provides six levels of prioritized interrupts to

minimize external software interaction. The Interrupt

StatusRegister(ISR)providestheuserwithsixinterrupt

status bits. Performing a read cycle on the ISR will

providetheuserwiththehighestpendinginterruptlevel

to be serviced. No other interrupts are acknowledged

until the pending interrupt is serviced. Whenever the

Rev. 1.20

29

XR16C850

Table6, INTERRUPTSOURCETABLE

Priority

Level

[ ISR BITS ]

Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

Source of the interrupt

1

2

3

4

5

6

0

1

0

1

0

1

0

1

0

1

0

1

0

LSR(ReceiverLineStatusRegister)

RXRDY(ReceivedDataReady)

RXRDY(ReceiveDatatimeout)

TXRDY(TransmitterHoldingRegisterEmpty)

MSR (Modem Status Register)

RXRDY(ReceivedXoffsignal)/Specialcharacter

CTS, RTS change of state

ISR BIT-0:

sets. The first is by setting bit-7 = 1 to select the baud

ratedivisor(DLLandDLM)registers,andthesecondset

ofregistersisselectedwhena“BF”hexiswrittentoLCR

to select the enhanced register set.

Logic 0 = An interrupt is pending and the ISR contents

may be used as a pointer to the appropriate interrupt

serviceroutine.

Logic 1 = No interrupt pending. (normal default condi-

tion)

LCRBIT0-1:(logic0orclearedisthedefaultcondition)

Thesetwobitsspecifythewordlengthtobetransmitted

orreceived. Theupperunusedbit(s)inthereceiveddata

byte is set to zero.

ISRBIT1-3:(logic0orclearedisthedefaultcondition)

Thesebitsindicatethesourceforapendinginterruptat

interruptprioritylevels1,2,and3(SeeInterruptSource

Table).

BIT-1

BIT-0

Word length

ISRBIT4-5:(logic0orclearedisthedefaultcondition)

These bits are enabled when EFR bit-4 is set to a logic

1. ISR bit-4 indicates that matching Xoff character(s)

havebeendetected.ISRbit-5indicatesthatCTS,RTS

havebeengenerated.Notethatoncesettoalogic1,the

ISR bit-4 will stay a logic 1 until Xon character(s) are

received.

0

1

0

1

0

1

5

6

7

8

LCR BIT-2: (logic 0 or cleared is the default condition)

The length of stop bit is specified by this bit in conjunc-

tion with the programmed word length.

ISRBIT6-7:(logic0orclearedisthedefaultcondition)

Thesebitsaresettoalogic0whentheFIFOisnotbeing

used. They are set to a logic 1 when the FIFOs are

enabled

BIT-2

Word length

Stop bit

length

Line Control Register (LCR)

(Bittime(s))

The Line Control Register is used to specify the asyn-

chronousdatacommunicationformat.Thewordlength,

the number of stop bits, and the parity are selected by

writingtheappropriatebitsinthisregister.Thisregister

alsohasasecondaryfunctiontoselect2otherregister

0

1

5,6,7,8

5

6,7,8

1

1-1/2

2

Rev. 1.20

30

XR16C850

LCRBIT-3:

Parity or no parity can be selected via this bit.

Logic 0 = No parity (normal default condition)

Logic 1 = A parity bit is generated during the transmis-

sion, thereceiverchecksandreportsparityerrorinthe

LSRregister. Theparityisnotpresentedinthereceived

data byte.

LCRBIT-7:

The internal baud rate counter latch and Enhance

Featuremodeenable.

Logic 0 = Divisor latch disabled. (normal default condi-

tion)

Logic1=Selectbaudratedivisors(DLLandDLM)and

enhancedfeatureregistersetenabled

LCRBIT-4:

If the parity bit is enabled with LCR bit-3 set to a logic

1, LCR BIT-4 selects the even or odd parity format.

Logic 0 = ODD Parity is generated by forcing an odd

numberoflogic1’sinthetransmitteddata.Thereceiver

must be programmed to check the same format. (nor-

maldefaultcondition)

Modem Control Register (MCR)

Thisregistercontrolstheinterfacewiththemodemora

peripheraldevice.

MCRBIT-0:

Logic 1 = EVEN Parity is generated by forcing an even

numberoflogic1’sinthetransmitteddata.Thereceiver

must be programmed to check the same format.

Logic0=Force-DTRoutputtoalogic1.(normaldefault

condition)

Logic 1 = Force -DTR output to a logic 0.

LCRBIT-5:

MCRBIT-1:

Iftheparitybitisenabled,LCRBIT-5selectstheforced

parityformat.

Logic0=Force-RTSoutputtoalogic1.(normaldefault

condition)

LCRBIT-5=logic0,parityisnotforced(normaldefault

condition)

LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit

isforcedtoalogical1forthetransmitandreceivedata.

LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit

isforcedtoalogical0forthetransmitandreceivedata.

Logic 1 = Force -RTS output to a logic 0.

Automatic RTS may be used for hardware flow control

by enabling EFR bit-6 (See EFR bit-6).

MCRBIT-2:

Logic 0 = Set -OP1 output to a logic 1. (normal default

condition)

Logic 1 = Set -OP1 output to a logic 0.

LCR

Bit-3

LCR

Bit-4

LCR

Bit-5

Parity selection

MCRBIT-3:

Logic 0 = Set -OP2 output to a logic 1 (STD mode).

ForcesIRQxoutputstothreestatemodeduringthePC

mode.(normaldefaultcondition)

Logic 1 = Set -OP2 output to a logic 0 (STD mode).

Forces the IRQx outputs to the active mode during the

PC mode.

0

1

X

0

1

0

1

X

0

1

No parity

Oddparity

Evenparity

Force parity “1”

Forced parity “0”

MCRBIT-4:

LCRBIT-6:

Logic 0 = Disable loop-back mode. (normal default

condition)

Logic 1 = Enable local loop-back mode (diagnostics).

When enabled the Break control bit causes a break

conditiontobetransmitted(theTXoutputisforcedtoa

logic 0 state). This condition exists until disabled by

setting LCR bit-6 to a logic 0.

MCRBIT-5:

Logic 0 = No TX break condition. (normal default

condition)

Logic0=DisableXonAnyfunction(for16C550compat-

ibility). (normal default condition)

Logic 1 = Forces the transmitter output (TX) to a logic

0 for alerting the remote receiver to a line break condi-

tion.

Logic1=EnableXonAnyfunction.InthismodeanyRX

characterreceivedwillenableXon.

Rev. 1.20

31

XR16C850

MCRBIT-6:

previous data in the shift register is overwritten. Note

thatunderthisconditionthedatabyteinthereceiveshift

registerisnottransferintotheFIFO, thereforethedata

in the FIFO is not corrupted by the error.

Logic 0 = Enable Modem receive and transmit input/

outputinterface.(normaldefaultcondition)

Logic 1 = Enable infrared IrDA receive and transmit

inputs/outputs. While in this mode, the TX/RX output/

Inputsareroutedtotheinfraredencoder/decoder.The

data input and output levels will conform to the IrDA

infrared interface requirement. As such, while in this

modetheinfraredTXoutputwillbealogic0duringidle

dataconditions.Caremustbetakenintoconsideration

inthedesignnottooverheattheIRLEDduringpowerup

initialization state while TX output is still at logic 1.

LSR BIT-2:

Logic 0 = No parity error (normal default condition)

Logic 1 = Parity error. The receive character does not

have correct parity information and is suspect. In the

FIFO mode, this error is associated with the character

at the top of the FIFO.

LSR BIT-3:

Procedure to enable the IR encoder and decoder functions during

initialization routine.

Logic 0 = No framing error (normal default condition).

Logic 1 = Framing error. The receive character did not

have a valid stop bit(s). In the FIFO mode this error is

associated with the character at the top of the FIFO.

Write LCR with “BF” hex ; access to EFR “shadow” register

Set EFR bit-4 to logic 1 ; enable enhanced function bits

Write LCR with op. values ; set operating parameters

LSR BIT-4:

Set MCR bit-6 to logic 1 ; enable IR mode, TX pin goes logic 0

Logic0=Nobreakcondition(normaldefaultcondition)

Logic1=Thereceiverreceivedabreaksignal(RXwas

a logic 0 for one character frame time). In the FIFO

mode,onlyonebreakcharacterisloadedintotheFIFO.

MCRBIT-7:

This bit overrides the CLKSEL pin selection.

Logic 0 = Divide by one. The input clock (crystal or

external)isdividedbysixteenandthenpresentedtothe

Programmable Baud Rate Generator (BGR) without

furthermodification,i.e.,dividebyone.(normal,default

condition)

Logic 1 = Divide by four. The divide by one clock

describedinMCRbit-7equalsalogic0,isfurtherdivided

byfour(alsoseeProgrammableBaudRateGenerator

section).

LSR BIT-5:

This bit is the Transmit Holding Register Empty indica-

tor. This bit indicates that the UART is ready to accept

a new character for transmission. In addition, this bit

causestheUARTtoissueaninterrupttoCPUwhenthe

THRinterruptenableisset.TheTHRbitissettoalogic

1 when a character is transferred from the transmit

holdingregisterintothetransmittershiftregister.Thebit

is reset to logic 0 concurrently with the loading of the

transmitter holding register by the CPU. In the FIFO

mode this bit is set when the transmit FIFO is empty;

itisclearedwhenatleast1byteiswrittentothetransmit

FIFO.

Line Status Register (LSR)

This register provides the status of data transfers

between the 850 and the CPU.

LSR BIT-0:

LSR BIT-6:

Logic 0 = No data in receive holding register or FIFO.

(normaldefaultcondition)

Logic 1 = Data has been received and is saved in the

receiveholdingregisterorFIFO.

This bit is the Transmit Empty indicator. This bit is set

to a logic 1 whenever the transmit holding register and

the transmit shift register are both empty. It is reset to

logic0 whenevereithertheTHRorTSRcontainsadata

character. In the FIFO mode this bit is set to one

whenever the transmit FIFO and transmit shift register

are both empty.

LSR BIT-1:

Logic0=Nooverrunerror. (normaldefaultcondition)

Logic1=Overrunerror.Adataoverrunerroroccurredin

thereceiveshiftregister.Thishappenswhenadditional

data arrives while the FIFO is full. In this case the

LSR BIT-7:

Logic 0 = No Error (normal default condition)

Rev. 1.20

32

XR16C850

Logic1=Atleastoneparityerror,framingerrororbreak

indicationisinthecurrentFIFOdata.Thisbitiscleared

when LSR register is read.

Normally MSR bit-4 bit is the compliment of the -CTS

input. However in the loop-back mode, this bit is

equivalent to the RTS bit in the MCR register.

Modem Status Register (MSR)

MSRBIT-5:

DSR (active high, logical 1). Normally this bit is the

compliment of the -DSR input. In the loop-back mode,

this bit is equivalent to the DTR bit in the MCR register.

This register provides the current state of the control

interface signals from the modem, or other peripheral

device that the 850 is connected to. Four bits of this

register are used to indicate the changed information.

These bits are set to a logic 1 whenever a control input

from the modem changes state. These bits are set to a

logic 0 whenever the CPU reads this register.

MSRBIT-6:

RI (active high, logical 1). Normally this bit is the

complimentofthe-RIinput. Intheloop-backmodethis

bit is equivalent to the OP1 bit in the MCR register.

MSRBIT-0:

MSRBIT-7:

Logic 0 = No -CTS Change (normal default condition)

Logic 1 = The -CTS input to the 850 has changed state

since the last time it was read. A modem Status

Interruptwillbegenerated.

CD (active high, logical 1). Normally this bit is the

complimentofthe-CDinput.Intheloop-backmodethis

bit is equivalent to the OP2 bit in the MCR register.

Scratchpad Register (SPR)

MSRBIT-1:

Logic 0 = No -DSR Change (normal default condition)

Logic1=The-DSRinputtothe850haschangedstate

since the last time it was read. A modem Status

Interruptwillbegenerated.

The XR16C850 provides a temporary data register to

store 8 bits of user information.

Enhanced Feature Register (EFR)

MSRBIT-2:

Enhanced features are enabled or disabled using this

register.

Logic 0 = No -RI Change (normal default condition)

Logic 1 = The -RI input to the 850 has changed from a

logic 0 to a logic 1. A modem Status Interrupt will be

generated.

Bits-0 through 4 provide single or dual character soft-

ware flow control selection. When the Xon1 and Xon2

and/orXoff1andXoff2modesareselected(seetable7),

the double 8-bit words are concatenated into two se-

quentialcharacters.

MSRBIT-3:

Logic 0 = No -CD Change (normal default condition)

Logic 1 = Indicates that the -CD input to the 850 has

changedstatesincethelasttimeitwasread.Amodem

Status Interrupt will be generated.

EFRBIT0-3:(logic0orclearedisthedefaultcondition)

Combinations of software flow control can be selected

by programming these bits.

MSRBIT-4:

-CTSfunctionsashardwareflowcontrolsignalinputifit

is enabled via EFR bit-7. The transmit holding register

flow control is enabled/disabled by MSR bit-4. Flow

control(whenenabled)allowsthestartingandstopping

the transmissions based on the external modem -CTS

signal. A logic 1 at the -CTS pin will stop 850 transmis-

sions as soon as current character has finished trans-

mission.

Rev. 1.20

33

XR16C850

Cont-3

Cont-2

Cont-1

Cont-0

TX, RX software flow controls

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

X

0

1

No transmit flow control

TransmitXon1/Xoff1

TransmitXon2/Xoff2

TransmitXon1andXon2/Xoff1andXoff2

Noreceiveflowcontrol

ReceivercomparesXon1/Xoff1

ReceivercomparesXon2/Xoff2

TransmitXon1/Xoff1.

ReceivercomparesXon1andXon2,

Xoff1andXoff2

0

1

0

1

0

1

TransmitXon2/Xoff2

ReceivercomparesXon1andXon2/Xoff1andXoff2

TransmitXon1andXon2/Xoff1andXoff2

ReceivercomparesXon1andXon2/Xoff1andXoff2

No transmit flow control

ReceivercomparesXon1andXon2/Xoff1andXoff2

Table 7. SOFTWARE FLOW CONTROL FUNCTIONS

EFR BIT-4:

Logic 1 = Special Character Detect Enabled. The 850

compareseachincomingreceivecharacterwithXoff-2

data. If a match exists, the received data will be

transferred to FIFO and ISR bit-4 will be set to indicate

detection of special character. Bit-0 in the X-registers

correspondswiththeLSBbitforthereceivecharacter.

Whenthisfeatureisenabled, thenormalsoftwareflow

control must be disabled (EFR bits 0-3 must be set to

a logic 0).

Enhanced function control bit. The content of the IER

bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7

are enabled when this bit is set to logic 1. After

modifying these bits EFR bit-4 can be set to a logic 0 to

latch the new values. This feature prevents existing

softwarefromalteringoroverwritingthe850enhanced

functions.

Logic 0 = disable/latch enhanced features. IER bits 4-

7,ISRbits4-5,FCRbits4-5,andMCRbits5-7aresaved

toretaintheusersettings, thenIERbits4-7, ISRbits4-

5, FCR bits 4-5, and MCR bits 5-7 are initialized to the

defaultvaluesshownintheInternalRegisterTable.After

areset,theIERbits4-7,ISRbits4-5,FCRbits4-5,and

MCR bits 5-7 are set to a logic 0 to be compatible with

ST16C550mode.(normaldefaultcondition).

Logic 1 = Enables the enhanced functions. When this

bitissettoalogic1allenhancedfeaturesofthe850are

enabled and user settings stored during a reset will be

restored.

EFR BIT-6:

Automatic RTS is used for hardware flow control by

enabling EFR bit-6. The user must assert –RTS to

initiate this function. When AUTO RTS is selected, an

interruptwillbegeneratedwhenthereceiveFIFOisfilled

to the programmed Rx trigger level and -RTS will go to

alogic1whenitreachestheupperlimitofthehysterisis

level. -RTSwillreturntoalogic0whendataisunloaded

to the lower limit of the hysterisis. The state of this

registerbitchangeswiththestatusofthehardwareflow

control. -RTS functions normally when hardware flow

control is disabled.

EFR BIT-5:

0 = Automatic RTS flow control is disabled. (normal

defaultcondition)

1 = Enable Automatic RTS flow control.

Logic 0 = Special Character Detect Disabled (normal

defaultcondition)

Rev. 1.20

34

XR16C850

EFR bit-7:

Automatic CTS Flow Control.

FCTRBIT4-5:

Transmit / receive trigger table select.

Logic 0 = Automatic CTS flow control is disabled.

(normaldefaultcondition)

Logic1=EnableAutomaticCTSflowcontrol.Transmis-

sion will stop when -CTS goes to a logical 1. Transmis-

sion will resume when the -CTS pin returns to a logical

0.

FCTR

Bit-5

FCTR

Bit-4

Table

0

1

0

1

0

1

Table-A(TX/RX)

Table-B(TX/RX)

Table-C(TX/RX)

Table-D(TX/RX)

FEATURECONTROLREGISTER(FCTR)

ThisregistercontrolstheXR16C850newfunctionsthat

arenotavailableonST16C550orST16C650A.

FCTRBIT0-1:

FCTRBIT-6:

User selectable -RTS delay timer for hardware flow

control application. After reset, these bits are set to “0”

toselectthenexttriggerlevelforhardwareflowcontrol.

Register mode select.

0=ScratchPadregisterisselectedasgeneralreadand

writeregister.ST16C550compatiblemode.

1 = FIFO count register, Enhanced Mode Select Reg-

ister. Number of characters in transmit or receive

holding register can be read via scratch pad register

when this bit is set. Enhanced Mode is selected when

it is written into it.

FCTR

Bit-1

FCTR

Bit-0

Trigger

level

0

1

0

1

0

1

Nexttriggerlevel

4char+triggerlevel

6char+triggerlevel

8char+triggerlevel

FCTRBIT-7:

Programmabletriggerregisterselect.

0 = Receiver programmable trigger level register is

selected.

1 = Transmitter programmable trigger level register is

selected.

FCTRBIT-2:

0 = Select RX input as encoded IrDa data.

1 = Select RX input as active high encoded IrDa data.

TRIGGER LEVEL / FIFO DATA COUNT REGISTER

(TRG)

FCTRBIT-3:

Auto RS-485 Direction control.

User programmable transmit / receive trigger level

register.

0=StandardST16C550mode.Transmittergenerates

an interrupt when transmit holding register becomes

empty and transmit shift register is shifting data out.

1=EnableAutoRS485DirectionControlfunction.The

direction control signal, -OP1 pin, changes its output

logicstatefromlowtohighonebittimeafterthelaststop

bitofthelastcharacterisshiftedout.Also,theTransmit

interruptgenerationisdelayeduntilthetransmittershift

register becomes empty. The -OP1 output pin will

automaticallyreturntologichighstatewhenadatabyte

is loaded into the TX FIFO.

TRG BIT 0-7: Write only.

thesebitsareusedtoprogramdesiredtriggerlevelsthat

are not available in standard tables.

TRG BIT 0-7: Read only.

Transmit/receiveFIFOcount.Numberofcharactersin

transmit or receive FIFO can be read via this register.

Rev. 1.20

35

XR16C850

ENHANCEDMODESELECTREGISTER(EMSR)

This register is accessible only when FCTR Bit-6 is set

to “1”.

XR16C850EXTERNALRESETCONDITIONS

REGISTERS

RESETSTATE

EMSR BIT-0: “Write only”

IER

ISR

IER BITS 0-7 = logic 0

ISR BIT-0=1, ISR BITS 1-7 = logic

0

0 = Receive FIFO count register. The scratch pad

registerisusedtoprovidethereceiveFIFOcountwhen

it is read.

1 = Transmit FIFO count register. The scratch pad

registerisusedtoprovidethetransmitFIFOcountwhen

it is read.

LCR,MCR

LSR

BITS 0-7 = logic 0

LSR BITS 0-4 = logic 0,

LSR BITS 5-6 = logic 1 LSR, BIT 7

= logic 0

MSR

MSR BITS 0-3 = logic 0,

MSR BITS 4-7 = logic levels of the

input signals

EMSR BIT-1: “Write only”

0 = Normal.

1 = Alternate receive - transmit FIFO count. When

EMSRBit-0=1andEMSRBit-1=1,scratchpadregister

is used to provide the receive - transmit FIFO count

whenitisreadeveryalternatereadcycle.TheTRGBit-

7 will provide FIFO count mode information, TRG Bit-

7=0 receive mode, TRG Bit-7=1 transmit mode.

FCR, EFR

FCTR

EMSR

BITS 0-7 = logic 0

BITS 0-7 = logic 1

SCPAD

SIGNALS

RESETSTATE

EMSR BIT-2: “Write only”

ThisbitselectsandenablestheDMAinterfacefunction

on the 52-pin device, –DACK, -DRQ and TC become

active.OnlyTXorRXDMAcanbeenabledatonetime.

0 = Enable RX DMA

TX

Logic 1

-OP1

-OP2

-RTS

-DTR

-RXRDY

1 = Enable TX DMA

Logic 1

Logic 1 (STD mode),/ Three state

(PCmode)

EMSR BIT 3-7:

Reservedforfutureuse.

-TXRDY

Logic 0 (STD mode) / Three state

(PCmode)

IRQn/INT

Logic 0 (STD mode) / Three state

(PCmode)

Rev. 1.20

36

XR16C850

AC ELECTRICAL CHARACTERISTICS

T_A=0° - 70° C ( -40° - +85° C for IP, IJ, IQ packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.

Symbol

Parameter

Limits

3.3

Limits

5.0

Units

Conditions

Min

Max

Min

Max

T_1w,T_2wClock pulse duration

20

ns

MHz

ns

T_3w

Oscillator/Clockfrequency

Address strobe width

Address setup time

8

24

T

4w

5s

5h

50

15

10

0

10

50

5

25

10

5

0

10

25

5

8

50

T

Address hold time

T_6s

Address setup time

T6h

Chip select hold time

T_7d

T_7w

T_7h

T8d

T_9d

-IOR delay from chip select

-IORstrobewidth

Chip select hold time from -IOR

IOR delay from chip select

Read cycle delay

Note 1:

8

50

T_10d

T_11d

T_12d

T_12h

T_13d

T_13w

T_13h

T_14d

T_15d

T_16s

T_16h

T_17d

T_18d

CSOUT delay from chip select

-IORto-DDISdelay

Delay from -IOR to data

Data disable time

-IOW delay from chip select

-IOW strobe width

Chip select hold time from -IOW

-IOW delay from address

Write cycle delay

Data setup time

Data hold time

Delay from -IOW to output

Delay to set interrupt from MODEM

input

15

25

10

20

100 pF load

35

25

10

40

0

10

50

20

50

25

15

10

40

0

10

50

15

35

Note 1:

50

35

100 pF load

T_19d

T_20d

T_21d

T_22d

T_23d

Delay to reset interrupt from -IOR

Delay from stop to set interrupt

Delay from -IOR to reset interrupt

Delay from stop to interrupt

Delay from initial INT reset to transmit

start

50

1

200

100

24

35

1

200

100

24

ns

Rclk

ns

Rclk

100 pF load

8

T_24d

T_25d

T_26d

T_27d

T_28d

T_R

Delay from -IOW to reset interrupt

Delay from stop to set -RxRdy

Delay from -IOR to reset -RxRdy

Delay from -IOW to set -TxRdy

Delay from start to reset -TxRdy

Reset pulse width

175

1

175

8

175

1

175

8

ns

Rclk

ns

Rclk

ns

40

1

40

1

N

Baudratedevisor

2¹⁶-1

Rclk

Note 1: Applicable only when -AS is tied low.

Rev. 1.20

37

XR16C850

ABSOLUTE MAXIMUM RATINGS

Supplyrange

7 Volts

GND-0.3 V to VCC+0.3 V

-40° C to +85° C

Voltage at any pin

Operatingtemperature

Storagetemperature

Package dissipation

-65° C to +150° C

500 mW

DC ELECTRICAL CHARACTERISTICS

T_A=0° - 70° C ( -40° - +85° C for IP, IJ, IQ packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.

Symbol

Parameter

Limits

3.3

Limits

5.0

Units

Conditions

Min

Max

Min

Max

V_ILCK

V_IHCK

V_IL

V_IH

V_OL

V_OH

I_IL

I_CL

I_CC

I_SB

C_P

Clock input low level

Clock input high level

Inputlowlevel

-0.3

2.4

-0.3

2.0

0.6

VCC

0.8

-0.5

3.0

-0.5

2.2

0.6

VCC

0.8

VCC

0.4

V

µA

mA

µA

pF

Inputhighlevel

Output low level on all outputs

Outputhighlevel

Inputleakage

I_OL= 5 mA

I_OL= 4 mA

I_OH= -5 mA

I_OH= -1 mA

0.4

2.4

2.0

±10

2.7

30

±10

4

50

5

Clockleakage

Avgpowersupplycurrent

Avg stand by current

Inputcapacitance

see Test 1:

5

Test 1: For low power operation these pins should be left at logic 1 state: S1, S2, A4, A9, BUS8/16, CLK8/16,

CLKSEL, -DMA, -DACK, SEL, TC and RX.

Rev. 1.20

38

XR16C850

T1w

T2w

EXTERNAL

CLOCK

T3w

-BAUDOUT

1/2 -BAUDOUT

1/3 -BAUDOUT

1/3> -BAUDOUT

X450-CK-1

Clock Timing

Rev. 1.20

39

XR16C850

T4w

-AS

T5h

T6h

T5s

Valid

Address

A0-A2

T6s

-CS2

CS1-CS0

Valid

T7d

T7h

T7w

T8d

T9d

-IOR

IOR

Active

T11d

T12h

T11d

Active

-DDIS

D0-D7

T12d

Data

X550-RD-1

General Read timing in "STD mode"

Rev. 1.20

40

XR16C850

T4w

-AS

T5h

T6h

T5s

Valid

Address

A0-A2

T6s

-CS2

CS1-CS0

Valid

T13d

T13h

T16h

T13w

T14d

T15d

-IOW

IOW

Active

T16s

Data

D0-D7

X550-WD-1

General Write timing in "STD mode"

Rev. 1.20

41

XR16C850

Valid

Address

A0-A9

T6s

T7d

Active

-AEN

-IOR

T7w

T7d

T9d

Active

T12s

T12h

D0-D7

Data

X650-RD-2

General Read timing in "PC mode"

Valid

Address

A0-A9

-AEN

-IOW

T6s

Active

T13h

T13d

T13w

T15d

Active

T16s

T16h

Data

D0-D7

X650-WD-2

General Write timing in "PC mode"

Rev. 1.20

42

XR16C850

-IOW

IOW

Active

T17d

Change of state

-RTS

-DTR

Change of state

-CD

-CTS

Change of state

-DSR

T18d

Active

INT

Active

T19d

-IOR

IOR

Active

T18d

Change of state

X450-MD-1

-RI

ModemInput/Outputtiming

Rev. 1.20

43

XR16C850

STOP

BIT

START

BIT

DATA BITS (5-8)

RX

D0

D1

D2

D3

D4

D5

D6 D7

PARITY

BIT

START

BIT

5 DATA BITS

6 DATA BITS

7 DATA BITS

T20d

Active

INT

T21d

-IOR

IOR

16 BAUD RATE CLOCK

X450-RX-1

Receive timing

Rev. 1.20

44

XR16C850

STOP

BIT

START

BIT

DATA BITS (5-8)

RX

D0

D1

D2

D3

D4

D5

D6 D7

PARITY

BIT

START

BIT

T25d

Active

Data

-RXRDY

Ready

T26d

-IOR

IOR

Active

X550-RX-2

Receive Ready timing in non FIFO mode

Rev. 1.20

45

XR16C850

STOP

BIT

START

BIT

DATA BITS (5-8)

RX

D0

D1

D2

D3

D4

D5

D6 D7

PARITY

BIT

First byte

that reaches

the trigger

level

T25d

Active

Data

Ready

-RXRDY

T26d

-IOR

IOR

Active

X550-RX-3

Receive Ready timing in FIFO mode

Rev. 1.20

46

XR16C850

STOP

BIT

START

BIT

DATA BITS (5-8)

TX

D0

D1

D2

D3

D4

D5

D6 D7

PARITY

BIT

START

BIT

5 DATA BITS

6 DATA BITS

7 DATA BITS

T22d

Active

Tx Ready

INT

T24d

T23d

-IOW

IOW

Active

16 BAUD RATE CLOCK

X450-TX-1

Transmittiming

Rev. 1.20

47

XR16C850

STOP

BIT

START

BIT

DATA BITS (5-8)

TX

D0

D1

D2

D3

D4

D5

D6 D7

PARITY

BIT

START

BIT

-IOW

IOW

T28d

BYTE #128

T27d

-TXRDY

FIFO

FULL

X850-TX-2

Transmit Ready timing in non FIFO mode

Rev. 1.20

48

XR16C850

START BIT

DATA BITS (5-8)

STOP BIT

TX

D0

D1

D2

D3

D4

D5

D6 D7

5 DATA BITS

PARITY BIT

6 DATA BITS

7 DATA BITS

-IOW

IOW

Active

T28d

D0-D7

BYTE #128

T27d

-TXRDY

FIFO Full

X850-TX-3

Transmit Ready timing in FIFO mode

Rev. 1.20

49

XR16C850

UART Frame

Data Bits

1

0

TX

IRTX

1/2 Bit Time

Bit Time

3/16 Bit Time

Infraredtransmittiming

IRRX

RX

Bit Time

0-1 16x clock

delay

1

0

Data Bits

UART Frame

X650-IR-1

Infraredreceivetiming

Rev. 1.20

50

XR16C850

Rev. 1.20

51

XR16C850

Rev. 1.20

52

XR16C850

Rev. 1.20

53

XR16C850

Rev. 1.20

54

XR16C850

NOTICE

EXARCorporationreservestherighttomakechangestotheproductscontainedinthispublicationinordertoimprove

design,performanceorreliability.EXARCorporationassumesnoresponsibilityfortheuseofanycircuitsdescribed

herein, conveysnolicenseunderanypatentorotherright, andmakesnorepresentationthatthecircuitsarefreeof

patentinfringement.Chartsandschedulescontainedhereinareonlyforillustrationpurposesandmayvarydepending

upon a user’s specific application. While the information in this publication has been carefully checked; no

responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure

ormalfunctionoftheproductcanreasonablybeexpectedtocausefailureofthelifesupportsystemortosignificantly

affectitssafetyoreffectiveness.ProductsarenotauthorizedforuseinsuchapplicationsunlessEXARCorporation

receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the

user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the

circumstances.

DatasheetJune1999

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

Rev. 1.20

55


型号：	XR16C850CP
厂家：	EXAR CORPORATION
描述：	UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control UART与128字节FIFO的FIFO计数器和半双工控制计数器先进先出芯片
文件：	总55页 (文件大小：331K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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