XR16L2752CJ-F [EXAR]
Serial I/O Controller, 2 Channel(s), 0.78125MBps, CMOS, PQCC44, GREEN, PLASTIC, LCC-44;型号: | XR16L2752CJ-F |
厂家: | EXAR CORPORATION |
描述: | Serial I/O Controller, 2 Channel(s), 0.78125MBps, CMOS, PQCC44, GREEN, PLASTIC, LCC-44 通信 时钟 数据传输 外围集成电路 |
文件: | 总49页 (文件大小:458K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
xr
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
MAY 2005
REV. 1.2.1
FEATURES
GENERAL DESCRIPTION
• 2.25 to 5.5 Volt Operation
• 5 Volt Tolerant Inputs
• Pin-to-pin compatible to Exar’s ST16C2552 and
XR16C2852
1
The XR16L2752 (2752) is a low voltage dual
universal asynchronous receiver and transmitter
(UART) with 5 Volt tolerant inputs. The device
operates from 2.25 to 5.5 Volt supply range and is
pin-to-pin compatible to Exar’s ST16C2552 and
XR16C2852. The 2752 register set is compatible to
the ST16C2552 and the XR16C2852 enhanced
features. It supports the Exar’s enhanced features of
64 bytes of TX and RX FIFOs, programmable FIFO
trigger level and FIFO level counters, automatic
hardware (RTS/CTS) and software flow control,
automatic RS-485 half duplex direction control output
and a complete modem interface. Onboard registers
provide the user with operational status and data
error flags. An internal loopback capability allows
system diagnostics. Independent programmable
baud rate generators are provided in each channel to
select data rates up to 6.25 Mbps at 5 Volt and 8X
sampling. The 2752 is available in the 44-pin PLCC
package.
• Larger FIFO version of PC16C552
• Two independent UART channels
■ Reg set compatible to 16C2552 and 16C2852
■ Up to 6.25 Mbps at 5 Volt, 4 Mbps at 3.3 Volt
and 3 Mbps at 2.5 Volt with 8X sampling rate
■ Transmit and Receive FIFOs of 64 bytes
■ Programmable TX and RX FIFO Trigger Levels
■ Transmit and Receive FIFO Level Counters
■ Automatic Hardware (RTS/CTS) Flow Control
■ Selectable Auto RTS Flow Control Hysteresis
■ Automatic Software (Xon/Xoff) Flow Control
■ Automatic RS-485 Half-duplex Direction
Control Output via RTS#
■ Wireless Infrared (IrDA 1.0) Encoder/Decoder
■ Automatic sleep mode
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,949,787
APPLICATIONS
■ Full modem interface
• Alternate Function Register
• Portable Appliances
• Device Identification and Revision
• Crystal oscillator or external clock input
• Industrial and commercial temperature ranges
• 44-PLCC package
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
FIGURE 1. XR16L2752 BLOCK DIAGRAM
2.25 V to 5.5 V VCC
*5 Volt Tolerant Inputs
(Except External Clock Input)
A2:A0
D7:D0
IOR#
GND
UART Channel A
IOW#
CS#
CHSEL
TXA (or TXIRA)
64 Byte TX FIFO
UART
Regs
IR
ENDEC
TX & RX
INTA
INTB
BRG
64 Byte RX FIFO
RXA (or RXIRA)
8-bit Data
TXRDYA#
Bus
TXRDYB#
TXB (or TXIRB)
RXB (or RXIRB)
UART Channel B
(same as Channel A)
Interface
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
XTAL1
XTAL2
Crystal Osc/Buffer
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
Modem Control Logic
Reset
DTR#A/B, RTS#A/B
2752BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
xr
REV. 1.2.1
FIGURE 2. PIN OUT ASSIGNMENT
7
39 RXA
D5
D6
8
38 TXA
37 DTRA#
36 RTSA#
35 MFA#
34 INTA
D7
9
10
11
12
A0
XTAL1
GND
XR16L2752
44-pin PLCC
VCC
XTAL2 13
A1 14
33
32 TXRDYB#
31 RIB#
A2 15
16
30 CDB#
CHSEL
INTB 17
29 DSRB#
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
DEVICE STATUS
XR16L2752CJ
XR16L2752IJ
44-Lead PLCC
44-Lead PLCC
0°C to +70°C
Active
Active
-40°C to +85°C
2
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
PIN DESCRIPTIONS
Pin Description
44-PLCC
NAME
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
15
14
10
I
Address data lines [2:0]. These 3 address lines select one of the internal registers in
UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
9
8
7
6
5
4
3
2
I/O
Data bus lines [7:0] (bidirectional).
IOR#
24
I
Input/Output Read Strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to
read it on the rising edge.
IOW#
CS#
20
18
16
I
I
I
Input/Output Write Strobe (active low). The falling edge instigates an internal write
cycle and the rising edge transfers the data byte on the data bus to an internal regis-
ter pointed by the address lines.
UART chip select (active low). This function selects channel A or B in accordance
with the logical state of the CHSEL pin. This allows data to be transferred between the
user CPU and the 2752.
CHSEL
Channel Select - UART channel A or B is selected by the logical state of this pin when
the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a
logic 1 selects UART channel A. Normally, CHSEL could just be an address line from
the user CPU such as A4. Bit-0 of the Alternate Function Register (AFR) can tempo-
rarily override CHSEL function, allowing the user to write to both channel register
simultaneously with one write cycle when CS# is low. It is especially useful during the
initialization routine.
INTA
INTB
34
17
1
O
O
O
O
UART channel A Interrupt output (active high). A logic high indicates channel A is
requesting for service. For more details, see Figures 18- 23.
UART channel B Interrupt output (active high). A logic high indicates channel B is
requesting for service. For more details, see Figures 18- 23.
TXRDYA#
TXRDYB#
UART channel A Transmitter Ready (active low). The output provides the TX
FIFO/THR status for transmit channel A. See Table 2.
32
UART channel B Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel B. See Table 2.
MODEM OR SERIAL I/O INTERFACE
TXA 38
O
UART channel A Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be
HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
Pin Description
44-PLCC
NAME
TYPE
DESCRIPTION
PIN #
RXA
39
I
UART channel A Receive Data or infrared receive data. Normal receive data input
must idle HIGH. The infrared receiver pulses typically idles LOW but can be inverted
by software control prior going in to the decoder, see MCR[6] and FCTR[2]. If this pin
is not used, tie it to VCC or pull it high via a 100k ohm resistor.
RTSA#
CTSA#
36
40
O
I
UART channel A Request-to-Send (active low) or general purpose output. This output
must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see
FCTR[3] and EMSR[3].
UART channel A Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to
VCC when not used.
DTRA#
DSRA#
CDA#
37
41
42
O
I
UART channel A Data-Terminal-Ready (active low) or general purpose output. If this
pin is not used, leave it unconnected.
UART channel A Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
I
UART channel A Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
RIA#
43
35
I
UART channel A Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
MFA#
O
Multi-Function Output Channel A. This output pin can function as the OP2A#, BAUD-
OUTA#, or RXRDYA# pin. One of these output signal functions can be selected by
the user programmable bits 1-2 of the Alternate Function Register (AFR). These sig-
nal functions are described as follows:
1) OP2A# - When OP2A# (active low) is selected, the MF# pin is LOW when MCR bit-
3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 0 condition after a
reset or power-up.
2) BAUDOUTA# - When BAUDOUTA# function is selected, the 16X Baud rate clock
output is available at this pin.
3) RXRDYA# - RXRDYA# (active low) is intended for monitoring DMA data transfers.
See Table 2 for more details.
TXB
26
O
UART channel B Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be
HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.
RXB
25
23
I
UART channel B Receive Data or infrared receive data. Normal receive data input
must idle HIGH. The infrared receiver pulses typically idles LOW but can be inverted
by software control prior going in to the decoder, see MCR[6] and FCTR[2]. If this pin
is not used, tie it to VCC or pull it high via a 100k ohm resistor.
RTSB#
O
UART channel B Request-to-Send (active low) or general purpose output. This port
must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see
FCTR[3] and EMSR[3].
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
Pin Description
44-PLCC
NAME
TYPE
DESCRIPTION
PIN #
CTSB#
28
I
UART channel B Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to
VCC when not used.
DTRB#
DSRB#
CDB#
27
29
30
O
I
UART channel B Data-Terminal-Ready (active low) or general purpose output. If this
pin is not used, leave it unconnected.
UART channel B Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
I
UART channel B Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
RIB#
31
19
I
UART channel B Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
MFB#
O
Multi-Function Output Channel B. This output pin can function as the OP2B#, BAUD-
OUTB#, or RXRDYB# pin. One of these output signal functions can be selected by
the user programmable bits 1-2 of the Alternate Function Register (AFR). These sig-
nal functions are described as follows:
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is LOW when MCR bit-
3 is set HIGH (see MCR bit-3). MCR bit-3 defaults to a logic 0 condition after a reset
or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud rate clock
output is available at this pin.
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data transfers.
See Table 2 for more details.
ANCILLARY SIGNALS
XTAL1
XTAL2
RESET
11
13
21
I
O
I
Crystal or external clock input. Caution: this input is not 5V tolerant.
Crystal or buffered clock output.
Reset (active high) - A longer than 40 ns HIGH pulse on this pin will reset the internal
registers and all outputs. The UART transmitter output will be held HIGH, the receiver
input will be ignored and outputs are reset during reset period (see External Reset
Conditions).
VCC
GND
44, 33
22, 12
Pwr 2.25 to 5.5V power supply. All input pins, except XTAL1, are 5V tolerant.
Pwr Power supply common, ground.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
1.0 PRODUCT DESCRIPTION
The XR16L2752 (2752) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has 64-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware
flow control with hysteresis control, automatic Xon/Xoff and special character software flow control,
programmable transmit and receive FIFO trigger levels, FIFO level counters, infrared encoder and decoder
(IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 6.25
Mbps with 8X sampling clock rate or 3.125 Mbps in the 16X rate. The XR16L2752 is a 2.25 to 5.5V device with
5 volt tolerant inputs. The 2752 is fabricated with an advanced CMOS process.
Enhanced Features
The 2752 DUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of
128 bytes provided in the XR16C2852 and 16 bytes in the ST16C2552. The 2752 is designed to work with low
supply voltage and high performance data communication systems, that require fast data processing time.
Increased performance is realized in the 2752 by the larger transmit and receive FIFOs, FIFO trigger level
control, FIFO level counters and automatic flow control mechanism. This allows the external processor to
handle more networking tasks within a given time. For example, the ST16C2552 with a 16 byte FIFO, unloads
16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at
115.2 Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However
with the 64 byte FIFO in the 2752, the data buffer will not require unloading/loading for 6.1 ms. This increases
the service interval giving the external CPU additional time for other applications and reducing the overall
UART interrupt servicing time. In addition, the programmable FIFO level trigger interrupt and automatic
hardware/software flow control is uniquely provided for maximum data throughput performance especially
when operating in a multi-channel system. The combination of the above greatly reduces the CPU’s bandwidth
requirement, increases performance, and reduces power consumption.
The 2752 supports a half-duplex output direction control signaling pin, RTS# A/B, to enable and disable the
external RS-485 transceiver operation. It automatically switches the logic state of the output pin to the receive
state after the last stop-bit of the last character has been shifted out of the transmitter. After receiving, the logic
state of the output pin switches back to the transmit state when a data byte is loaded in the transmitter. The
auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has
to set FCTR Bit-3 to “1”. This pin is normally high for receive state, low for transmit state.
Data Rate
The 2752 is capable of operation up to 3.125 Mbps at 5V with 16X internal sampling clock rate, and 6.25 Mbps
at 5V with 8X sampling clock rate. The device can operate with an external 24 MHz crystal on pins XTAL1 and
XTAL2, or external clock source of up to 50 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and
through a software option, the user can set the prescaler bit for data rates of up to 1.84 Mbps.
The rich feature set of the 2752 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, selectable TX and RX baud rates, infrared
encoder/decoder interface, modem interface controls, and a sleep mode are all standard features.
Following a power on reset or an external reset, the 2752 is software compatible with previous generation of
UARTs 16C2552 and 16C2852.
6
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 2752 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in Figure 3
FIGURE 3. XR16L2750 DATA BUS INTERCONNECTIONS
VC C
VC C
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
TXA
R XA
D TR A#
R TSA#
C TSA#
U AR T
C hannel A
Serial Interface of
R S-232, R S-485
D SR A#
C D A#
A0
A1
A2
A0
A1
A2
R IA#
(O P2A#)
IO R #
IO R #
(BAU D O U TA#)
IO W #
IO W #
TXB
R XB
C S#
U AR T_C S#
C H SEL
U AR T_C H SEL
D TR B#
U AR T_IN TA
U AR T_IN TB
IN TA
IN TB
R TSB#
C TSB#
D SR B#
CD B#
U AR T
C hannel B
Serial Interface of
R S-232, R S-485
TXR D YA#
(RXR D YA#)
TXR D YB#
TXR D YA#
(R XR DYA#)
TXR D YB#
(R XR DYB#)
R IB#
(O P2B#)
(RXR D YB#)
(BAU D O U TB#)
U AR T_R ESET
R ESET
G N D
2750int
Pins in parentheses become available through the M F# pin. M F# A/B becomes R XR DY# A/B when AFR [2:1] = '10'. M F# A/B becomes O P2 # A/B
when AFR [2:1] = '00'. M F# A/B becom es BAU DO U T# A/B when AFR [1:0] = '01'.
2.2
5-Volt Tolerant Inputs
The 2752 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the 2752 is
operating at 2.5V, its V may not be high enough to meet the requirements of the V of a CPU or a serial
OH
IH
transceiver that is operating at 5V. Caution: XTAL1 is not 5 volt tolerant.
2.3 Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device.
2.4
Device Identification and Revision
The XR16L2752 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x0A for the
XR16L2752 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01
means revision A.
2.5
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pin (CS#) allows the user to select
the UART and then using the channel select (CHSEL) pin, the user can select channel A or B to configure,
send transmit data and/or unload receive data to/from the UART. Individual channel select functions are shown
in Table 1.
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
TABLE 1: CHANNEL A AND B SELECT
CS#
CHSEL
FUNCTION
1
0
0
X
1
0
UART de-selected
Channel A selected
Channel B selected
2.6
Channel A and B Internal Registers
Each UART channel in the 2752 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM), and a user accessible Scratchpad Register (SPR).
Beyond the general 16C2550 features and capabilities, the 2752 offers enhanced feature registers (AFR,
EMSR, FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware
flow control, Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable,
FIFO trigger level control, FIFO level counters, and simultaneous writes to both channels. All the register
functions are discussed in full detail later in “Section 3.0, UART INTERNAL REGISTERS” on page 20.
2.7
Simultaneous Write to Channel A and B
During a write mode cycle, the setting of Alternate Function Register (AFR) bit-0 to a logic 1 will override the
CHSEL selection and allows a simultaneous write to both UART channel sections. This functional capability
allow the registers in both UART channels to be modified concurrently, saving individual channel initialization
time. Caution should be considered, however, when using this capability. Any in-process serial data transfer
may be disrupted by changing an active channel’s mode.
2.8
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B (MF# A/B becomes RXRDY# A/B output when AFR[2:1] = ‘10’) and TXRDY# A/B output
pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode
operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for
more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1).
When the transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the 2752 is
placed in single-character mode for data transmit or receive operation. When DMA mode is enabled (FCR bit-
3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO in a block
sequence determined by the programmed trigger level. In this mode, the 2752 sets the TXRDY# pin when the
transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO becomes empty. The following
table shows their behavior. Also see Figures 18 through 23.
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
FCR BIT-0=0
PINS
FCR BIT-0=1 (FIFO ENABLED)
(FIFO DISABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY# A/B LOW = 1 byte.
HIGH = no data.
LOW = at least 1 byte in FIFO. HIGH to LOW transition when FIFO reaches the
trigger level, or time-out occurs.
HIGH = FIFO empty.
LOW to HIGH transition when FIFO empties.
TXRDY# A/B LOW = THR empty. LOW = FIFO empty.
LOW = FIFO has at least 1 empty location.
HIGH = byte in THR. HIGH = at least 1 byte in FIFO. HIGH = FIFO is full.
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2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
2.9
INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see Figures 18
through 23.
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER
Auto RS485
Mode
FCR BIT-0 = 0
FCR BIT-0 = 1 (FIFO ENABLED)
LOW = FIFO above trigger level
(FIFO DISABLED)
INTA/B Pin
INTA/B Pin
NO
LOW = a byte in THR
HIGH = THR empty
HIGH = FIFO below trigger level or FIFO empty
YES
LOW = a byte in THR
LOW = FIFO above trigger level
HIGH = transmitter empty
HIGH = FIFO below trigger level or transmitter empty
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
FCR BIT-0 = 1
(FIFO DISABLED)
(FIFO ENABLED)
INTA/B Pin
LOW = no data
HIGH = 1 byte
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
2.10 Crystal Oscillator or External Clock Input
The 2752 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
“Programmable Baud Rate Generator.”
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R1
0-120 Ω
(Optional)
R2
500 KΩ − 1 MΩ
1.8432 MHz
to
Y1
24 MHz
C1
C2
22-47 pF
22-47 pF
9
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
xr
REV. 1.2.1
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4). The programmable Baud
Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. However, with an
external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2 pin (as shown in Figure 5) it can
extend its operation up to 50 MHz (6.25 Mbps serial data rate) and 5V with an 8X sampling rate.
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
External Clock
vcc
XTAL1
gnd
VCC
R1
2K
XTAL2
For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR web site at
http://www.exar.com.
2.11 Programmable Baud Rate Generator
Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a
software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external
clock by 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a
16
programmable divisor between 1 and (2 -1) to obtain a 16X sampling rate clock of the serial data rate. The
sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG
divisor defaults to the maximum baud rate (DLL = 0x01 and DLM = 0x00) upon power up.
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER
DLL and DLM
Registers
MCR Bit-7=0
(default)
Prescaler
Divide by 1
16X
Crystal
Osc/
Buffer
XTAL1
XTAL2
Sampling
Rate Clock to
Transmitter
Baud Rate
Generator
Logic
Prescaler
Divide by 4
MCR Bit-7=1
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate. Table 5 shows the standard data rates available with a 14.7456 MHz crystal or external
clock at 16X sampling rate clock rate. A 16X sampling clock is typically used. However, user can select the 8X
sampling clock rate mode (EMSR bit-7=0) to double the operating data rate. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation.
10
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16XMode [EMSR bit-7] = 1
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8), with 16XMode [EMSR bit-7] = 0
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate OUTPUT Data Rate
DLM
PROGRAM
VALUE (HEX) VALUE (HEX)
DLL
PROGRAM
DATA RATE
ERROR (%)
DIVISOR FOR 16x DIVISOR FOR 16x
Clock (Decimal) Clock (HEX)
MCR Bit-7=1
MCR Bit-7=0
(DEFAULT)
100
600
400
2304
384
192
96
48
24
12
6
900
180
C0
60
09
01
00
00
00
00
00
00
00
00
00
00
80
C0
60
30
18
0C
06
04
02
01
0
0
0
0
0
0
0
0
0
0
0
2400
1200
2400
4800
9600
19.2k
38.4k
57.6k
115.2k
230.4k
4800
9600
19.2k
38.4k
76.8k
153.6k
230.4k
460.8k
921.6k
30
18
0C
06
4
04
2
02
1
01
2.12 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods (see EMSR bit-7). The transmitter sends the start-bit followed by the
number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and
TSR are reported in the Line Status Register (LSR bit-5 and bit-6).
2.12.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.12.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
11
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2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
Transmit
Holding
Register
(THR)
Data
Byte
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X or 8X Clock
(EMSR bit-7)
M
S
B
L
S
B
Transmit Shift Register (TSR)
TXNOFIFO1
2.12.3 Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
FIFO
Transmit
Data Byte
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
Auto CTS Flow Control (CTS# pin)
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
Auto Software Flow Control
16X or 8X Clock
(EMSR bit-7 = 1)
Transmit Data Shift Register
(TSR)
TXFIFO1
2.13 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X for timing. It verifies and validates every bit
on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an
internal receiver counter starts counting at the 16X. After 8 clocks the start bit period should be at the center of
the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer
is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register.
RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO
trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt
12
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2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
when data is not received for 4 word lengths as defined by LCR[1,0] plus 12 bits time. This is equivalent to 3.7-
4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.13.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
16X or 8X Clock
(EMSR bit-7)
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Error
Receive
Data Byte
and Errors
Receive Data
Holding Register
(RHR)
Tags in
LSR bits
4:2
RHR Interrupt (ISR bit-2)
RXFIFO1
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X or 8X Clock
(EMSR bit-7)
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Example
- RX FIFO trigger level selected at 16
:
bytes
(See Note Below)
64 bytes by 11-bit
wide
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
FIFO
Data falls to 8
Receive
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
Data FIFO
FIFO Trigger=16
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
Data fills to 24
Receive
Data
Receive Data
Byte and Errors
RXFIFO1
NOTE: Table-B selected as Trigger Table for Figure 10 (Table 10).
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
2.14 Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 11):
• Enable auto RTS flow control using EFR bit-6.
• The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
• Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.15
Auto RTS Hysteresis
The 2752 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with
the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt
is generated when the receive FIFO reaches the programmed RX trigger level. The RTS# pin will not be forced
HIGH (RTS off), until the receive FIFO reaches the upper limit of the hysteresis level. The RTS# pin will return
LOW after the RX FIFO is unloaded to the lower limit of the hysteresis level. Under the above described
conditions, the 2752 will continue to accept data until the receive FIFO gets full. The Auto RTS function is
initiated when the RTS# output pin is asserted LOW (RTS On). Table 13 shows the complete details for the
Auto RTS# Hysteresis levels. Please note that this table is for programmable trigger levels only (Table D). The
hysteresis values for Tables A-C are the next higher and next lower trigger levels in Tables A-C.
2.16
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 11):
• Enable auto CTS flow control using EFR bit-7.
If using the Auto CTS interrupt:
• Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as
the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-
asserted (LOW), indicating more data may be sent.
14
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION
Local UART
UARTA
Remote UART
UARTB
RXA
TXB
Receiver FIFO
Trigger Reached
Transmitter
RTSA#
TXA
CTSB#
Auto RTS
Trigger Level
Auto CTS
Monitor
RXB
Receiver FIFO
Trigger Reached
Transmitter
CTSA#
RTSB#
Auto CTS
Monitor
Auto RTS
Trigger Level
Assert RTS# to Begin
Transmission
1
10
11
ON
ON
ON
RTSA#
OFF
OFF
7
2
ON
3
CTSB#
TXB
8
Restart
9
Data Starts
6
Suspend
4
RXA FIFO
Receive
Data
RX FIFO
12
RTS High
Threshold
RTS Low
Threshold
5
RX FIFO
Trigger Level
Trigger Level
INTA
(RXA FIFO
Interrupt)
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
15
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
2.17 Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 15), the 2752 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the 2752 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the 2752 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the 2752 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters (See Table 15) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are
selected, the 2752 compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control
mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the 2752 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 2752 sends the
Xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate)
after the receive FIFO crosses the programmed trigger level (for all trigger tables A-D). To clear this condition,
the 2752 will transmit the programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger
level below the programmed trigger level (for Trigger Tables A, B, and C) or when receive FIFO is less than the
trigger level minus the hysteresis value (for Trigger Table D). This hysteresis value is the same as the Auto
RTS Hysteresis value in Table 13. Table 6 below explains this when Trigger Table-B (See Table 10) is selected.
TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
XOFF CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
XON CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
RX TRIGGER LEVEL
INT PIN ACTIVATION
8
8
8*
0
8
16
24
28
16
24
28
16*
24*
28*
16
24
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2
characters); for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.
2.18
Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The 2752 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will
be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal
Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff
Registers corresponds with the LSB bit for the receive character.
2.19
Auto RS485 Half-duplex Control
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit-3. By default, it de-asserts RTS# (HIGH) output following the last stop bit of the last character that has been
transmitted. This helps in turning around the transceiver to receive the remote station’s response. When the
host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit FIFO. The
transmitter automatically re-asserts RTS# (LOW) output prior to sending the data. The RS485 half-duplex
direction control output can be inverted by enabling EMSR bit-3.
16
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
2.20 Infrared Mode
The 2752 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGH-
pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See Figure 12 below.
The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. When the infrared feature
is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level
of logic zero from a reset and power up, see Figure 12.
Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream. However, this is not true with some
infrared modules on the market which indicate a logic 0 by a light pulse. So the 2752 has a provision to invert
the input polarity to accommodate this. In this case user can enable FCTR bit-2 to invert the input signal.
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
Character
Data Bits
1
1
1
1
1
0
0
0
0
0
TX Data
Transmit
IR Pulse
(TX Pin)
1/2 Bit Time
Bit Time
3/16 Bit Time
IrEncoder-1
Receive
IR Pulse
(RX pin)
Bit Time
1/16 Clock Delay
1
1
1 1
1
0
0
0
0
0
RX Data
Data Bits
Character
IRdecoder-
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
2.21
Sleep Mode with Auto Wake-Up
The 2752 supports low voltage system designs, hence, a sleep mode is included to reduce its power
consumption when the chip is not actively used.
All of these conditions must be satisfied for the 2752 to enter sleep mode:
■ no interrupts pending for both channels of the 2752 (ISR bit-0 = 1)
■ sleep mode of both channels are enabled (IER bit-4 = 1)
■ modem inputs are not toggling (MSR bits 0-3 = 0)
■ RX input pins are idling HIGH
The 2752 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for
no clock output as an indication that the device has entered the sleep mode.
The 2752 resumes normal operation by any of the following:
■ a receive data start bit transition (HIGH to LOW)
■ a data byte is loaded to the transmitter, THR or FIFO
■ a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the 2752 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the 2752 is awakened by the modem inputs, a
read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while
an interrupt is pending from channel A or B. The 2752 will stay in the sleep mode of operation until it is disabled
by setting IER bit-4 to a logic 0.
If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and modem input lines remain steady when the
2752 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical
Characteristics on page 39. If the input lines are floating or are toggling while the 2752 is in sleep mode, the
current can be up to 100 times more. If any of those signals are toggling or floating, then an external buffer
would be required to keep the address, data and control lines steady to achieve the low current. As an
alternative, please refer to the XR16L2751 with the PowerSave feature that eliminates any unnecessary
external buffer.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. The number of characters lost during the restart also depends on your
operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep
RX A/B inputs idling HIGH or “marking” condition during sleep mode to avoid receiving a “break” condition
upon the restart. This may occur when the external interface transceivers (RS-232, RS-485 or another type)
are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a
47k-100k ohm pull-up resistor on the RXA and RXB pins.
18
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2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
2.22
Internal Loopback
The 2752 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#,
DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else
upon exiting the loopback test the UART may detect and report a false “break” signal. Also, Auto RTS/CTS
hardware flow control is not supported during internal loopback.
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B
VCC
TXA/TXB
Transmit Shift Register
(THR/FIFO)
MCR bit-4=1
Receive Shift Register
(RHR/FIFO)
RXA/RXB
VCC
RTSA#/RTSB#
RTS#
CTS#
CTSA#/CTSB#
VCC
DTRA#/DTRB#
DTR#
DSR#
DSRA#/DSRB#
OP1#
RI#
RIA#/RIB#
VCC
(OP2A#/OP2B#)
OP2#
CD#
CDA#/CDB#
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2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
3.0 UART INTERNAL REGISTERS
Each of the UART channel in the 2752 has its own set of configuration registers selected by address lines A0,
A1 and A2 with CS# and CHSEL selecting the channel. The complete register set is shown in Table 7 and
Table 8.
TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS
ADDRESSES
REGISTER
READ/WRITE
COMMENTS
A2 A1 A0
16C550 COMPATIBLE REGISTERS
0
0 0
RHR - Receive Holding Register
Read-only
Write-only
LCR[7] = 0
THR - Transmit Holding Register
0
0 0
0 1
1 0
0 0
0 1
0 1
1 0
DLL - Div Latch Low Byte
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Read/Write
0
0
0
0
0
0
DLM - Div Latch High Byte
LCR[7] = 1, LCR ≠ 0xBF
AFR - Alternate Function Register
DREV - Device Revision Code
DVID - Device Identification Code
IER - Interrupt Enable Register
DLL, DLM = 0x00,
LCR[7] = 1, LCR ≠ 0xBF
LCR[7] = 0
LCR[7] = 0
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
0
1
1
1 1
0 0
0 1
LCR - Line Control Register
Read/Write
Read/Write
MCR - Modem Control Register
LSR - Line Status Register
Reserved
Read-only
Write-only
LCR ≠ 0xBF
1
1 0
MSR - Modem Status Register
Reserved
Read-only
Write-only
1
1
1
1 1
1 1
1 1
SPR - Scratch Pad Register
Read/Write
Read-only
Write-only
LCR ≠ 0xBF, FCTR[6] = 0
LCR ≠ 0xBF, FCTR[6] = 1
FLVL - RX/TX FIFO Level Counter Register
EMSR - Enhanced Mode Select Register
ENHANCED REGISTERS
0
0 0
TRG -RX/TX FIFO Trigger Level Register
FC - RX/TX FIFO Level Counter Register
Write-only
Read-only
0
0
1
1
1
1
0 1
1 0
0 0
0 1
1 0
1 1
FCTR - Feature Control Register
EFR - Enhanced Function Register
Xon-1 - Xon Character 1
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
LCR = 0xBF
Xon-2 - Xon Character 2
Xoff-1 - Xoff Character 1
Xoff-2 - Xoff Character 2
20
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2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
.
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
REG
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
A2-A0
NAME
16C550 Compatible Registers
0 0 0
0 0 0
0 0 1
RHR
THR
RD
Bit-7
Bit-7
0/
Bit-6
Bit-6
0/
Bit-5
Bit-5
0/
Bit-4
Bit-4
0/
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
WR
IER RD/WR
Modem RXLine
Stat.
Int.
TX
Empty
Int
RX
Data
Int.
Stat.
Int.
CTS Int. RTS Int. Xoff Int.
Enable Enable Enable
Sleep
Mode
Enable
Enable Enable Enable Enable
0 1 0
ISR
RD
FIFOs
Enabled Enabled
FIFOs
0/
0/
INT
INT
INT
INT
LCR[7] = 0
Source Source Source Source
Bit-3
INT
INT
Bit-2
Bit-1
Bit-0
Source Source
Bit-5
Bit-4
0 1 0
FCR
WR RXFIFO RXFIFO
Trigger Trigger
0/
0/
DMA
Mode
TX
FIFO
RX
FIFOs
FIFO Enable
TXFIFO TXFIFO
Trigger Trigger
Enable Reset Reset
0 1 1
1 0 0
LCR RD/WR Divisor Set TX Set Par-
Even
Parity Enable
Parity
Stop
Bits
Word
Length Length
Bit-1 Bit-0
Word
Enable
Break
ity
MCR RD/WR
0/
0/
0/
Internal OP2# Rsrvd RTS# DTR#
Lopback Output
Enable Control
Output Output
Control Control
(OP1#)
BRG
Pres-
caler
IR Mode XonAny
ENable
LCR ≠ 0xBF
1 0 1
LSR
RD
RD
RX FIFO THR &
THR
Empty
RX
Break
RX
RX
RX
RX
Data
Ready
Global
Error
TSR
Empty
Fram- Parity Over-
ing
Error
Error
run
Error
1 1 0
1 1 1
MSR
CD#
RI#
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR# CTS#
Delta
Input
Input
SPR RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1 Bit-0
LCR ≠ 0xBF
FCTR bit-6=0
1 1 1
EMSR
FLVL
WR
RD
16X
LSR
Error
Inter-
rupt.
Imd/Dly#
Auto
Auto
Auto
RS485
Output
Inver-
sion
Rsrvd Rx/Tx Rx/Tx
FIFO FIFO
Count Count
Sam-
pling
Rate
RTS
Hyst.
RTS
Hyst.
LCR ≠ 0xBF
FCTR bit-6=1
bit-3
bit-2
Mode
1 1 1
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
21
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2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
REG
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
A2-A0
NAME
Baud Rate Generator Divisor
0 0 0
0 0 1
0 1 0
DLL RD/WR
DLM RD/WR
Bit-7
Bit-7
Bit-6
Bit-6
Rsvd
Bit-5
Bit-5
Rsvd
Bit-4
Bit-4
Rsvd
Bit-3
Bit-3
Rsvd
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
LCR[7] = 1
LCR ≠ 0xBF
RXRDY# Baudout# Concur-
AFR RD/WR Rsvd
Select
Bit-2
0
Select
Bit-1
1
rent Write
Bit-0
0
0 0 0
0 0 1
DREV
DVID
RD
RD
Bit-7
0
Bit-6
0
Bit-5
0
Bit-4
0
Bit-3
1
LCR[7] = 1
LCR ≠ 0xBF
DLL=0x00
DLM=0x00
Enhanced Registers
0 0 0
0 0 0
0 0 1
TRG
FC
WR
RD
Bit-7
Bit-7
Bit-6
Bit-6
Bit-5
Bit-5
Bit-4
Bit-4
Bit-3
Bit-3
Auto
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
FCTR RD/WR RX/TX SCPAD
Trig
Table
Bit-1
Trig
Table
Bit-0
RX IR
Input
Inv.
Auto
RTS
Hyst
Bit-1
Auto
RTS
Hyst
Bit-0
Mode
Swap
RS485
Direc-
tion
Control
Enable
0 1 0
EFR RD/WR
Auto
CTS
Enable Enable
Auto
RTS
Special
Char
Select
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
Cntl
LCR=0XBF
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
1 0 0
1 0 1
1 1 0
1 1 1
XON1 RD/WR
XON2 RD/WR
XOFF1 RD/WR
XOFF2 RD/WR
Bit-7
Bit-7
Bit-7
Bit-7
Bit-6
Bit-6
Bit-6
Bit-6
Bit-5
Bit-5
Bit-5
Bit-5
Bit-4
Bit-4
Bit-4
Bit-4
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
See “Receiver” on page 12.
4.2
Transmit Holding Register (THR) - Write-Only
See “Transmitter” on page 11.
4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
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2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
4.3.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
4.3.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L2752 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-
FIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is
empty when this bit is enabled, an interrupt will be generated.
• Logic 0 = Disable Transmit Ready interrupt (default).
• Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bits 1-4 generate an interrupt immediately when
the character has been received.
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
• Logic 0 = Disable Sleep Mode (default).
• Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
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REV. 1.2.1
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
• Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the RTS# interrupt (default).
• Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the CTS# interrupt (default).
• Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
4.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 9, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1
Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by a 4-char plus 12 bits delay timer.
• TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).
• MSR is by any of the MSR bits 0, 1, 2 and 3.
• Receive Xoff/Special character is by detection of a Xoff or Special character.
• CTS# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.
• RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.
4.4.2
Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register.
• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by reading RHR.
• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
• MSR interrupt is cleared by a read to the MSR register.
• Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
• Special character interrupt is cleared by a read to ISR or after the next character is received.
• RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
24
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2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
]
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
2
3
4
5
6
7
-
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
RXRDY (Received Xoff or Special character)
CTS#, RTS# change of state
None (default)
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 9).
ISR[5:4]: Interrupt Status
These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data
match of the Xoff character(s). Note that once set to a logic 1, the ISR bit-4 will stay a logic 1 until a Xon
character is received. ISR bit-5 indicates that CTS# or RTS# has changed state.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
• Logic 0 = Disable the transmit and receive FIFO (default).
• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No receive FIFO reset (default)
• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
25
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No transmit FIFO reset (default).
• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
• Logic 0 = Normal Operation (default).
• Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 10 below shows the selections. EFR bit-4
must be set to ‘1’ before these bits can be accessed. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 5-4 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receive
FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the
trigger level. Table 10 shows the complete selections. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
26
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
TRANSMIT
TRIGGER
LEVEL
TRIGGER FCTR FCTR
FCR
BIT-7
FCR
BIT-6
FCR
BIT-5
FCR
BIT-4
RECEIVE
TRIGGER LEVEL
COMPATIBILITY
TABLE
BIT-5
BIT-4
Table-A
0
0
0
0
1 (default)
16C550, 16C2550,
16C2552, 16C554,
16C580
0
0
1
1
0
1
0
1
1 (default)
4
8
14
Table-B
Table-C
Table-D
0
1
1
1
0
1
0
0
1
1
0
1
0
1
16
8
16C650A
24
30
0
0
1
1
0
1
0
1
8
16
24
28
0
0
1
1
0
1
0
1
8
16C654
16
32
56
0
0
1
1
0
1
0
1
8
16
56
60
X
X
X
X
Programmable Programmable 16L2752, 16C2850,
16C2852, 16C850,
16C854, 16C864
via TRG
via TRG
register.
register.
FCTR[7] = 0.
FCTR[7] = 1.
4.6
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
1
1
0
1
0
1
5 (default)
6
7
8
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
STOP BIT LENGTH
(BIT TIME(S))
WORD
LENGTH
BIT-2
0
1
1
5,6,7,8
5
1 (default)
1-1/2
2
6,7,8
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 11 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
• LCR BIT-5 = logic 0, parity is not forced (default).
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
TABLE 11: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
No parity
X
0
0
1
X
0
1
0
0
1
1
1
Odd parity
Even parity
Force parity to mark,
“1”
1
1
1
Forced parity to
space, “0”
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2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space”, LOW state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
• Logic 0 = No TX break condition (default).
• Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
• Logic 0 = Data registers are selected (default).
• Logic 1 = Divisor latch registers are selected.
4.7
Alternate Function Register (AFR) - Read/Write
This register is used to select specific modes of MF# operation and to allow both UART register sets to be
written concurrently.
AFR[0]: Concurrent Write Mode
When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is
intended to reduce the dual UART initialization time. It can be used by the CPU when both channels are
initialized to the same state. The external CPU can set or clear this bit by accessing either register set. When
this bit is set, the channel select pin still selects the channel to be accessed during read operations. The user
should ensure that LCR Bit-7 of both channels are in the same state before executing a concurrent write to the
registers at address 0, 1, or 2.
• Logic 0 = No concurrent write (default).
• Logic 1 = Register set A and B are written concurrently with a single external CPU I/O write operation.
AFR[2:1]: MF# Output Select
These bits select a signal function for output on the MF# A/B pins. These signal function are described as:
OP2#, BAUDOUT#, or RXRDY#. Only one signal function can be selected at a time.
BIT-2
BIT-1
MF# FUNCTION
0
0
1
1
0
1
0
1
OP2# (default)
BAUDOUT#
RXRDY#
Reserved
AFR[7:3]: Reserved
All are initialized to logic 0.
4.8
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force DTR# output HIGH (default).
• Logic 1 = Force DTR# output LOW.
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2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
• Logic 0 = Force RTS# output HIGH (default).
• Logic 1 = Force RTS# output LOW.
MCR[2]: Reserved
OP1# is not available as an output pin on the 2752. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
MCR[3]: OP2# Output / INT Output Enable
OP2# is available as an output pin on the 2752 when AFR[2:1] = ‘00’. In the Loopback Mode, MCR[3] is used
to write the state of the modem CD# interface signal. Also see pin descriptions for MF# pins.
• Logic 0 = Forces OP2# output HIGH (default).
• Logic 1 = Forces OP2# output LOW.
MCR[4]: Internal Loopback Enable
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 13.
MCR[5]: Xon-Any Enable
• Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
• Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the 2752 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable
• Logic 0 = Enable the standard modem receive and transmit input/output interface (default).
• Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. While in this mode, the infrared TX output will be a logic 0 during idle data conditions.
MCR[7]: Clock Prescaler Select
• Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
• Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
4.9
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or FIFO (default).
• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Flag
• Logic 0 = No overrun error. (default)
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
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REV. 1.2.1
LSR[2]: Receive Data Parity Error Flag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Flag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[4]: Receive Break Flag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte
is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0
concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set
when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
• Logic 0 = No FIFO error (default).
• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.
4.10 Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem
changes state. These bits may be used as general purpose inputs when they are not used with modem
signals.
MSR[0]: Delta CTS# Input Flag
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
• Logic 0 = No change on DSR# input (default).
• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
• Logic 0 = No change on RI# input (default).
• Logic 1 = The RI# input has changed from a LOW to HIGH, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
MSR[3]: Delta CD# Input Flag
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has
finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of
the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The
CTS# input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is
not used.
MSR[6]: RI Input Status
Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
4.11 Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.12 Enhanced Mode Select Register (EMSR)
This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Count (Write-Only)
When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is
operating in.
TABLE 12: SCRATCHPAD SWAP SELECTION
FCTR[6] EMSR[1] EMSR[0] Scratchpad is
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Scratchpad
RX FIFO Counter Mode
TX FIFO Counter Mode
RX FIFO Counter Mode
Alternate RX/TX FIFO
Counter Mode
During Alternate RX/TX FIFO Counter Mode, the first value read after EMSR bits 1-0 have been asserted will
always be the RX FIFO Counter. The second value read will correspond with the TX FIFO Counter. The next
value will be the RX FIFO Counter again, then the TX FIFO Counter and so on and so forth.
EMSR[2]: Reserved
EMSR[3]: Automatic RS485 Half-Duplex Control Output Inversion
• Logic 0 = RTS# output is a logic 0 during TX and a logic 1 during RX (default, compatible with 16C2850).
• Logic 1 = RTS# output is a logic 1 during TX and a logic 0 during RX.
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2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
EMSR[5:4]: Extended RTS Hysteresis
TABLE 13: RTS Hysteresis Levels
EMSR
BIT-5
EMSR
BIT-4
FCTR
BIT-1
FCTR
BIT-0
RTS# HYSTERESIS
(CHARACTERS)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
±4
±6
±8
±8
±16
±24
±32
±40
±44
±48
±52
±12
±20
±28
±36
EMSR[6]: LSR Interrupt Mode
• Logic 0 = LSR Interrupt Delayed (for 16C2550 compatibility, default). LSR bits 2, 3, and 4 will generate an
interrupt when the character with the error is in the RHR.
• Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is
received into the FIFO.
EMSR[7]: 16X Sampling Rate Mode
Logic 0 = 8X Sampling Rate.
Logic 1 = 16X Sampling Rate (for 16C2550 compatibility, default).
4.13 FIFO Level Register (FLVL) - Read-Only
The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this is
not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].
See Table 12 for details.
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
4.14 Baud Rate Generator Registers (DLL and DLM) - Read/Write
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
• Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.15 Device Identification Register (DVID) - Read Only
This register contains the device ID (0x0A for XR16C2752). Prior to reading this register, DLL and DLM should
be set to 0x00.
4.16 Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
4.17 Trigger Level Register (TRG) - Write-Only
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
4.18 RX/TX FIFO Level Count Register (FC) - Read-Only
This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count
Register which is located in the general register set when FCTR bit-6 = 1 (Scratchpad Register Swap). It is
suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit-6 = 1.
See Table 12.
FC[7:0]: RX/TX FIFO Level Count
Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter
FIFO (FCTR[7] = 1) can be read via this register.
4.19 Feature Control Register (FCTR) - Read/Write
This register controls the XR16L2752 new functions.
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to
“0” to select the next trigger level for hardware flow control. See Table 13 for more details.
FCTR[2]: IrDa RX Inversion
• Logic 0 = Select RX input as encoded IrDa data.
• Logic 1 = Select RX input as active high encoded IrDa data.
FCTR[3]: Auto RS-485 Direction Control
• Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
becomes empty and transmit shift register is shifting data out.
• Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its
output logic state from LOW to HIGH one bit time after the last stop bit of the last character is shifted out.
Also, the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The
RTS# output pin will automatically return LOW when a data byte is loaded into the TX FIFO. However, RTS#
behavior can be inverted by setting EMSR[3] = 1.
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
FCTR[5:4]: Transmit/Receive Trigger Table Select
See Table 10.
TABLE 14: TRIGGER TABLE SELECT
FCTR
BIT-5
FCTR
BIT-4
TABLE
0
0
1
1
0
1
0
1
Table-A (TX/RX)
Table-B (TX/RX)
Table-C (TX/RX)
Table-D (TX/RX)
FCTR[6]: Scratchpad Swap
• Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
• Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced
Mode Select Register is selected when it is written into.
FCTR[7]: Programmable Trigger Register Select
• Logic 0 = Registers TRG and FC selected for RX.
• Logic 1 = Registers TRG and FC selected for TX.
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0
0
1
0
1
X
X
X
1
0
0
0
1
1
X
X
X
0
0
X
X
X
X
0
1
0
1
0
X
X
X
X
0
No TX and RX flow control (default and reset)
No transmit flow control
Transmit Xon1, Xoff1
Transmit Xon2, Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
No receive flow control
0
Receiver compares Xon1, Xoff1
Receiver compares Xon2, Xoff2
1
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
0
1
1
0
1
1
1
1
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 to be
modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This
feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is
recommended to leave it enabled, logic 1.
• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are set to a logic 0 to be compatible with ST16C550 mode (default).
• Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
• Logic 0 = Special Character Detect Disabled (default).
• Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
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2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts HIGH at the next upper trigger level. RTS# will return LOW when FIFO data falls below the
next lower trigger level. The RTS# output must be asserted (LOW) before the auto RTS can take effect. RTS#
pin will function as a general purpose output when hardware flow control is disabled.
• Logic 0 = Automatic RTS flow control is disabled (default).
• Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
• Logic 0 = Automatic CTS flow control is disabled (default).
• Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
4.20 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Table 6.
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B
REGISTERS
RESET STATE
DLM and DLL
DLM = 0x00 and DLL = 0x01. Only resets to these values during a
power up. They do not reset when the Reset Pin is asserted.
AFR
RHR
THR
IER
Bits 7-0 = 0x00
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x01
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x60
FCR
ISR
LCR
MCR
LSR
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR
EMSR
FLVL
Bits 7-0 = 0xFF
Bits 7-0 = 0x80
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
RESET STATE
HIGH
EFR
XON1
XON2
XOFF1
XOFF2
FC
I/O SIGNALS
TX
OP1#
MF#
HIGH
HIGH
RTS#
DTR#
TXRDY#
INT
HIGH
HIGH
LOW
LOW
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
ABSOLUTE MAXIMUM RATINGS
Power Supply Range
Voltage at Any Pin
7 Volts
GND-0.3 V to 7 V
-40o to +85oC
Operating Temperature
-65o to +150oC
500 mW
Storage Temperature
Package Dissipation
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
theta-ja = 50oC/W, theta-jc = 21oC/W
Thermal Resistance (44-PLCC)
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC=2.25 -5.5V
LIMITS
2.5V
LIMITS
3.3V
LIMITS
5.0V
SYMBOL
PARAMETER
UNITS
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
VILCK
VIHCK
VIL
Clock Input Low Level
Clock Input High Level
Input Low Voltage
-0.3
2.0
0.6
-0.3
2.4
0.6
-0.5
3.0
0.6
V
V
V
V
VCC
0.8
VCC
0.8
VCC
0.8
-0.3
2.0
-0.3
2.0
-0.5
2.2
VIH
Input High Voltage
Output Low Voltage
5.5
5.5
5.5
IOL = 6 mA
IOL = 4 mA
IOL = 2 mA
VOL
0.4
V
V
V
0.4
0.4
Output High Voltage
IOH = -6 mA
IOH = -1 mA
IOH = -400 uA
VOH
2.4
V
V
V
2.0
1.8
IIL
IIH
Input Low Leakage Current
Input High Leakage Current
Input Pin Capacitance
Power Supply Current
Sleep Current
±10
±10
5
±10
±10
5
±10
±10
5
uA
uA
pF
CIN
ICC
2.7
6
2.7
15
4
mA
uA
ISLEEP
30
See Test 1
Test 1: The following inputs must remain steady at VCC or GND state to minimize Sleep current: A0-A2, D0-
D7, IOR#, IOW#, CS#, CHSEL, and all modem inputs. Also, RXA and RXB inputs must idle at logic 1 state
while asleep. Floating inputs will result in sleep currents in the mA range. For PowerSave feature that isolates
address, data and control signals, please see the XR16L2751 datasheet.
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
AC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC=2.25-5.5V,
70 PF LOAD WHERE APPLICABLE
LIMITS
2.5
LIMITS
3.3
LIMITS
5.0
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX MIN
MAX
-
Crystal Frequency
16
20
24
MHz
ns
CLK
OSC
TAS
External Clock Low/High Time
External Clock Frequency
Address Setup Time
20
15
10
24
33
50
MHz
ns
10
10
10
10
75
75
75
10
10
50
50
50
TAH
TCS
Address Hold Time
ns
ns
Chip Select Width
150
150
150
TRD
TDY
IOR# Strobe Width
ns
Read Cycle Delay
ns
TRDV
TDD
TWR
TDY
Data Access Time
135
45
70
30
45
30
ns
Data Disable Time
0
0
0
ns
IOW# Strobe Width
150
150
25
75
75
20
10
50
50
15
10
ns
Write Cycle Delay
ns
TDS
Data Setup Time
ns
TDH
TWDO
TMOD
TRSI
TSSI
TRRI
TSI
Data Hold Time
15
ns
Delay From IOW# To Output
Delay To Set Interrupt From MODEM Input
Delay To Reset Interrupt From IOR#
Delay From Stop To Set Interrupt
Delay From IOR# To Reset Interrupt
Delay From Stop To Interrupt
150
150
150
1
75
75
75
1
50
50
50
1
ns
ns
ns
Bclk
ns
150
150
24
75
75
24
50
50
24
ns
TINT
Delay From Initial INT Reset To Transmit
Start
8
8
8
Bclk
TWRI
TSSR
TRR
Delay From IOW# To Reset Interrupt
Delay From Stop To Set RXRDY#
150
1
75
1
50
1
ns
Bclk
ns
Delay From IOR# To Reset RXRDY#
Delay From IOW# To Set TXRDY#
Delay From Center of Start To Reset TXRDY#
150
150
8
75
75
8
50
50
8
TWT
ns
TSRT
Bclk
40
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
AC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC=2.25-5.5V,
70 PF LOAD WHERE APPLICABLE
LIMITS
2.5
LIMITS
3.3
LIMITS
5.0
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX MIN
MAX
TRST
N
Reset Pulse Width
40
40
40
ns
-
216-1
216-1
216-1
Baud Rate Divisor
Baud Clock
1
1
1
Bclk
16X or 8X of data rate
Hz
FIGURE 14. CLOCK TIMING
CLK
CLK
EXTERNAL
CLOCK
OSC
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B
IO W #
A c tive
T W D O
R T S #
D T R #
C h a n g e o f s ta te
C h a n g e o f s ta te
C D #
C T S #
D S R #
C h a n g e o f s ta te
C h a n g e o f s ta te
T M O D
T M O D
IN T
A c tive
A c tive
A c tive
A c tive
T R S I
IO R #
A c tive
A c tive
T M O D
C h a n g e o f s ta te
R I#
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
FIGURE 16. DATA BUS READ TIMING
A0-A2
Valid Address
TCS
Valid Address
TCS
TAS
TAS
TAH
TAH
CSA#/
CSB#
TDY
TRD
TRD
IOR#
TDD
TDD
TRDV
TRDV
D0-D7
Valid Data
Valid Data
RDTm
FIGURE 17. DATA BUS WRITE TIMING
A0-A2
Valid Address
Valid Address
TCS
TAS
TAS
TAH
TAH
TCS
CSA#/
CSB#
TDY
TWR
TWR
IOW#
TDH
TDH
TDS
Valid Data
TDS
Valid Data
D0-D7
16Write
42
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
FIGURE 18. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
RX
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
TSSR
TSSR
TSSR
1 Byte
1 Byte
1 Byte
in RHR
in RHR
in RHR
INT
TSSR
TSSR
TSSR
Active
Data
Active
Data
Active
Data
RXRDY#
Ready
Ready
Ready
TRR
TRR
TRR
IOR#
(Reading data
out of RHR)
RXNFM
FIGURE 19. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
TX
(Unloading)
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
IER[1]
enabled
ISR is read
ISR is read
ISR is read
INT*
TWRI
TWRI
TWRI
TSRT
TSRT
TSRT
TXRDY#
TWT
TWT
TWT
IOW#
(Loading data
into THR)
*INT is cleared when the ISR is read or when data is loaded into the THR.
TXNonFIFO
43
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
xr
REV. 1.2.1
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B
Start
Bit
RX
S
S
S
S
T
D0:D7
D0:D7
D0:D7
T
D0:D7
TSSI
D0:D7
S
T
S
D0:D7
T
D0:D7
T
Stop
Bit
RX FIFO drops
below RX
Trigger Level
INT
TSSR
FIFO
Empties
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RXRDY#
First Byte is
Received in
RX FIFO
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXINTDMA#
FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B
Start
Bit
Stop
Bit
RX
S
S
S
S
T
D0:D7
D0:D7
D0:D7
T
D0:D7
TSSI
D0:D7
S
T
S
D0:D7
T
D0:D7
T
RX FIFO drops
below RX
Trigger Level
INT
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
TSSR
FIFO
Empties
RXRDY#
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXFIFODMA
44
xr
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX FIFO
Empty
TX
(Unloading)
T
S
S
S
T
S
T
S
D0:D7
D0:D7
T
S D0:D7
T
D0:D7
T
D0:D7
D0:D7
T
ISR is read
TSI
IER[1]
enabled
ISR is read
TSRT
INT*
TX FIFO
Empty
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
TWRI
Data in
TX FIFO
TXRDY#
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
TXDMA#
FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX
(Unloading)
S
D0:D7
S
D0:D7
S
S
D0:D7
T
T
T
D0:D7
D0:D7
S
D0:D7
T
S D0:D7
T
T
IER[1]
enabled
ISR Read
ISR Read
TSI
TSRT
INT*
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
TWRI
At least 1
empty location
in FIFO
TX FIFO
Full
TXRDY#
TWT
IOW#
(Loading data
into FIFO)
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
TXDMA
45
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
xr
REV. 1.2.1
PACKAGE DIMENSIONS (44 PIN PLCC)
44 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
Rev. 1.00
C
D
Seating Plane
D1
45° x H
1
45° x H
2
A
2
2
1
44
B
1
B
D
D
1
D
D
3
2
e
R
D
3
A
1
A
Note: The control dimension is the millimeter column
INCHES
MAX
MILLIMETERS
SYMBOL
MIN
MIN
MAX
4.57
3.05
A
0.165
0.090
0.180
0.120
4.19
2.29
A
1
A
0.020
0.013
0.026
0.008
0.685
0.650
---
0.51
0.33
---
2
B
0.021
0.032
0.013
0.695
0.656
0.53
0.81
0.32
17.65
16.66
B
0.66
1
C
D
0.19
17.40
16.51
D
1
D
0.590
0.630
14.99
16.00
2
D
0.500 typ.
0.050 BSC
12.70 typ.
1.27 BSC
1.07
3
e
H
0.042
0.056
0.048
0.045
1.42
1.22
1.14
1
H
0.042
0.025
1.07
0.64
2
R
46
xr
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
REVISION HISTORY
DATE
REVISION
DESCRIPTION
November 2001
March 2002
Rev P1.0.0
Rev P1.1.0
Prelim data sheet.
Corrected INTA/B pin descriptions and reset state. Renamed Sclk to Bclk. Changed
A0-A7 in Figures 16 and 17 to A0-A2.
September 2002
Rev 1.0.0
Release into production. Clarified RTS# pin descriptions, XTAL1 pin description,
external clock description, auto RS485 half-duplex control description, EMSR bit-3
description and updated 2.5 V, I and I
DC Electrical Characteristics.
CC
SLEEP
March 2003
August 2004
Rev 1.1.0
Rev 1.2.0
Updated AC Electrical Characteristics.
Added Device Status to Ordering Information. Clarified pin descriptions- changed
from using logic 1 and logic 0 to HIGH (VCC) and LOW (GND) for input and output
pin descriptions.
May 2005
Rev 1.2.1
Updated the Data Access Time (T
) in AC Electrical Characteristics. Corrected
RDV
reset state of MCR bit-3 in MFA# and MFB# pin descriptions.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2005 EXAR Corporation
Datasheet May 2005.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
47
XR16L2752
REV. 1.2.1
xr
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS................................................................................................................................................1
FEATURES .....................................................................................................................................................1
FIGURE 1. XR16L2752 BLOCK DIAGRAM ......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT ..................................................................................................................................................... 2
ORDERING INFORMATION.................................................................................................................................2
PIN DESCRIPTIONS .........................................................................................................3
1.0 PRODUCT DESCRIPTION .....................................................................................................................6
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................7
2.1 CPU INTERFACE .............................................................................................................................................. 7
FIGURE 3. XR16L2750 DATA BUS INTERCONNECTIONS.................................................................................................................... 7
2.2 5-VOLT TOLERANT INPUTS ........................................................................................................................... 7
2.3 DEVICE RESET ................................................................................................................................................ 7
2.4 DEVICE IDENTIFICATION AND REVISION ..................................................................................................... 7
2.5 CHANNEL A AND B SELECTION .................................................................................................................... 7
TABLE 1: CHANNEL A AND B SELECT ............................................................................................................................................... 8
2.6 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................ 8
2.7 SIMULTANEOUS WRITE TO CHANNEL A AND B ......................................................................................... 8
2.8 DMA MODE ....................................................................................................................................................... 8
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE............................................................................................. 8
2.9 INTA AND INTB OUTPUTS .............................................................................................................................. 9
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER ........................................................................................................ 9
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................... 9
2.10 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ........................................................................... 9
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS................................................................................................................................. 9
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE .......................................................................................... 10
2.11 PROGRAMMABLE BAUD RATE GENERATOR ......................................................................................... 10
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER ..................................................................................................................... 10
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 11
2.12 TRANSMITTER ............................................................................................................................................. 11
2.12.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY....................................................................................... 11
2.12.2 TRANSMITTER OPERATION IN NON-FIFO MODE................................................................................................ 11
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 12
2.12.3 TRANSMITTER OPERATION IN FIFO MODE ......................................................................................................... 12
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 12
2.13 RECEIVER .................................................................................................................................................... 12
2.13.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 13
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................... 13
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 13
2.14 AUTO RTS (HARDWARE) FLOW CONTROL ............................................................................................. 14
2.15 AUTO RTS HYSTERESIS ............................................................................................................................ 14
2.16 AUTO CTS FLOW CONTROL ..................................................................................................................... 14
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 15
2.17 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................... 16
TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 16
2.18 SPECIAL CHARACTER DETECT ............................................................................................................... 16
2.19 AUTO RS485 HALF-DUPLEX CONTROL .................................................................................................. 16
2.20 INFRARED MODE ........................................................................................................................................ 17
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 17
2.21 SLEEP MODE WITH AUTO WAKE-UP ....................................................................................................... 18
2.22 INTERNAL LOOPBACK .............................................................................................................................. 19
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 19
3.0 UART INTERNAL REGISTERS ...........................................................................................................20
TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS....................................................................................... 20
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1......................................... 21
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................22
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 22
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 22
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .............................................................................. 22
I
xr
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 23
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 23
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 24
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 24
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 24
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 25
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ..................................................................................... 25
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 27
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 27
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 28
4.7 ALTERNATE FUNCTION REGISTER (AFR) - READ/WRITE ....................................................................... 29
4.8 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 29
4.9 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 30
4.10 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................. 31
4.11 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 32
4.12 ENHANCED MODE SELECT REGISTER (EMSR) ...................................................................................... 32
TABLE 12: SCRATCHPAD SWAP SELECTION .................................................................................................................................... 32
TABLE 13: RTS HYSTERESIS LEVELS ............................................................................................................................................. 33
4.13 FIFO LEVEL REGISTER (FLVL) - READ-ONLY ......................................................................................... 33
4.14 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 34
4.15 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 34
4.16 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 34
4.17 TRIGGER LEVEL REGISTER (TRG) - WRITE-ONLY ................................................................................. 34
4.18 RX/TX FIFO LEVEL COUNT REGISTER (FC) - READ-ONLY .................................................................... 34
4.19 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ........................................................................ 34
TABLE 14: TRIGGER TABLE SELECT ............................................................................................................................................... 35
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS........................................................................................................................ 36
4.20 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 37
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 38
ABSOLUTE MAXIMUM RATINGS .................................................................................. 39
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)39
ELECTRICAL CHARACTERISTICS................................................................................ 39
DC ELECTRICAL CHARACTERISTICS.............................................................................................................. 39
AC ELECTRICAL CHARACTERISTICS.............................................................................................................. 40
Unless otherwise noted: TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc=2.25-5.5V, ................ 40
70 pF load where applicable ..................................................................................................................................... 40
FIGURE 14. CLOCK TIMING............................................................................................................................................................. 41
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 41
FIGURE 16. DATA BUS READ TIMING.............................................................................................................................................. 42
FIGURE 17. DATA BUS WRITE TIMING ............................................................................................................................................ 42
FIGURE 19. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 43
FIGURE 18. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 43
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 44
FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 44
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B ........................... 45
FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 45
PACKAGE DIMENSIONS (44 PIN PLCC)....................................................................... 46
REVISION HISTORY ...................................................................................................................................... 47
TABLE OF CONTENTS ............................................................................................................ I
II
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