XRD9826ACD-F [EXAR]
Analog Circuit, 1 Func, CMOS, PDSO20, 0.300 INCH, SOIC-20;
| 型号： | XRD9826ACD-F |
| 厂家： | 
EXAR CORPORATION |
| 描述： | Analog Circuit, 1 Func, CMOS, PDSO20, 0.300 INCH, SOIC-20 传感器 CD |
| 文件： | 总33页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XRD9826
16-Bit Linear CIS/CCD Sensor
Signal Processor with Serial Control
May 2000-3
FEATURES
APPLICATIONS
·
·
·
·
·
·
·
16-Bit Resolution
·
Color and Grayscale Flatbed Scanners
One-channel 6MSPS Pixel Rate
Triple-channel 2MSPS Pixel Rate
6-BitProgrammableGainAmplifier
8-Bit Programmable Offset Adjustment
CIS or CCD Compatibility
·
·
·
·
·
·
Color and Grayscale Sheetfed Scanners
MultifunctionPeripherals
DigitalColorCopiers
General Purpose CIS or CCD Imaging
Low Cost Data Acquisition
Simple and Direct Interface to Canon 600 DPI
Sensors
Internal Clamp for CIS or CCD AC Coupled
Configurations
·
·
·
·
·
3.3V or 5V Operation & I/O Compatibility
SerialLoadControlRegisters
Low Power CMOS: 200mW-typ
Low Cost 20-Lead Packages
USBCompliant
GENERALDESCRIPTION
range of the ADC. In the CIS configuration the input
can also be AC coupled similar to the CCD configura-
tion. This enables CIS signals with large black levels
tobeinternallyclampedtoaDCreferenceequaltothe
black level. The DC reference is internally subtracted
from the input signal.
TheXRD9826isacompletelinearCISorCCDsensor
signal processor on a single monolithic chip. The
XRD9826includesahighspeed16-bit resolutionADC,
a 6-bit Programmable Gain Amplifier with gain adjust-
mentof1to10, and8-bitprogrammableinputreferred
offset calibration range of 800mV.
The CIS configuration can also be used in other
applications that do not require CDS function, such as
low cost data acquisition.
IntheCCDconfigurationtheinputsignalisACcoupled
with an external capacitor. An internal clamp sets the
black level. In the CIS configuration, the clamp switch
can be disabled and the CIS output signal is DC
coupledfromtheCISsensortotheXRD9826. TheCIS
signal is level shifted to VRB in order to use the full
ORDERINGINFORMATION
PackageType
20-LeadSOIC
20-LeadSSOP
TemperatureRange
0°Cto+70°C
0°Cto+70°C
PartNumber
XRD9826ACD
XRD9826ACU
Rev. 1.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRD9826
VBG
* CIS REF Circuit
AVDD
Power
Down
* CIS REF Circuit
RED
GRN
Triple
S/H
&
DVDD
+
_
3-1
VREF+
VRT
VRB
MUX
BUFFER
BLU
16
8
DATA
I/O
PORT
16-BIT
RL
PGA
6
DB7:0
DGND
ADC
DC Reference
V
DCREF
VDCEXT
INT/EXT_V
DCREF
G<5:0>
CLP
6-BIT GAIN
AVDD
AGND
REGISTERS
Power
Down
DC/AC
R
G
B
AGND
8-BIT DAC
AGND
SYNCH
8
O<7:0>
CIS/CCD
CLAMP
8-BIT OFFSET
REGISTERS
TIMING
&
ADCCLK
R
G
B
VRT
CCD
CIS
CONTROL LOGIC
Note: * For Canon CIS Sensor
Figure 1. Functional Block Diagram
Rev. 1.00
2
XRD9826
PIN CONFIGURATION
1
2
20
19
18
17
16
15
14
13
DVDD
DB0
AVDD
RED
3
DB1
GRN
4
DB2
BLU
5
DB3
VDCEXT
VREF+
AGND
SYNCH
XRD9826ACD
6
DB4
7
DB5/SCLK
DB6/SDATA
8
12 CLAMP
9
DB7/LD
DGND
11
10
ADCCLK
20-LeadSOIC
PINDESCRIPTION
Pin#
1
2
Symbol
DVDD
DB0
Description
Digital VDD (for Output Drivers)
Data Output Bit 0
3
DB1
Data Output Bit 1
4
DB2
Data Output Bit 2
5
DB3
Data Output Bit 3
6
DB4
Data Output Bit 4
7
8
9
DB5/SCLK
DB6/SDATA
DB7/LD
DGND
ADCCLK
CLAMP
SYNCH
AGND
VREF+
VDCEXT
BLU
Data Output Bit 5 & Data Input SCLK
Data Output Bit 6 & Data Input SDATA
Data Output Bit 7 & LD
Digital Ground (for Output Drivers)
A/D Converter Clock
Clamp and Video Sample Clock
Start of New Line and Serial Data Input Control
Analog Ground
A/D Positive Reference for Decoupling Cap
External DC Reference
Blue Input
Green Input
Red Input
10
11
12
13
14
15
16
17
18
19
20
GRN
RED
AVDD
Analog Power Supply
Rev. 1.00
3
XRD9826
ELECTRICALCHARACTERISTICS
Test Conditions: AVDD=DVDD=5V, ADCCLK=6MHz, 50% Duty Cycle, TA=25°C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit Conditions
Power Supplies
AVDD
DVDD
IDD
Analog Power Supply
3.0
3.0
25
3.3
3.3
40
5.5
5.5
60
V
V
(Note 2)
Digital I/O Power Supply
Supply Current
DVDD < AVDD
mA VDD=5V
IDDPD
Power Down Power Supply Current
50
µA VDD=5V
ADC Specifications
RES
Fs
Resolution
16
12
Bits
MSPS
LSB
V
Maximum Sampling Rate
Differential Non-Linearity
Bottom Reference Voltage
Differential Reference Voltage
(VRT - VRB)
DNL
VRB
-2.0
±1.5
2.0
AVDD/10
0.67AVDD
DVREF
0.3
V
RL
Ladder Resistance
300
600
780
Ω
PGA & Offset DAC Specifications
PGARES
PGAGMIN
PGAGMAX
PGAGD
VBLACK
PGA Resolution
6
Bits
Minimum Gain
0.950
9.5
1.0
1.050
10.50
V/V
Maximum Gain
10.0
0.14
V/V
Gain Adjustment Step Size
Black Level Input Range
Offset DAC Resolution
Minimum Offset Adjustment
Maximum Offset Adjustment
Minimum Offset Adjustment
Maximum Offset Adjustment
Offset Adjustment Step Size
V/V
-100
8
500
mV DC Configuration
Bits
DACRES
OFFMIN
-250
+500
-450
+350
-200
+600
-400
-150
+700
-350
+450
mV Mode 111, D5=0 (Note 1)
mV Mode 111, D5=0
mV Mode 111, D5=1 (Note 1)
mV Mode 111, D5=1
mV
OFFMAX
OFFMIN
OFFMAX
OFF∆
+400
3.125
Note 1: The additional ±100 mV of adjustment with respect to the black level input range is needed to compensate
for any additional offset introduced by the XRD9826 Buffer/PGA internally.
Note 2: It is not recommended to operate the part between 3.6V and 4.4V.
Rev. 1.00
4
XRD9826
ELECTRICALCHARACTERISTICS(CONT'D)
Test Conditions: AVDD=DVDD=5V, ADCCLK=6MHz, 50% Duty Cycle, TA=25°C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Buffer Specifications
IIL
Input Leakage Current
100
nA
pF
V
CIN
Input Capacitance
10
VINPP
AC Input Voltage Range
0
0
AVDD-1.4
CIS AC; INT VDCREF
Config Reg
=> XXX010XX
Gain=1 (Note 1)
CCD AC; INT VDCREF
Config Reg
AC Input Voltage Range
DC Input Voltage Range
DC Input Voltage Range
DVREF
V
V
V
=> XXX011XX
Gain=1 (Note 1)
CIS DC; INT VDCREF
Config Reg
VIN
-0.1
AVDD-1.4
=> XXX000XX
Gain=1 (Note 2)
CIS DC; EXT VDCREF
Config Reg
V
DCEXT-0.1
VDCEXT+
DVREF
=> XXX100XX
Gain=1 (Note 3)
VDCEXT+DVREF < AVDD
VDCEXT
External DC Reference
0.3
3
AVDD/2
V
CIS DC; EXT VDCREF
Config Reg
=> XXX100XX
VINBW
VINCT
Input Bandwidth
MHz
dB
Channel to Channel Crosstalk
-60
-50
fin=3MHz
Internal Clamp Specifications
VCLAMP
Clamp Voltage
AGND
VRT
50
mV
V
CIS (AC) Config
CCD (AC) Config
3.5
10
RINT
ROFF
Clamp Switch On Resistance
Clamp Switch Off Resistance
100
150
Ω
MΩ
Note 1: VINPP is the signal swing before the external capacitor tied to the MUX inputs.
Note 2: The -0.1V minimum is specified in order to accommodate black level signals lower than the external DC
reference (clamp) voltage.
Note 3: The VDCEXT-0.1V minimum is specified in order to accommodate black level signals lower than the external DC
reference voltage.
Rev. 1.00
5
XRD9826
ELECTRICALCHARACTERISTICS(CONT'D)
Test Conditions: AVDD=DVDD=5V, ADCCLK=6MHz, 50% Duty Cycle, TA=25°C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
+2.3
+5.0
Unit
Conditions
Note 1
System Specifications (MUX + Buffer + PGA + ADC)
SYSDNL
SYSLIN
SYSGE
IRN
System DNL
-1.0
-5.0
±0.5
±6.0
LSB
LSB
%
System Linearity
System Gain Error
Input Referred Noise
Input Referred Noise
1.5
0.5
mVrms
mVrms
Gain=1
Gain=10
System Timing Specifications
tcklw
tckhw
tckpd
tsypw
trars
ADCCLK Low Pulse Width
50
70
120
30
0
83
83
ns
ns
ns
ns
ADCCLK High Pulse Width
ADCCLK Period
166
SYNCH Pulse Width
Rising ADCCLK to rising
SYNCH
SYNCH must rise equal to
or after ADCCLK, See Figure 18
tclpw
CLAMP Pulse Width
30
ns
Note 2
Write Timing Specifications
tsclkw
tdz
SCLK Pulse Width
40
20
20
0
ns
ns
ns
ns
ns
LD Low to SCLK High
Input Data Set-up Time
Input Data Hold Time
SCLK High to LD High
tds
tdh
tdl
50
ADC Digital Output Specifications
tap
tdv
tsa
tlat
tlat
Aperture Delay
Output Data Valid
SYNCH to ADCCLK
Latency
10
ns
ns
ns
40
15
3ch Pixel Md
8
6
cycles Config 00, 11
pixels Config 01, 10
Latency
Digital Input Specifications
VIH
VIL
IIH
Input High Voltage
AVDD-2.5
V
V
Input Low Voltage
1
High Voltage Input Current
Low Voltage Input Current
Input Capacitance
5
5
µA
µA
pF
IIL
CIN
10
Note 1: System performance is specified for typical digital system timing specifications.
Note 2: The actual minimum ‘tclpw’ is dependent on the external capacitor value, the CIS output impedance.
During ‘clamp’ operation, sufficient time needs to be allowed for the external capacitor to charge up to the
correct operating level. Refer to the description in Theory of Operation, CIS Config.
Rev. 1.00
6
XRD9826
ELECTRICALCHARACTERISTICS(CONT'D)
Test Conditions: AVDD=DVDD=5V, ADCCLK=6MHz, 50% Duty Cycle, TA=25°C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Digital Output Specifications
VOH
DVDD
VOL
Output High Voltage
80
(%)
(%)
IL=1mA
Output Low Voltage
IL=-1mA
20
10
15
DVDD
IOZ
Output High-Z Leakage Current
Output Capacitance
Slew Rate (10% to 90% DVDD)
-10
2
µA
pF
ns
COUT
SR
10
CL=10pF, DVDD=3.3V
Rev. 1.00
7
XRD9826
Mode 1. DC Coupled
THEORYOFOPERATION
If the CIS does not have leading or trailing black pixels
asshowninFigure2,thenDCcoupletheCISoutputto
theXRD9826input.
CIS Configuration (Contact Image Sensor)
TheXRD9826hastwoconfigurationsforCISapplica-
tions. Eachconfigurationissetbythecontrolregisters
accessed through the serial port.
Optically Shielded
Pixels
Valid Pixels
Figure 2. Typical Output CIS Mode
Adjust the offset of the CIS (-100 mV to 500 mV) by
setting the internal registers of the XRD9826 to set the
black pixel value when the LEDs of the CIS are off.
When the LEDs are on, use the XRD9826 Program-
mable Gain to maximize the ADCs dynamic range.
Figure 3, shows a typical application for a CIS with an
offset of -100mV to 500mV.
Rev. 1.00
8
XRD9826
XRD9826
VDD
VRT
C
I
RED
M
U
X
N/C
N/C
N/C
RL
S
VRB
Figure 3. Application with Offset in the Range (-100mv to 500mv)
The input is added to VRB before the signal passes
beyond the offset range of the XRD9826 (see Offset
ControlDAC,Pg.22)settheinternalmoderegistersto
external reference. An external reference voltage
equal to the value of the CIS offset voltage can be
applied to VDCEXT (Figure 4) in order to meet the
dynamicrangeoftheXRD9826. Figure4,isadiagram
oftheXRD9826intheexternalreferencemodeforCIS,
DCcoupledapplications.
through the ADC. If the CIS output is zero, then the
output of the ADC will be zero code. This enables the
CIS to be referenced to the bottom ladder reference
voltage to use the full range of the ADC.
Some CIS sensors have an output with an offset
voltage of greater than 500mV. If the CIS output is
Rev. 1.00
9
XRD9826
XRD9826
VDD
VRT
C
I
RED
M
U
X
N/C
N/C
S
RL
VDCEXT
DC
REFERENCE
VRB
Figure 4. Application with Offset Greater Than (-100mv to 500mv)
TheDCreferencevoltageappliedtoVDCEXTdoesnot
have to be accurate. The internal offset DAC voltage
is still used in this mode for fine adjustment. VDCEXT
cannot be used as an input from the CIS. Any signal
applied to VDCEXT will be subtracted from the output
signal of the multiplexer.
Rev. 1.00
10
XRD9826
VCC (5V - 15V)
19
18
9
8
7
6
5
4
3
2
DB7/LD
RED
GRN
DB6/SDATA
DB5/SCLK
DB4
N/C
N/C
DB3
AVDD
DB2
C
I
S
DB1
17
16
DB0
BLU
DIGITAL
ASIC
VDCEXT
11
ADCCLK
CLAMP
SYNCH
12
13
15
VREF+
0.1uF
AVDD
DVDD (3V - 5V)
1
20
14
AVDD
AGND
DVDD
DGND
10
XRD9826
AGND
DGND
Figure 5. Typical Application Circuitry CIS DC Coupled Non-Inverted Mode
Rev. 1.00
11
XRD9826
CIS Mode Timing -- DC Coupled
(CLAMP disabled)
Pixel N-1
Pixel N
tap
Pixel N+1
tap
CIS
tckpd
tckhw tcklw
ADCCLK
tdv
tdv
N-6
N-6
N-8
N-7
N-8
N-7
N-5
N-5
[5:0]
DB
MSB
LSB
LSB
MSB
MSB
LSB
LSB
[11:6]
MSB
Figure 6. Timing Diagram for Figure 5
ADCCLK
Events
↓
ADC Sample & PGA Start Tracking next Pixel
MSB Data Out
↑
LSB Data Out
HI
LO
ADC Track PGA Output
ADC Hold/Convert
Table 1.
Mode 2. AC Coupled
If the CIS signal has a black reference for the video
signal, an external capacitor CEXT is used. When
CLAMP(clamp)pinissethighaninternalswitchallows
one side of the external capacitor to be set to ground.
Itthenislevelshiftedtocorrespondtothebottomladder
reference voltage of the ADC (Figure 7).
Rev. 1.00
12
XRD9826
XRD9826
VDD
VRT
REXT
CEXT
RED
C
I
S
M
U
X
N/C
N/C
N/C
RL
CLAMP
VRB
RINT
Figure 7. CIS AC Coupled Application
This value corresponds to the black reference of the
imagesensor. WhentheCLAMPpinissetbacktolow,
the ADC samples the video signal with respect to the
black reference. The typical value for the external
capacitor is 100pF. This value should be adjusted
according to the time constant (Tc) needed in a
particularapplication. TheCLAMPpinhasaninternal
150 ohm impedance (RINT) which is in series with the
externalcapacitor(CEXT).
Therefore, Tc =1/RINTCEXT
If the input to the external capacitor has a source
impedance(REXT),then:
Tc=1/(RINT+REXT)CEXT
Rev. 1.00
13
XRD9826
VCC (5V - 15V)
19
18
17
16
15
9
8
7
6
5
4
3
2
DB7/LD
RED
DB6/SDATA
DB5/SCLK
100PF
DB4
N/C
N/C
N/C
GRN
DB3
DB2
C
I
S
DB1
DB0
BLU
DIGITAL
ASIC
11
VDCEXT
VREF+
ADCCLK
12
13
CLAMP
SYNCH
DVDD (3V - 5V)
1
AVDD
20
14
AVDD
AGND
DVDD
DGND
10
XRD9826
AGND
DGND
Figure 8. Typical Application Circuitry CIS AC Coupled Non-Inverted
Rev. 1.00
14
XRD9826
CIS Mode Timing -- AC Coupled
(CLAMP enabled)
Pixel N-1
Pixel N
tap
Pixel N+1
tap
CIS
tckpd
tckhw tcklw
ADCCLK
tdv
tdv
N-6
MSB
N-6
N-8
MSB
N-7
MSB
N-8
N-7
[5:0]
DB
N-5
MSB
N-5
LSB
LSB
LSB
LSB
[11:6]
tclpw
CLAMP
Note: There is an 8 clock latency for the output
Figure 9. Timing Diagram for Figure 8.
ADCCLK
Events
↓
ADC Sample & PGA Start Track of next Pixel
MSB Data Out (8 Upper Bits)
LSB Data Out (8 Lower Bits)
ADC Track PGA Output
↑
HI
LO
ADC Hold/Convert
Table 3.
CLAMP
Events
HI
PGA Tracks VCLAMP & CEXT is Charged to
VBLACK - VCLAMP, which is equal to VBLACK
PGA Tracks VINPP
LO
Table 4.
Rev. 1.00
15
XRD9826
Internal CIS Reference Circuit (DB 4 = 1)
The XRD9826 has an internal register reserved for
interfacing to the Canon CIS model number CVA-
60216K. When this register is selected, the VDCEXT
(Pin16)becomesanoutputvoltageof1.24volts. This
voltage can be directly connected to the VREF (Pin 5)
of the Canon sensor. This reduces the amount of
componentsneededforbiasingtheCanonCISsensor
(theexternaldiodesandresistorstypicallyusedinthis
applicationhavebeenincludedinsidetheXRD9826for
this mode of operation). Below is a typical application
circuitusingtheXRD9826andtheCanonCVA-60216K
CIS sensor.
VCC (5V)
CANON CIS
DVDD (3V - 5V)
SENSOR
VOUT
1
2
MODE
3
AGND
4
VCC
5
VREF
19
18
9
8
7
6
5
4
3
2
6
RED
GRN
DB7/LD
DB6/SDATA
DB5/SCLK
DB4
SP
7
CLK
8
N/C
N/C
DB3
DB2
DB1
DB0
LED COM
9
LED BLU
17
16
10
BLU
LED GRN
11
LED RED
VDCEXT
DIGITAL
ASIC
NPN
11
12
13
12
ADCCLK
CLAMP
SYNCH
FGND
47uF
DGND
15
VREF+
NPN
0.1uF
AGND
DVDD (3V - 5V)
AVDD
DGND
20
14
1
0.01uF
AVDD
AGND
DVDD
DGND
NPN
10
100uF
DGND
AGND
DGND
XRD9826
DGND
CVA-60216K
Figure 10. Typical Application Circuitry Internal CIS Reference Circuit Mode
CANONCISSensor,Model#CVA=60216k
Rev. 1.00
16
XRD9826
CIS Line-By-Line Rotating Gain and Offset
(Configuration DB1 = 1, DB0 = 1)
Line-by-line rotating gain and offset minimizes the
amountofwritecyclesperscan. Pre-loadedvaluesof
gainandoffsetcanbeloadedforeachcolorbeforethe
first line is scanned. Each gain and offset is cycled
through line-by-line so that the gain and offset do not
havetobeloadedinbetweenlines. Belowisthetypical
application circuit and timing for this configuration.
VCC (5V - 15V)
19
9
RED
DB7/LD
8
7
6
5
4
3
2
DB6/SDATA
DB5/SCLK
DB4
18
GRN
DB3
DB2
DB1
DB0
C
I
S
17
BLU
DIGITAL
ASIC
16
N/C
VDCEXT
11
12
13
ADCCLK
CLAMP
SYNCH
15
VREF+
0.1uF
DVDD (3V - 5V)
AVDD
20
1
AVDD
DVDD
DGND
14
10
AGND
AGND
XRD9826
DGND
Figure 11. Typical Application Circuitry Internal CIS Rotating Gain
andOffsetLine-By-Line
Rev. 1.00
17
XRD9826
CIS Rotating Gain and Offset
Line-By-Line (Md 11)
CIS
Red Pixel Line Scan
Grn Pixel Line Scan
Blu Pixel Line Scan
ADCCLK
SYNCH
tsypw
tsa
GAIN/
Red Gain/Offset Cycle
Grn Gain/Offset Cycle
Blu Gain/Offset Cycle
OFFSET
Tri-State (SYNCH = LO)
LD
Reset Internal Mux Color to Red Channel (LD = 110YYYYYY11)
Y = Previous State
Note:
Figure 12. Timing Diagram for Figure 11.
CCDConfiguration(ChargeCoupledDevice)
Mode 1. AC Coupled
WhenCLAMP(clamp)pinissethighaninternalswitch
allows one side of the external capacitor to be set to
VRT (Figure 13). This value corresponds to the black
referenceoftheCCD. WhentheCLAMPpinissetback
to low, the ADC samples the video signal with respect
to the black reference. The difference between the
black reference and the video signal is the actual pixel
value of the video content. Since this value is refer-
encedtothetopladderreferencevoltageoftheADCa
zero input signal would yield a full scale output code.
Therefore, the output of the conversion is inverted
(internally) to correspond to zero scale output code.
In the CCD configuration of operation, an external
capacitor needs to be chosen according to the equa-
tionsbelow.Thetypicalvaluefortheexternalcapacitor
is 100pF. This value should be adjusted according to
the time constant (Tc) needed in a particular applica-
tion. The CLAMP pin has an internal 150 ohm imped-
ance(RINT)whichisinserieswiththeexternalcapacitor
(CEXT).
Therefore, Tc =1/RINTCEXT
If the input to the external capacitor has a load
impedance(REXT),then
Tc=1/(RINT+REXT)CEXT
Rev. 1.00
18
XRD9826
XRD9826
VDD
CLAMP
VRT
AREA
or
RED
LINEAR
CCD
M
U
X
N/C
N/C
N/C
RL
VRB
Figure 13. CCD AC Coupled Application
Area or Linear CCD Applications
pixelvalueshavebeensampled,thegainandoffsetare
adjustedatthebeginningofthenextline. Forexample,
if there is a line-to-line variation between the black
reference pixels, the offset is adjusted. The gain is
always adjusted for the highest color intensity.
Figure 13 is a block diagram for applications with Area
or Linear CCDs (The timing for Area CCDs and B/W
CCDs is the same). For Area or Linear CCD applica-
tions, a global offset is loaded into the serial port at the
beginning of a line. The gain is set to adjust for the
highest color intensity of the CCD output. Once the
Rev. 1.00
19
XRD9826
VCC (5V - 15V)
19
18
17
16
15
9
8
7
6
5
4
3
2
RED
DB7/LD
DB6/SDATA
DB5/SCLK
DB4
100PF
N/C
N/C
N/C
GRN
DB3
DB2
DB1
DB0
C
C
D
BLU
DIGITAL
ASIC
11
12
13
VDCEXT
VREF+
ADCCLK
CLAMP
SYNCH
DVDD (3V - 5V)
AVDD
20
14
1
AVDD
AGND
DVDD
DGND
10
AGND
XRD9826
DGND
Figure 14. Typical Application Circuitry Single
Channel CCD AC Coupled Inverted Mode.
Rev. 1.00
20
XRD9826
AREA, LINEAR or B/W CCD -- AC Coupled
(CLAMP Enabled)
Pixel N-1
Pixel N
Pixel N+1
CCD
Channel N
tckpd
tckhw tcklw
tap
tap
ADCCLK
tclpw
CLAMP
[5:0]
tdv
tdv
N-6
N-7
MSB
N-8
MSB
N-7
N-6
N-8
LSB
DB
MSB
LSB
LSB
[11:6]
Note: There is an 8 clock latency at the output.
Figure 15. Timing Diagram for Figure 14.
Triple Channel CCD Application
Thegainandoffsetisautomaticallyrotatedtoadjustfor
each channel input. The MSBs (8 upper bits) are
available on the output bus on the falling edge of
ADCCLK. The LSBs (8 lower bits) are available on the
rising edge of ADCCLK.
Figure 6 is a block diagram for pixel-by-pixel applica-
tions with triple channel CCDs. During the optically
shielded section of a pixel, CLAMP must go high to
storetheblackreferenceoneachcapacitortotheinput.
Rev. 1.00
21
XRD9826
XRD9827
VDD
CLAMP
VRT
RED/GRN/BLU
C
C
D
M
U
X
RL
N/C
VRB
Figure 16. CCD AC Coupled Application
Rev. 1.00
22
XRD9826
VCC (5V - 15V)
19
18
17
16
15
9
8
7
6
5
4
3
2
RED
DB7/LD
DB6/SDATA
DB5/SCLK
DB4
100PF
100PF
100PF
GRN
DB3
DB2
DB1
DB0
C
C
D
BLU
DIGITAL
ASIC
11
12
N/C
VDCEXT
VREF+
ADCCLK
CLAMP
SYNCH
13
AVDD
DVDD (3V - 5V)
20
14
1
AVDD
AGND
DVDD
DGND
10
AGND
XRD9826
DGND
Figure 17. Typical Application Circuitry Triple Channel CCD
AC Coupled Inverted Mode
Rev. 1.00
23
XRD9826
PIXEL-BY-PIXEL 3 CHANNEL CCD -- AC Coupled
(CLAMP Enabled)
RED
N Pixel
N+1 Pixel
GRN
N Pixel
N+1 Pixel
tclp=10ns
tclp=10ns
BLU
N Pixel
N+1 Pixel
tap
CONVERT
BLU (N)
CONVERT
GRN (N)
TRACK
RED (N)
CONVERT
RED (N)
TRACK
GRN (N)
TRACK
BLU (N)
TRACK
RED (N+1)
CONVERT
RED (N+1)
ADCCLK
CLAMP
trars
Simultaneous
Sample
CLAMP
tdv
tdv
RED (N-6)
tdv
RED (N-6)
tdv
GRN (N-6)
tdv
GRN (N-6)
MSB
BLU (N-6)
LSB
BLU (N-6)
MSB
LSB
LSB
MSB
DATA
tsa
tsypw
SYNCH
Note: There is an 8 clock latency at the output.
Figure 18. Timing Diagram for Figure 17
ADCCLK
Events
3rd ↓
Simultaneous RED/GRN/BLU Sample Every 3rd CLK.
Convert RED, S/H GRN, S/H BLU.
MSB Data Out (8 upper bits)
All ↓
↑
LSB Data Out (8 lower bits)
HI
LO
ADC Track PGA Output
ADC Hold/Convert
CLAMP
HI
Events
Internal Clamp Enabled
LO
SYNCH
HI
Internal RED/GRN/BLU Tracking Enabled
Events
Reset Internal Mux to Red, Ouput Bus is Tri-stated
Increment Mux Color on Falling Edge of ADCCLK
LO
Table 5.
Rev. 1.00
24
XRD9826
VRT
S1, S2 and S3 close when
CLAMP is high and open
when CLAMP is low
S1 S2 S3
From CCD RED
Channel
S6
S7
S8
C
C
C
EXT
EXT
EXT
R
G
B
12-Bit ADC
S9 closes at rising edge and opens
at falling edge of ADCCLK
From CCD
S4
VRT - V
PIX
GRN Channel
-
S9
PGA
+
T/H
T/H
From CCD BLU
Channel
S5
VRT
VCDS = PGAG * [VRT - (VRT - VPIX)]
= PGAG * VPIX
T/H
XRD9827
VBLK
CCD
Waveform
V
PIX
V
-
VBLK
PIX
CLAMP
S8 Opens, S4,
S5 and S6
S8 Opens, S4,
S6 opens, S7
closes at this
rising edge
S7 opens, S8
closes at this
rising edge
S4 and S5 open
at this falling
edge
S5 and S6
close at this
rising edge
close at this
rising edge
Track
RED
Convert
RED
Track
GRN
Convert
GRN
Track
BLU
Convert
BLU
Track
RED
Convert
RED
ADCCLK
Figure 19. CDS Timing (Triple Channel)
Mode:11000001110
Rev. 1.00
25
XRD9826
PGA GAIN TRANSFER CURVE
GAIN 1 - 10
10
9
8
7
6
5
4
3
2
1
Mode 2. DC Coupled
Typical CCDs have outputs with black references.
Therefore, DC Coupled is not recommended for CCD
applications.
OffsetControlDAC
0
10
20
30
40
50
60
TheoffsetDACiscontrolledby8bits. Theoffsetrange
is800mVrangingfrom-200mVto+600mV(whenDB5
is set to 0) and -400 mV to +400 mV (when DB5 is set
to 1). Therefore, the resolution of the 8-Bit offset DAC
is 3.14 mV. However, the XRD9826 has +/- 100 mV
reserved for internal offsets. Therefore, the effective
rangeforadjustingforCISoffsetsorblackreferenceis
600 mV. The offset adjustment is used primarily to
correctforthedifferencebetweentheblacklevelofthe
imagesensorandthebottomladderreferencevoltage
(VRB) of the ADC. By adjusting the black level to
correspondtoVRB,theentirerangeoftheADCcanbe
used.
CODE
Figure 20. Transfer Curve for the 6-Bit PGA
After the signal is level shifted to correspond with the
bottom ladder reference voltage, the system can be
calibrated such that a white video pixel can represent
thetopladderreferencevoltagetotheADC. Thisallows
for a full scale conversion maximizing the resolution of
the ADC.
AnalogtoDigitalConverter
IftheoffsetoftheCISoutputisgreaterthan500mVan
external reference can be applied to VDCEXT. The
external reference can be used to adjust for large
offsets only when the internal mode is configured
through the serial port.
The ADC is a 16-bit, 10 MSPS analog-to-digital con-
verterforhighspeedandhighaccuracy. TheADCuses
a subranging architecture to maintain low power con-
sumption at high conversion rates. The output of the
ADCisonan8-bitdatabus. The8-bitdatabussupports
8x8 output data. ADCCLK samples the input on its
falling edge. After the input is sampled, the MSB (8
upperbits)islatchedtotheoutputdrivers. Ontherising
edge of the ADCCLK, the LSB (8 lower bits) is latched
to the output drivers. The output needs to be
demultiplexed with external circuitry or a digital ASIC.
There is an 8 clock cycle latency (Config 00, 11) or 6
pixel count latency (Config 01, 10) for the analog-to-
digitalconverter.
Since the offset DAC adjustment is done before the
gain stage, it is gain-dependent. For example, if the
gain needs to be changed between lines (red to blue,
etc.), the offset is calibrated before the signal passes
through the PGA.
PGA (Programmable Gain Amplifier) DAC
The gain of the input waveform is controlled by a 6-Bit
PGA. The PGA is used along with the offset DAC for
the purpose of using the entire range of the ADC. The
PGA has a linear gain from 1 to 10. Figure 19 is a plot
of the transfer curve for the PGA gain.
The VRT and VRB reference voltages for the ADC are
generated internally, unless the external VRT is se-
lected. In the external VRT mode, the VRT voltage is set
through the VREF+ pin. This allows the user to select
the dynamic range of the ADC.
Rev. 1.00
26
XRD9826
SerialLoadControlRegisters
The serial load registers are controlled by a three wire
serialinterfacethroughthebi-directionalparallelportto
reducethepincountofthisdevice. WhenSYNCHisset
to high, the output bus is tri-stated and the serial
interface is activated. DB7/LD, DB5/SCLK and DB6/
SDATA are the three input signals that control this
process. The DB7/LD signal is set low to initiate the
loading of the internal registers.
ThefirstthreeMSBschoosewhichinternalregisterwill
be selected. The remaining 8 LSBs contain the data
needed for programming the internal register for a
particularconfiguration.
Power-UpStateoftheInternalRegisters
The control register settings upon initial power-up are
for CIS, DC Coupled configuration (VRT is set to
internal, Input DC Reference=AGND and the input to
theADCisselectedthroughtheREDchannel). Gainis
unity and Offset is set to zero. The test modes are
disabled in the power-up state.
Thereareinternal registersthatareaccessedviaan11-
bit data string. Data is shifted in on the rising edge of
SCLK and loaded to the registers on the rising edge of
LD. The data on pin DB6/SDATA is latched automati-
cally after eleven DB5/SCLKs have been counted. If
elevenclocksarenotpresentonDB5/SCLKbeforethe
DB7/LD signal returns high, no data will be loaded into
the internal registers. If more than 11 clocks are
present on DB5/SCLK, the additional clocks will be
ignored. The data corresponding to the first eleven
DB5/SCLKs will be loaded only.
SYNCH
tsclkw
DB7/LD
tdl
tdz
DB5/SCLK
tds tdh
S1
S2
S0
D7
D2
D1
D0
DB6/SDATA
Figure 21. Write Timing
Rev. 1.00
27
XRD9826
OutputBusFormat
ADCOutput—>DO15(MSB):DO0(LSB)
DB7
DO5
DO7
DB6
DO4
DO6
DB5
DO3
DO5
DB4
DO2
DO4
DB3
DO1
DO3
DB2
DO0
DO2
DB1
DO9
DO1
DB0
DO8
DO0
MSB
LSB
Table 9. 8 MSB + 8 LSB Output Bus Format
Note : 1 These are the control register settings upon initial power-up. The previous register settings are retained
following a logic power-down initiated by the power down bit except the signal configuration. When de-selecting
the power down bit (D7 = 0, Normal), the signal configuration (D5 and D0) has to be reprogrammed.
2
MSB = 8 upper bits
LSB = 8 lower bits
Rev. 1.00
28
XRD9826
ControlRegisters
Function
(Register
S2/S1/S0)
D7
D6
D5
D4
D3
D2
D1
D0
Power-up
State
(Note1)
Red Gain
(000)
G5
(MSB)
G4
O6
G4
G3
O5
G3
G2
O4
G2
G1
O3
G1
G0
(LSB)
X
O1
X
X
000000XX
01000000
000000XX
Red Offset
(001)
O7
(MSB)
O2
O0
(LSB)
Grn Gain
(010)
G5
(MSB)
G0
(LSB)
X
Grn Offset
(011)
O7
(MSB)
O6
G4
O6
O5
G3
O4
G2
O4
O3
G1
O2
O1
X
O0
(LSB)
01000000
000000XX
Blu Gain
(100)
G5
(MSB)
G0
(LSB)
X
Blu Offset
(101)
O7
(MSB)
O5
O3
O2
O1
O0
(LSB)
01000000
00000000
Mode
(110)
POWER
DOWN
DIGITAL
RESET
VRT
INPUTDC
REFERENCE
DC/AC
SIGNAL
POLARITY
SIGNAL
CONFIGURATION
(VDCREF
)
0:NORMAL
0: NO RESET
0:INTERNAL
1:EXTERNAL
0:INTERNAL
(VDCREF=AGND)
1:EXTERNAL
0: DC
1: AC
0: Non-
Inverted
(CIS)
1: Inverted
(CCD/CIS)
00:Single-Channel
RED input/gain/offset
1:
1:RESET
(REGISTERS
ARERESETTO
POWER-UP
STATES)
POWER
DOWN
(VDCREF=VDCEXT
)
01:Single-Channel
REDinput
RED/GRN/BLU
gain/offset cycle
pixel-by-pixel
10:Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
pixel-by-pixel
11:Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
line-by-line
Mode
&Test
(111)
TEST5
OUTPUT
DISABLE
OFFSET
DAC
RANGE
INTERNALCIS
REFERENCE
CIRCUIT
TEST4
TEST3
TEST2
TEST1
00000000
0:NOTUSED
1:NORMAL
0:OUTPUTS
ENABLED
0:-200mV to
+600mV
0:NORMAL
0: TEST4
0:TEST3
0:TEST2 0:NORMAL
DISABLED DISABLED DISABLED
1:OUTPUTS
DISABLED
1:-400mV to
+400mV
1:REFERENCE
CIRCUIT
ENABLED
1:OUTPUT 1:OUTPUT
OF BUFFER OFPGA
TIEDTO
BLU
1:INPUT
OFADC
TIEDTO
GRN
1:TEST1
ENABLED
TIEDTO
VDCEXT
Rev. 1.00
29
XRD9826
2.50
2.00
1.50
1.00
0.50
0.00
-0.50
-1.00
-1.50
0.00
20,000
40,000
60,000
Code
Figure 22. DNL: Single-Channel CCD 6MSPS AC Coupled
2.50
2.00
1.50
1.00
0.50
0.00
-0.50
-1.00
-1.50
0.00
20,000
40,000
60,000
Code
Figure 23. DNL: Three-Channel CCD 6MSPS AC Coupled
Rev. 1.00
30
XRD9826
Rev. 1.00
31
XRD9826
20 LEAD SHRINK SMALL OUTLINE PACKAGE
(5.3 mm SSOP)
Rev. 2.00
D
20
11
E
H
1
10
C
A2
A
Seating
Plane
α
e
B
A1
L
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
0.079
0.006
0.073
0.015
0.010
0.296
0.221
MIN
1.70
0.05
1.65
0.22
0.09
6.90
5.00
MAX
2.00
0.15
1.85
0.38
0.25
7.50
5.60
A
A1
A2
B
C
D
0.067
0.002
0.065
0.009
0.004
0.272
0.197
E
e
0.0256 BSC
0.65 BSC
H
L
0.292
0.022
0.323
0.037
7.40
0.55
8.20
0.95
α
0°
8°
0°
8°
Note: The control dimension is the inch column
Rev. 1.00
32
XRD9826
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation
that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustra-
tion purposes and may vary depending upon a user’s specific application. While the information in this publi-
cation has been carefully checked; no responsibility, however, is assumed for in accuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or
damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is
adequately protected under the circumstances.
Copyright 2000 EXAR Corporation
Datasheet May 2000
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.00
33
相关型号：
©2020 ICPDF网 联系我们和版权申明