XRD9827ACU [EXAR]
12-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control; 12位线性CIS / CCD传感器信号处理器与串行控制
| 型号： | XRD9827ACU |
| 厂家： | 
EXAR CORPORATION |
| 描述： | 12-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control |
| 文件： | 总32页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XRD9827
12-Bit Linear CIS/CCD Sensor
Signal Processor with Serial Control
May 2000-3
FEATURES
APPLICATIONS
· 12-Bit Resolution, No Missing Codes
· One-channel 6MSPS Pixel Rate
· Triple-channel 2MSPS Pixel Rate
· 6-BitProgrammableGainAmplifier
· 8-Bit Programmable Offset Adjustment
· CIS or CCD Compatibility
· Color and Grayscale Flatbed Scanners
· Color and Grayscale Sheetfed Scanners
· MultifunctionPeripherals
· DigitalColorCopiers
· General Purpose CIS or CCD Imaging
· Low Cost Data Acquisition
· Internal Clamp for CIS or CCD AC Coupled
Configurations
· Simple and Direct Interface to Canon 600 DPI
Sensors
· 3.3V or 5V Operation & I/O Compatibility
· SerialLoadControlRegisters
· Low Power CMOS: 200mW-typ
· Low Cost 20-Lead Packages
· USBCompliant
GENERALDESCRIPTION
The XRD9827 is a complete linear CIS or CCD sensor
signal processor on a single monolithic chip. The
XRD9827includesahighspeed12-Bit resolutionADC,
a 6-Bit Programmable Gain Amplifier with gain adjust-
mentof1to10, and8-Bitprogrammableinputreferred
offset calibration range of 800mV.
AC coupled similar to the CCD configuration. This
enables CIS signals with large black levels to be
internallyclampedtoaDCreferenceequaltotheblack
level. The DC reference is internally subtracted from
the input signal.
The CIS configuration can also be used in other appli-
cations that do not require CDS function, such as low
cost data acquisition.
IntheCCDconfigurationtheinputsignalisACcoupled
with an external capacitor. An internal clamp sets the
black level. In the CIS configuration, the clamp switch
canbedisabledandtheCISoutputsignalisDCcoupled
from the CIS sensor to the XRD9827. The CIS signal
is level shifted to VRB in order to use the full range of
theADC. IntheCISconfigurationtheinputcanalsobe
ORDERINGINFORMATION
PackageType
TemperatureRange
0°Cto+70°C
0°Cto+70°C
PartNumber
XRD9827ACD
XRD9827ACU
20-LeadSOIC
20-LeadSSOP
Rev. 1.20
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRD9827
VBG
CIS REF Circuit
AVDD
Power
Down
CIS REF Circuit
RED
GRN
Triple
S/H
&
DVDD
+
_
3-1
VREF+
VRT
VRB
MUX
BUFFER
BLU
12
8
DATA
I/O
PORT
12-BIT
RL
PGA
6
DB7:0
DGND
ADC
DC Reference
V
DCREF
VDCEXT
INT/EXT_V
DCREF
G<5:0>
CLP
6-BIT GAIN
AVDD
AGND
REGISTERS
Power
Down
DC/AC
R
G
B
AGND
8-BIT DAC
AGND
SYNCH
8
O<7:0>
CIS/CCD
CLAMP
8-BIT OFFSET
REGISTERS
TIMING
&
ADCCLK
R
G
B
VRT
CCD
CIS
CONTROL LOGIC
Figure 1. Functional Block Diagram
Rev. 1.20
2
XRD9827
PINCONFIGURATION
1
2
20
19
18
17
16
15
14
13
D V D D
DB0
AVDD
RED
3
DB1
G R N
4
DB2
BLU
5
DB3
VDCEXT
VREF+
A G N D
SYNCH
XRD9827ACD
6
DB4
7
DB5/SCLK
DB6/SDATA
8
12 CLAMP
9
DB7/LD
D G N D
11
10
ADCCLK
20-LeadSOIC
PINDESCRIPTION
Pin#
1
2
Symbol
DVDD
DB0
Description
Digital VDD (for Output Drivers)
Data Output Bit 0
3
DB1
Data Output Bit 1
4
DB2
Data Output Bit 2
5
DB3
Data Output Bit 3
6
DB4
Data Output Bit 4
7
8
9
DB5/SCLK
DB6/SDATA
DB7/LD
DGND
ADCCLK
CLAMP
SYNCH
AGND
VREF+
VDCEXT
BLU
Data Output Bit 5 & Data Input SCLK
Data Output Bit 6 & Data Input SDATA
Data Output Bit 7 & LD
Digital Ground (for Output Drivers)
A/D Converter Clock
Clamp and Video Sample Clock
Start of New Line and Serial Data Input Control
Analog Ground
A/D Positive Reference for Decoupling Cap
External DC Reference
Blue Input
Green Input
Red Input
10
11
12
13
14
15
16
17
18
19
20
GRN
RED
AVDD
Analog Power Supply
Rev. 1.20
3
XRD9827
ELECTRICALCHARACTERISTICS
Test Conditions: AVDD=DVDD=5V, ADCCLK=6MHz, 50% Duty Cycle, TA=25°C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit Conditions
Power Supplies
AVDD
DVDD
IDD
Analog Power Supply
3.0
3.0
25
3.3
3.3
40
5.5
5.5
60
V
V
(Note 2)
Digital I/O Power Supply
Supply Current
DVDD < AVDD
mA VDD=5V
IDDPD
Power Down Power Supply Current
50
µA VDD=5V
ADC Specifications
RES
Fs
Resolution
12
12
Bits
MSPS
LSB
Maximum Sampling Rate
Differential Non-Linearity
Integral Non-Linearity
Monotonicity
DNL
INL
±0.5
±1.0
LSB
MON
VRT
Yes
Top Reference Voltage
Bottom Reference Voltage
Differential Reference Voltage
(VRT - VRB)
3.50
0.3
3.70
3.90
780
V
V
V
VRB
AVDD/10
0.67AVDD
DVREF
RL
Ladder Resistance
300
600
Ω
PGA & Offset DAC Specifications
PGARES
PGAGMIN
PGAGMAX
PGAGD
VBLACK
PGA Resolution
6
Bits
Minimum Gain
0.950
9.5
1.0
1.050
10.50
V/V
Maximum Gain
10.0
0.14
V/V
Gain Adjustment Step Size
Black Level Input Range
Offset DAC Resolution
Minimum Offset Adjustment
Maximum Offset Adjustment
Minimum Offset Adjustment
Maximum Offset Adjustment
Offset Adjustment Step Size
V/V
-100
8
500
mV DC Configuration
Bits
DACRES
OFFMIN
-250
+500
-450
+350
-200
+600
-400
+400
3.14
-150
+700
-350
+450
mV Mode 111, D5=0 (Note 1)
mV Mode 111, D5=0
mV Mode 111, D5=1 (Note 1)
mV Mode 111, D5=1
mV
OFFMAX
OFFMIN
OFFMAX
OFF∆
Note 1: The additional ±100 mV of adjustment with respect to the black level input range is needed to compensate
for any additional offset introduced by the XRD9827 Buffer/PGA internally.
Note 2: It is not recommended to operate the part between 3.6V and 4.4V.
Rev. 1.20
4
XRD9827
ELECTRICALCHARACTERISTICS(CONT'D)
Test Conditions: AVDD=DVDD=5V, ADCCLK=6MHz, 50% Duty Cycle, TA=25°C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Buffer Specifications
IIL
Input Leakage Current
100
nA
pF
V
CIN
Input Capacitance
10
VINPP
AC Input Voltage Range
0
0
AVDD-1.4
CIS AC; INT VDCREF
Config Reg
=> XXX010XX
Gain=1 (Note 1)
CCD AC; INT VDCREF
Config Reg
AC Input Voltage Range
DC Input Voltage Range
DC Input Voltage Range
DVREF
V
V
V
=> XXX011XX
Gain=1 (Note 1)
CIS DC; INT VDCREF
Config Reg
VIN
-0.1
AVDD-1.4
=> XXX000XX
Gain=1 (Note 2)
CIS DC; EXT VDCREF
Config Reg
V
DCEXT-0.1
VDCEXT+
DVREF
=> XXX100XX
Gain=1 (Note 3)
VDCEXT+DVREF < AVDD
VDCEXT
External DC Reference
0.3
AVDD/2
V
CIS DC; EXT VDCREF
Config Reg
=> XXX100XX
VINBW
VINCT
Input Bandwidth (Small Signal)
Channel to Channel Crosstalk
10
MHz
dB
-60
-50
fin=3MHz
Internal Clamp Specifications
VCLAMP
Clamp Voltage
AGND
VRT
50
mV
V
CIS (AC) Config
CCD (AC) Config
3.5
10
RINT
ROFF
Clamp Switch On Resistance
Clamp Switch Off Resistance
100
150
Ω
MΩ
Note 1: VINPP is the signal swing before the external capacitor tied to the MUX inputs.
Note 2: The -0.1V minimum is specified in order to accommodate black level signals lower than the external DC
reference (clamp) voltage.
Note 3: The VDCEXT-0.1V minimum is specified in order to accommodate black level signals lower than the external DC
reference voltage.
Rev. 1.20
5
XRD9827
ELECTRICALCHARACTERISTICS(CONT'D)
Test Conditions: AVDD=DVDD= 5V, ADCCLK=6MHz, 50% Duty Cycle, TA=25°C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
+2.3
+5.0
Unit
Conditions
Note 1
System Specifications (MUX + Buffer + PGA + ADC)
SYSDNL
SYSLIN
SYSGE
IRN
System DNL
-1.0
-5.0
±0.5
±6.0
LSB
LSB
%
System Linearity
System Gain Error
Input Referred Noise
Input Referred Noise
1.5
0.5
mVrms
mVrms
Gain=1
Gain=10
System Timing Specifications
tcklw
tckhw
tckpd
tsypw
trars
ADCCLK Low Pulse Width
50
70
120
30
0
83
83
ns
ns
ns
ns
ADCCLK High Pulse Width
ADCCLK Period
166
SYNCH Pulse Width
Rising ADCCLK to rising
SYNCH
SYNCH must rise equal to
or after ADCCLK, See Figure 18
tclpw
CLAMP Pulse Width
30
ns
Note 2
Write Timing Specifications
tsclkw
tdz
SCLK Pulse Width
40
20
20
0
ns
ns
ns
ns
ns
LD Low to SCLK High
Input Data Set-up Time
Input Data Hold Time
SCLK High to LD High
tds
tdh
tdl
50
ADC Digital Output Specifications
tap
tdv
tsa
tlat
tlat
Aperture Delay
Output Data Valid
SYNCH to ADCCLK
Latency
10
ns
ns
ns
40
15
3ch Pixel Md
8
6
cycles Config 00, 11
pixels Config 01, 10
Latency
Digital Input Specifications
VIH
VIL
IIH
Input High Voltage
AVDD-2.5
V
V
Input Low Voltage
1
High Voltage Input Current
Low Voltage Input Current
Input Capacitance
5
5
µA
µA
pF
IIL
CIN
10
Note 1: System performance is specified for typical digital system timing specifications.
Note 2: The actual minimum ‘tclpw’ is dependent on the external capacitor value, the CIS output impedance.
During ‘clamp’ operation, sufficient time needs to be allowed for the external capacitor to charge up to the
correct operating level. Refer to the description in Theory of Operation, CIS Config.
Rev. 1.20
6
XRD9827
ELECTRICALCHARACTERISTICS(CONT'D)
Test Conditions: AVDD=DVDD=5V, ADCCLK=6MHz, 50% Duty Cycle, TA=25°C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Digital Output Specifications
VOH
VOL
IOz
Output High Voltage
80
-10
2
(
%)DVDD
IL = 1mA
IL = -1mA
Output Low Voltage
20
10
(%)DVDD
Output High-Z Leakage Current
Output Capacitance
µA
COUT
SR
10
pF
Slew Rate (10% to 90% DVDD)
15
ns
CL = 10pF, DVDD = 3.3V
Rev. 1.20
7
XRD9827
THEORYOFOPERATION
CISConfiguration(ContactImageSensor)
The XRD9827 has two configurations for CIS applications. Each configuration is set by the control registers
accessed through the serial port.
Mode 1. DC Coupled
If the CIS does not have leading or trailing black pixels as shown in Figure 2, then DC couple the CIS output to the
XRD9827input.
Optically Shielded
Pixels
Valid Pixels
Figure 2. Typical Output CIS Mode
Adjust the offset of the CIS (-100 mV to 500 mV) by setting the internal registers of the XRD9827 to set the black
pixel value when the LEDs of the CIS are off. When the LEDs are on, use the XRD9827 Programmable Gain to
maximizetheADCsdynamicrange. Figure3showsatypicalapplicationforaCISwithanoffsetof-100mVto500mV.
Rev. 1.20
8
XRD9827
XRD9827
VDD
VRT
C
I
RED
M
U
X
R
L
N/C
N/C
N/C
S
VRB
Figure 3. Application with Offset in the Range (-100mv to 500mv)
The input is added to VRB before the signal passes
through the ADC. If the CIS output is zero, then the
output of the ADC will be zero code. This enables the
CIS to be referenced to the bottom ladder reference
voltage to use the full range of the ADC.
offsetrangeoftheXRD9827(seeOffsetControlDAC,
Pg. 28) set the internal mode registers to external
reference. An external reference voltage equal to the
value of the CIS offset voltage can be applied to
VDCEXT(Figure4)inordertomeetthedynamicrange
oftheXRD9827. Figure4isadiagramoftheXRD9827
in the external reference mode for CIS, DC coupled
applications.
SomeCISsensorshaveanoutputwithanoffsetvoltage
of greater than 500mV. If the CIS output is beyond the
Rev. 1.20
9
XRD9827
XRD9827
VDD
VRT
C
I
RED
M
U
X
N/C
N/C
S
RL
VDCEXT
DC
REFERENCE
VRB
Figure 4. Application with Offset Greater Than (-100mv to 500mv)
TheDCreferencevoltageappliedtoVDCEXTdoesnot
have to be accurate. The internal offset DAC voltage
is still used in this mode for fine adjustment. VDCEXT
cannot be used as an input from the CIS. Any signal
applied to VDCEXT will be subtracted from the output
signal of the multiplexer.
Rev. 1.20
10
XRD9827
VCC (5V - 15V)
19
18
DB7/LD
9
8
7
6
5
4
3
2
RED
GRN
DB6/SDATA
DB5/SCLK
DB4
N/C
N/C
DB3
AVDD
DB2
C
I
S
DB1
DB0
17
16
BLU
DIGITAL
ASIC
VDCEXT
11
ADCCLK
CLAMP
SYNCH
12
13
15
VREF+
0.1uF
AVDD
DVDD (3V - 5V)
1
20
14
AVDD
AGND
DVDD
DGND
10
XRD9827
AGND
DGND
Figure 5. Typical Application Circuitry CIS DC Coupled Non-Inverted Mode
Rev. 1.20
11
XRD9827
CIS Mode Timing -- DC Coupled
(CLAMP disabled)
Pixel N-1
Pixel N
tap
Pixel N+1
tap
CIS
tckpd
tckhw tcklw
ADCCLK
tdv
tdv
N-6
N-6
N-8
N-7
N-8
N-7
N-5
N-5
[5:0]
DB
MSB
LSB
LSB
MSB
MSB
LSB
LSB
[11:6]
MSB
Figure 6. Timing Diagram for Figure 5
ADCCLK
Events
↓
ADC Sample & PGA Start Tracking next Pixel
MSB Data Out
↑
LSB Data Out
HI
LO
ADC Track PGA Output
ADC Hold/Convert
Table 1.
Mode 2. AC Coupled
one side of the external capacitor to be set to ground.
Itthenislevelshiftedtocorrespondtothebottomladder
reference voltage of the ADC (Figure 7).
If the CIS signal has a black reference for the video
signal, an external capacitor CEXT is used. When
CLAMP(clamp)pinissethighaninternalswitchallows
Rev. 1.20
12
XRD9827
XRD9827
VDD
VRT
REXT
CEXT
RED
C
I
S
M
U
X
R
L
N/C
N/C
N/C
CLAMP
VRB
RINT
Figure 7. CIS AC Coupled Application
Therefore, Tc =1/RINTCEXT
This value corresponds to the black reference of the
imagesensor. WhentheCLAMPpinissetbacktolow,
the ADC samples the video signal with respect to the
black reference. The typical value for the external
capacitor is 100pF. This value should be adjusted
accordingtothetimeconstant(Tc)neededinaparticu-
larapplication. TheCLAMPpinhasaninternal150ohm
impedance (RINT) which is in series with the external
capacitor(CEXT).
If the input to the external capacitor has a source
impedance(REXT),then:
Tc=1/(RINT+REXT)CEXT
Rev. 1.20
13
XRD9827
VCC (5V - 15V)
19
18
17
16
15
9
8
7
6
5
4
3
2
DB7/LD
RED
DB6/SDATA
DB5/SCLK
100PF
DB4
N/C
N/C
N/C
GRN
DB3
DB2
C
I
S
DB1
DB0
BLU
DIGITAL
ASIC
11
VDCEXT
VREF+
ADCCLK
12
13
CLAMP
SYNCH
DVDD (3V - 5V)
1
AVDD
20
14
AVDD
AGND
DVDD
DGND
10
XRD9827
AGND
DGND
Figure 8. Typical Application Circuitry CIS AC Coupled Non-Inverted
Rev. 1.20
14
XRD9827
CIS Mode Timing -- AC Coupled
(CLAMP enabled)
Pixel N-1
Pixel N
tap
Pixel N+1
tap
CIS
tckpd
tckhw tcklw
ADCCLK
tdv
tdv
N-6
MSB
N-6
N-8
MSB
N-7
MSB
N-8
N-7
[5:0]
DB
N-5
MSB
N-5
LSB
LSB
LSB
LSB
[11:6]
tclpw
CLAMP
Figure 9. Timing Diagram for Figure 8
ADCCLK
Events
↓
ADC Sample & PGA Start Track of next Pixel
MSB Data Out
↑
LSB Data Out
HI
LO
ADC Track PGA Output
ADC Hold/Convert
Table 3.
CLAMP
Events
HI
PGA Tracks VCLAMP & CEXT is Charged to
VBLACK - VCLAMP, which is equal to VBLACK
PGA Tracks VINPP
LO
Table 4.
Rev. 1.20
15
XRD9827
Internal CIS Reference Circuit (DB 4 = 1)
The XRD9827 has an internal register reserved for
interfacing to the Canon CIS model number CVA-
60216K. When this register is selected, the VDCEXT
(Pin16)becomesanoutputvoltageof1.24volts. This
voltage can be directly connected to the VREF (Pin 5)
of the Canon sensor. This reduces the amount of
componentsneededforbiasingtheCanonCISsensor
(the external diodes and resistors typically used in this
applicationhavebeenincludedinsidetheXRD9827for
this mode of operation). Below is a typical application
circuitusingtheXRD9827andtheCanonCVA-60216K
CIS sensor.
VCC (5V)
CANON CIS
DVDD (3V - 5V)
SENSOR
VOUT
1
2
MODE
3
AGND
4
VCC
5
VREF
19
18
9
8
7
6
5
4
3
2
6
RED
GRN
DB7/LD
DB6/SDATA
DB5/SCLK
DB4
SP
7
CLK
8
N/C
N/C
DB3
DB2
DB1
DB0
LED COM
9
LED BLU
17
16
10
BLU
LED GRN
11
LED RED
VDCEXT
DIGITAL
ASIC
NPN
11
12
13
12
ADCCLK
CLAMP
SYNCH
FGND
47uF
DGND
15
VREF+
NPN
0.1uF
AGND
DVDD (3V - 5V)
AVDD
DGND
20
14
1
0.01uF
AVDD
AGND
DVDD
DGND
NPN
10
100uF
DGND
AGND
DGND
XRD9827
DGND
CVA-60216K
Figure 10. Typical Application Circuitry Internal CIS Reference Circuit Mode
CANONCISSensor,Model#CVA=60216k
Rev. 1.20
16
XRD9827
CIS Line-By-Line Rotating Gain and Offset
(Configuration DB1 = 1, DB0 = 1)
through line-by-line so that the gain and offset do not
havetobeloadedinbetweenlines. Belowisthetypical
application circuit and timing for this configuration.
Line-by-line rotating gain and offset minimizes the
amount of write cycles per scan. Pre-loaded values of
gain and offset can be loaded for each color before the
first line is scanned. Each gain and offset is cycled
VCC (5V - 15V)
19
9
RED
DB7/LD
8
7
6
5
4
3
2
DB6/SDATA
DB5/SCLK
DB4
18
GRN
DB3
DB2
DB1
DB0
C
I
S
17
BLU
DIGITAL
ASIC
16
N/C
VDCEXT
11
12
13
ADCCLK
CLAMP
SYNCH
15
VREF+
0.1uF
DVDD (3V - 5V)
AVDD
20
1
AVDD
DVDD
DGND
14
10
AGND
AGND
XRD9827
DGND
Figure 11. Typical Application Circuitry Internal CIS Rotating Gain
andOffsetLine-By-Line
Rev. 1.20
17
XRD9827
CIS Rotating Gain and Offset
Line-By-Line (Md 11)
CIS
Red Pixel Line Scan
Grn Pixel Line Scan
Blu Pixel Line Scan
ADCCLK
SYNCH
tsypw
tsa
GAIN/
Red Gain/Offset Cycle
Grn Gain/Offset Cycle
Blu Gain/Offset Cycle
OFFSET
Tri-State (SYNCH = LO)
LD
Reset Internal Mux Color to Red Channel (LD = 110YYYYYY11)
Y = Previous State
Note:
Figure 12. Timing Diagram for Figure 11
CCDConfiguration(ChargeCoupledDevice)
Mode 1. AC Coupled
In the CCD configuration of operation, an external
capacitor needs to be chosen according to the equa-
tionsbelow.Thetypicalvaluefortheexternalcapacitor
is 100pF. This value should be adjusted according to
the time constant (Tc) needed in a particular applica-
tion. The CLAMP pin has an internal 150 ohm imped-
ance(RINT)whichisinserieswiththeexternalcapacitor
(CEXT).
WhenCLAMP(clamp)pinissethighaninternalswitch
allows one side of the external capacitor to be set to
VRT (Figure 13). This value corresponds to the black
referenceoftheCCD. WhentheCLAMPpinissetback
to low, the ADC samples the video signal with respect
to the black reference. The difference between the
black reference and the video signal is the actual pixel
value of the video content. Since this value is refer-
enced to the top ladder reference voltage of the ADC a
zero input signal would yield a full scale output code.
Therefore, the output of the conversion is inverted
(internally) to correspond to zero scale output code.
Therefore, Tc =1/RINTCEXT
If the input to the external capacitor has a load imped-
ance (REXT), then
Tc=1/(RINT+REXT)CEXT
Rev. 1.20
18
XRD9827
XRD9827
VDD
CLAMP
VRT
AREA
or
RED
LINEAR
CCD
M
U
X
N/C
N/C
N/C
RL
VRB
Figure 13. CCD AC Coupled Application
Area or Linear CCD Applications
pixelvalueshavebeensampled,thegainandoffsetare
adjustedatthebeginningofthenextline. Forexample,
if there is a line-to-line variation between the black
reference pixels, the offset is adjusted. The gain is
always adjusted for the highest color intensity.
Figure 13 is a block diagram for applications with Area
or Linear CCDs (The timing for Area CCDs and B/W
CCDs is the same). For Area or Linear CCD applica-
tions, a global offset is loaded into the serial port at the
beginning of a line. The gain is set to adjust for the
highest color intensity of the CCD output. Once the
Rev. 1.20
19
XRD9827
VCC (5V - 15V)
19
18
17
16
15
9
8
7
6
5
4
3
2
RED
DB7/LD
DB6/SDATA
DB5/SCLK
DB4
100PF
N/C
N/C
N/C
GRN
DB3
DB2
DB1
DB0
C
C
D
BLU
DIGITAL
ASIC
11
12
13
VDCEXT
VREF+
ADCCLK
CLAMP
SYNCH
DVDD (3V - 5V)
AVDD
20
14
1
AVDD
AGND
DVDD
DGND
10
AGND
XRD9827
DGND
Figure 14. Typical Application Circuitry Single
Channel CCD AC Coupled Inverted Mode
Rev. 1.20
20
XRD9827
AREA, LINEAR or B/W CCD -- AC Coupled
(CLAMP Enabled)
Pixel N-1
Pixel N
Pixel N+1
CCD
Channel N
tckpd
tckhw tcklw
tap
tap
ADCCLK
tclpw
CLAMP
[5:0]
tdv
tdv
N-6
N-7
MSB
N-8
MSB
N-7
N-6
N-8
LSB
DB
MSB
LSB
LSB
[11:6]
Figure 15. Timing Diagram for Figure 14
Triple Channel CCD Application
Thegainandoffsetisautomaticallyrotatedtoadjustfor
each channel input. The MSBs are available on the
output bus on the falling edge of ADCCLK. The LSBs
are available on the rising edge of ADCCLK.
Figure 16 is a block diagram for pixel-by-pixel applica-
tions with triple channel CCDs. During the optically
shielded section of a pixel, CLAMP must go high to
storetheblackreferenceoneachcapacitortotheinput.
Rev. 1.20
21
XRD9827
XRD9827
VDD
CLAMP
VRT
RED/GRN/BLU
C
C
D
M
U
X
RL
N/C
VRB
Figure 16. CCD AC Coupled Application
Rev. 1.20
22
XRD9827
VCC (5V - 15V)
19
18
17
16
15
9
8
7
6
5
4
3
2
RED
DB7/LD
DB6/SDATA
DB5/SCLK
DB4
100PF
100PF
100PF
GRN
DB3
DB2
DB1
DB0
C
C
D
BLU
DIGITAL
ASIC
11
12
N/C
VDCEXT
VREF+
ADCCLK
CLAMP
SYNCH
13
AVDD
DVDD (3V - 5V)
20
14
1
AVDD
AGND
DVDD
DGND
10
AGND
XRD9827
DGND
Figure 17. Typical Application Circuitry Triple Channel CCD
AC Coupled Inverted Mode
Rev. 1.20
23
XRD9827
PIXEL-BY-PIXEL 3 CHANNEL CCD -- AC Coupled
(CLAMP Enabled)
RED
N Pixel
N+1 Pixel
GRN
N Pixel
N+1 Pixel
tclp=10ns
tclp=10ns
BLU
N Pixel
N+1 Pixel
tap
CONVERT
BLU (N)
CONVERT
GRN (N)
TRACK
RED (N)
CONVERT
RED (N)
TRACK
GRN (N)
TRACK
BLU (N)
TRACK
RED (N+1)
CONVERT
RED (N+1)
ADCCLK
CLAMP
trars
Simultaneous
Sample
CLAMP
tdv
tdv
RED (N-6)
tdv
RED (N-6)
tdv
GRN (N-6)
tdv
GRN (N-6)
MSB
BLU (N-6)
LSB
BLU (N-6)
MSB
LSB
LSB
MSB
DATA
tsa
tsypw
SYNCH
Figure 18. Timing Diagram for Figure 17
Events
ADCCLK
3rd ↓
Simultaneous RED/GRN/BLU Sample Every 3rd CLK.
Convert RED, S/H GRN, S/H BLU.
MSB Data Out
All ↓
↑
LSB Data Out
HI
LO
ADC Track PGA Output
ADC Hold/Convert
CLAMP
HI
Events
Internal Clamp Enabled
LO
SYNCH
HI
Internal RED/GRN/BLU Tracking Enabled
Events
Reset Internal Mux to Red, Output Bus is Tri-stated
Increment Mux Color on Falling Edge of ADCCLK
LO
Table 5.
Rev. 1.20
24
XRD9827
VRT
S1, S2 and S3 close when
CLAMP is high and open
when CLAMP is low
S1 S2 S3
From CCD RED
Channel
S6
S7
S8
C
C
C
EXT
EXT
EXT
R
G
B
12-Bit ADC
S9 closes at rising edge and opens
at falling edge of ADCCLK
From CCD
S4
VRT - V
PIX
GRN Channel
-
S9
PGA
+
T/H
T/H
From CCD BLU
Channel
S5
VRT
VCDS = PGAG * [VRT - (VRT - VPIX)]
= PGAG * VPIX
T/H
XRD9827
VBLK
CCD
Waveform
V
PIX
V
-
VBLK
PIX
CLAMP
S8 Opens, S4,
S5 and S6
S8 Opens, S4,
S6 opens, S7
closes at this
rising edge
S7 opens, S8
closes at this
rising edge
S4 and S5 open
at this falling
edge
S5 and S6
close at this
rising edge
close at this
rising edge
Track
RED
Convert
RED
Track
GRN
Convert
GRN
Track
BLU
Convert
BLU
Track
RED
Convert
RED
ADCCLK
Figure 19. CDS Timing (Triple Channel)
Mode:11000001110
Rev. 1.20
25
XRD9827
Mode 2. DC Coupled
PGA GAIN TRANSFER CURVE
GAIN 1 - 10
10
9
8
7
6
5
4
3
2
1
Typical CCDs have outputs with black references.
Therefore, DC Coupled is not recommended for CCD
applications.
OffsetControlDAC
TheoffsetDACiscontrolledby8bits. Theoffsetrange
is800mVrangingfrom-200mVto+600mV(whenDB5
is set to 0) and -400 mV to +400 mV (when DB5 is set
to 1). Therefore, the resolution of the 8-Bit offset DAC
is 3.14 mV. However, the XRD9827 has +/- 100 mV
reserved for internal offsets. Therefore, the effective
rangeforadjustingforCISoffsetsorblackreferenceis
600 mV. The offset adjustment is used primarily to
correctforthedifferencebetweentheblacklevelofthe
imagesensorandthebottomladderreferencevoltage
(VRB) of the ADC. By adjusting the black level to
correspondtoVRB,theentirerangeoftheADCcanbe
used.
0
10
20
30
40
50
60
CODE
Figure 20. Transfer Curve for the 6-Bit PGA
After the signal is level shifted to correspond with the
bottom ladder reference voltage, the system can be
calibrated such that a white video pixel can represent
thetopladderreferencevoltagetotheADC. Thisallows
for a full scale conversion maximizing the resolution of
the ADC.
IftheoffsetoftheCISoutputisgreaterthan500mVan
external reference can be applied to VDCEXT. The
external reference can be used to adjust for large
offsets only when the internal mode is configured
through the serial port.
AnalogtoDigitalConverter
The ADC is a 12-Bit, 10 MSPS analog-to-digital con-
verterforhighspeedandhighaccuracy. TheADCuses
a subranging architecture to maintain low power con-
sumption at high conversion rates. The output of the
ADC is on 8-bit databus. The 8-bit databus supports
6x6or8x4outputdata. ADCCLKsamplestheinputon
its falling edge. After the input is sampled, the MSB is
latched to the output drivers. On the rising edge of the
ADCCLK, theLSBislatchedtotheoutputdrivers. The
outputneedstobedemultiplexedwithexternalcircuitry
or a digital ASIC. There is an 8 clock cycle latency
(Config 00, 11) or 6 pixel count latency (Config 01, 10)
fortheanalog-to-digitalconverter.
Since the offset DAC adjustment is done before the
gain stage, it is gain-dependent. For example, if the
gain needs to be changed between lines (red to blue,
etc.), the offset is calibrated before the signal passes
through the PGA.
PGA (Programmable Gain Amplifier) DAC
The gain of the input waveform is controlled by a 6-Bit
PGA. The PGA is used along with the offset DAC for
the purpose of using the entire range of the ADC. The
PGA has a linear gain from 1 to 10. Figure 20 is a plot
of the transfer curve for the PGA gain.
The VRT and VRB reference voltages for the ADC are
generated internally, unless the external VRT is se-
lected. In the external VRT mode, the VRT voltage is set
through the VREF+ pin. This allows the user to select
the dynamic range of the ADC.
Rev. 1.20
26
XRD9827
SerialLoadControlRegisters
The serial load registers are controlled by a three wire
serialinterfacethroughthebi-directionalparallelportto
reducethepincountofthisdevice. WhenSYNCHisset
to high, the output bus is tri-stated and the serial
interface is activated. DB7/LD, DB5/SCLK and DB6/
SDATA are the three input signals that control this
process. The DB7/LD signal is set low to initiate the
loading of the internal registers.
ThefirstthreeMSBschoosewhichinternalregisterwill
be selected. The remaining 8 LSBs contain the data
needed for programming the internal register for a
particularconfiguration.
Power-UpStateoftheInternalRegisters
The control register settings upon initial power-up are
forCIS,DCCoupledconfiguration(VRT issettointernal,
InputDCReference=AGNDandtheinputtotheADCis
selected through the RED channel). Gain is unity and
Offsetissettozero. Thetestmodesaredisabledinthe
power-upstate.
Thereareinternal registersthatareaccessedviaan11-
bit data string. Data is shifted in on the rising edge of
SCLK and loaded to the registers on the rising edge of
LD. The data on pin DB6/SDATA is latched automati-
cally after eleven DB5/SCLKs have been counted. If
elevenclocksarenotpresentonDB5/SCLKbeforethe
DB7/LD signal returns high, no data will be loaded into
the internal registers. If more than 11 clocks are
present on DB5/SCLK, the additional clocks will be
ignored. The data corresponding to the first eleven
DB5/SCLKs will be loaded only.
SYNCH
tsclkw
DB7/LD
tdl
tdz
DB5/SCLK
tds tdh
S1
S2
S0
D7
D2
D1
D0
DB6/SDATA
Figure 21. Write Timing
Rev. 1.20
27
XRD9827
OutputBusFormat
ADCOutput—>DO11(MSB):DO0(LSB)
DB7
DO11
DO5
DB6
DO10
DO4
DB5
DO9
DO3
DB4
DO8
DO2
DB3
DO7
DO1
DB2
DO6
DO0
DB1
X
X
DB0
X
X
MSB
LSB
Table 8. 6 MSB + 6 LSB Output Bus Format
DB7
DO11
DO3
DB6
DO10
DO2
DB5
DO9
DO1
DB4
DO8
DO0
DB3
DO7
X
DB2
DO6
X
DB1
DO5
X
DB0
DO4
X
MSB
LSB
Table 9. 8 MSB + 4 LSB Output Bus Format
Rev. 1.20
28
XRD9827
ControlRegisters
Function
(Register
S2/S1/S0)
D7
D6
D5
D4
D3
D2
D1
D0
Power-up
State
(Note1)
Red Gain
(000)
G5
(MSB)
G4
O6
G4
G3
O5
G3
G2
O4
G2
G1
O3
G1
G0
(LSB)
X
O1
X
X
000000XX
01000000
000000XX
Red Offset
(001)
O7
(MSB)
O2
O0
(LSB)
Grn Gain
(010)
G5
(MSB)
G0
(LSB)
X
Grn Offset
(011)
O7
(MSB)
O6
G4
O6
O5
G3
O4
G2
O4
O3
G1
O2
O1
X
O0
(LSB)
01000000
000000XX
Blu Gain
(100)
G5
(MSB)
G0
(LSB)
X
Blu Offset
(101)
O7
(MSB)
O5
O3
O2
O1
O0
(LSB)
01000000
00000000
Mode
(110)
POWER
DOWN
DIGITAL
RESET
VRT
INPUTDC
REFERENCE
DC/AC
SIGNAL
POLARITY
SIGNAL
CONFIGURATION
(VDCREF
)
0:NORMAL
0: NO RESET
0:INTERNAL
1:EXTERNAL
0:INTERNAL
(VDCREF=AGND)
1:EXTERNAL
0: DC
1: AC
0: Non-
Inverted
(CIS)
1: Inverted
(CCD/CIS)
00:Single-Channel
RED input/gain/offset
1:
1:RESET
(REGISTERS
ARERESETTO
POWER-UP
STATES)
POWER
DOWN
(VDCREF=VDCEXT
)
01:Single-Channel
REDinput
RED/GRN/BLU
gain/offset cycle
pixel-by-pixel
10:Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
pixel-by-pixel
11:Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
line-by-line
Mode
&Test
(111)
OUTPUT
BUS
CONTROL
OUTPUT
DISABLE
OFFSET
DAC
RANGE
INTERNALCIS
REFERENCE
CIRCUIT
TEST4
TEST3
TEST2
TEST1
00000000
0: 6 MSB +
6 LSB
0:OUTPUTS
ENABLED
0:-200mV to
+600mV
0:NORMAL
0: TEST4
0:TEST3
0:TEST2 0:NORMAL
DISABLED DISABLED DISABLED
1: 8 MSB +
4 LSB
1:OUTPUTS
DISABLED
1:-400mV to
+400mV
1:REFERENCE
CIRCUIT
ENABLED
1:OUTPUT 1:OUTPUT
OF BUFFER OFPGA
1:INPUT
OFADC
TIEDTO
GRN
1:TEST1
ENABLED
TIEDTO
BLU
TIEDTO
VDCEXT
Note : These are the control register settings upon initial power-up. The previous register settings are retained
following a logic power-down initiated by the power down bit except the signal configuration. When
de-selecting the power down bit (D7 = 0, Normal), the signal configuration (D5 and D0) has to be
reprogrammed.
Rev. 1.20
29
XRD9827
Rev. 1.20
30
XRD9827
20 LEAD SHRINK SMALL OUTLINE PACKAGE
(5.3 mm SSOP)
Rev. 2.00
D
20
11
E
H
1
10
C
A2
A
Seating
Plane
α
e
B
A1
L
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
0.079
0.006
0.073
0.015
0.010
0.296
0.221
MIN
1.70
0.05
1.65
0.22
0.09
6.90
5.00
MAX
2.00
0.15
1.85
0.38
0.25
7.50
5.60
A
A1
A2
B
C
D
0.067
0.002
0.065
0.009
0.004
0.272
0.197
E
e
0.0256 BSC
0.65 BSC
H
L
0.292
0.022
0.323
0.037
7.40
0.55
8.20
0.95
α
0°
8°
0°
8°
Note: The control dimension is the inch column
Rev. 1.20
31
XRD9827
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for in accuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to
significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2000EXARCorporation
DatasheetMay2000
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.20
32
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