XRT5794IJ-F [EXAR]
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| 型号： | XRT5794IJ-F |
| 厂家： | 
EXAR CORPORATION |
| 描述： | 暂无描述 |
| 文件： | 总11页 (文件大小：1111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XRT5794ES
Evaluation
System
GENERAL DESCRIPTION
balanced 120Ω operation are one quarter inch, 3-circuit
audio type jacks. Equipmentconnections should be made
with shielded twisted pair patch cords. The signal applied
to any inputs must be a CCITT G.703 compliant pulse that
may be attenuated by a twisted-paircable. The XR-T5794
exceeds G.703 maximum cable loss of requirement of 6.0
dB at 1.024 MHz.
The XR-T5794 demo board is
a 4.75” x 9.75”
double-sided circuit card that provides the support
circuitry necessary for a comprhensive evaluation of the
XR-T5794 CMOS Quad E1 Line Interface IC. three
board-mounted DIP switches allow complete testing of all
loop back, monitor, and transmitter power-down features.
The demo board is normally supplied configured for 120Ω
balanced E1 operation. However, the information
contianed in this manual enables the user to modify the
hardware for E1 unbalanced 75Ω cable service, or T1
balanced 100Ω use.
Similarly, transmitter outputs are labeleds TXOUT1
through TXOUT4 for the four channels. The monitor
channel output is labeled MONOUT. Connector types
and connection methods are identical to those specified
above for the recieve side. The transmitter output, when
terminated by a 120Ω resistor, is a pulse meeting the
G.703 template requirements. During demo board
evaluation, all ransmitters, including the monitor channel,
that are not powered down should be connected to either
a properly terminated cable, a piece of test equipment
contianing a termination, or a 120Ω load resistor.
BOARD OPERATION
Figures 1, 2 and Table 2 are the board component layout,
circuit diagram, and parts list respectively. The Demo
Board uses the same pin function and signal names as
the XR-T5794 data sheet. This user’s manual is designed
to be used in conjuction with the XR-T5794 data sheet.
The following description if for a demo board set up for
balanced 120 Ω E1 use. It also applies to the other modes
of operation if the appropriate impedence, cable type, and
signal source changes are made.
Equipment-Side Signal Connections
For
convenience, access
to
the
logic-level
equipment-side signals is provided by two groups of turret
terminals and also by two ribbon cable connectors. The
terminals are convient for simple tests while the ribbon
cable connectors reduce the amount of wiring necessary
to connect the entire equipment side of the demo board to
customer equipment.
Power Requirements
Power connections are made to banana jacks located in
the upper left hand corner of the board. Power supply
requirements are:
Header P1 and a group of terminals that provide channel
1 and 2 I/O are located below the XR-T5794. For
channels 3 and 4, P2 and a second group of pins are
located above the XR-T5794. P1 and P2 are dual-row 26
pin headers with only the odd-nimbered pins used to carry
signals. Even-numbered pins are grounded to minimize
ribbon cable crosstalk. Pin 13 is also grounded to provide
isolation between the transmit and receive directions.
V
DD
V
SS
= +5.0 V ‵ 5% at 850 mA maximum
= - 5.0 V ‵ 5% at 850 mA minimum
Line-Side Signals
Receiver signal inputs are labeled RXIN1 through RXIN4
for the four channels. The connectors supplied for
Rev. 2.00
5
XRT5794ES
For P1 and P2 respectively, Table 1 and 2 presented below give the header pin, signal symbol, the corresponding
XR-T5794 pin, and a brief description of the signal present.
P1 Pin
1
Symbol
LOS1
T5794 Pin
Signal Description
39
40
45
46
47
48
53
54
55
56
57
58
Channel 1 - Receive Loss of Signal Output
Channel 2 - Receive Loss of Signal Output
Channel 1 - Receive Negative Rail Output
Channel 1 - Receive Positive Rail Output
Channel 2 - Receive Negative Rail Output
Channel 2 - Receive Positive Rail Output
Channel 1 - Transmit Negative Rail Input
Channel 1 - Transmit Positive Rail Input
Channel 1 - Transmit Clock Input
3
LOS2
5
RXNEG1
RXPOS1
RXNEG2
RXPOS2
TXNEG1
TXPOS1
TXCLK1
TXNEG2
TXPOS2
TXCLK2
7
9
11
15
17
19
21
23
25
Channel 2 - Transmit Negative Rail Input
Channel 2 - Transmit Positive Rail Input
Channel 2 - Trnasmit Clock Input
Table 1. Header P1 - Channel 1 and 2 Equipment Side I/O Connections
P2 Pin
1
Symbol
TXCLK4
TXPOS4
TXNEG4
TXCLK3
TXPOS3
TXNEG3
RXPOS3
RXNEG3
RXPOS$
RXNEG4
LOS4
T5794 Pin
Signal Description
12
13
14
15
16
17
22
23
24
25
30
31
Channel 4 - Transmit Clock Input
3
Channel 4 - Transmit Positive Rail Input
Channel 4 - Transmit Negative Rail Input
Channel 3 - Transmit Clock Input
5
7
9
Channel 3 - Transmit Positive Rail Input
Channel 3 - Transmit Negative Rail Input
Channel 3 - Receive Positive rail Output
Channel 3 - Recevie Negative Rail Output
Channel 4 - Receive Positive Rail Output
Channel 4 - Receive Negative Rail Output
Channel 4 - Receive Loss of Signal Output
Channel 3 - Receive Loss of Signal Outpu
11
15
17
19
21
23
25
LOS3
Table 2. Header P2 - Channel 3 and 4 Equipment Side I/O Connections
Rev. 2.00
6
XRT5794ES
Equipment-Side Signal Characteristics
tranmitter output. The signal applied to a TXPOS input
must be wider that the positive half cycle of the
corresponding TXCLK, and must also meet the set-up
and hold time specifiedin the XR-T5794 datasheet. When
these conditions are met, the pulse width at the
transmitter output TXOUT is determined by the positive
going half-cycle of TXCLK .
All equipment-side connections at P1 and P2 are TTL
logic-level compatible for the inputs and outputs. Specific
signal types present at these pins are as follows.
LOS1 Through LOS4
These pins are the loss signal outputs (LOS) for the for
receive channels. A LOS output will go to a logic 1 state
when the input applied to the corresponding receiver is
less that the LOS threshold voltage.
TXNEG1 Through TXNEG4
These pins are the negative rail input for the dual-rail
RXPOS1 Through RXPOS4
transmit data for the four transmit channels.
A
positive-going pulse at a TXNEG input will produce a
negative bipolar output pulse at the corresponding
transmitter output. The pulse width conditions described
above for the TXPOS input also apply to TXNEG.
The signal present at these pins is the positive half of the
dual-rail receive data. A positive bipolar input pulse at a
receiver input will produce a positive-going pulse at the
corresponding RXPOS output. Data pulse width at an
RXPOS output is approximately equal to the width of the
pulse applied to the reciever input at its 50% amplitude
point.
Operation Without TXCLK
Operation without TXCLK is possible if this pin is
connected to either DGND or DVDD. Transmit output
pulse width in this mode of operation is determined by the
widths of the pulsed applied to the TXPOS and TXNEG
inputs. Therefore, the data applied to these inputs must
be one-half width return-to-zero (RZ) pulses in order to
produce a normal width bipolar transmit output pulse.
RXNEG1 Through RXNEG4
The signal present at these pins is the negative half of the
dual-rail receive data. A negative bipolar input pulse at a
receiver input will produce a positive-going pulse at the
corresponding RXNEG output. Data pulse width is the
same as described above for the RXPOS output.
DIP Switch Settings
TXCLK1 Through TXCLK4
On the demo board, the logic levels presented at all
control-type XR-T5794 input pins may be set with DIP
switches. The following circuit is used to switch logic
levels. Each IC input that is to be programmed has a 10 K
W pull-up resistor connected to VDD. A SPAT DIP switch
section is also connected between this input and ground.
Therefore, when the switch lever is in the “ON” position as
marked on the switch body, the IC input is at a “Logic 0”
level. For convenience, a small “1” and “0” that indicate IC
pin logic level to switch position correspondence is
printed on the borad at the top end of each DIP switch.
These pins are the transmit clock inputs of four transmit
channels. For a specific channel, TXCLK is a 2.048 MHz
50% duty cycle square wave that is synchronized with the
data to be transmitted over that channel.
TXPOS1 Through TXPOS4
These pins are the positive rail inputs for the dual-rail
transmit data for the four tranmit channels.
positive-going pulse at a TXPOS input will produce a
positive bipolar outout pulse at the corresponding
A
Rev. 2.00
7
XRT5794ES
Tables 3, 4 and 5, which are given below, list the switch position, XR-T5794 pin controlled, signal symbol, and
function of the three demo board DIP switches.
Switch Position
IC Pin
Symbol
Switch Setting Function
1
33
MSEL0
Off
On
Off
On
On
Off
MSEL0 = Logic 1
MSEL0 = Logic 0
MSEL1 = Logic 1
MSEL1 = Logic 0
MSEL2 = Logic 1
MSEL2 = Logic 0
2
3
34
37
MSEL1
MSEL2
4
(Not Used)
Table 3. Dip Switch S1 Functions
Switch Position
IC Pin
Symbol
Switch Setting Function
1
61
TXEN2
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
Transmitter 2 Output Enabled
Transmitter 2 Output High Impedence
Transmitter 1 Output Enabled
Transmitter 1 Output High Impedance
120 W Mode Selected
2
3
4
5
6
7
62
60
52
51
50
42
TXEN1
ZSEL
75 W Mode Selected
LPEN2
LPEN1
E1/T1B
LPMOD2
Channel 2 Loop Mode Enabled
Channel 2 Normal Operation
Channel 1 Loop Mode Enabled
Channel 1 Normal Operation
E1 Mode Selected
T1 Mode Selected
Channel 2 Remote Loop Back Mode
Selected
On
Off
Channel 2 Local Loop back Mode Selected
8
41
LPMOD1
Channel 1 remote Loopback Mode
Selected
On
Channel 1 Local Loop Back Mode
Selected
Table 4. Dip Switch S2 Functions
Rev. 2.00
8
XRT5794ES
Switch Position
IC Pin
Symbol
Switch Setting Function
1
28
LPMOD3
Off
On
Off
On
Channel 3 Remote Loop Back Mode
Selected
Channel 3 Local Loop Back Mode
Selected
2
27
LPMOD4
Channel 4 Remote Loop Back Mode
Selected
Channel 4 Remote Loop Back Mode
Selected
3
(Not Used)
4
5
6
7
8
19
18
10
9
LPEN3
LPEN4
MONEN
TXEN3
TXEN4
Off
On
Off
On
Off
On
Off
On
Off
On
Channel 3 Loop Mode Enabled
Channel 3 Normal Operation
Channel 4 Loop Made Enabled
Channel 4 Normal Operation
Monitor Output Enabled
Monitor Output High Impedance
Transmitter 3 Output Enabled
Transmitter 3 Output High Impedance
Transmitter 4 Output Enabled
Transmitter 4 Output High Impedance
8
Table 5. Dip Switch S3 Functions
HARDWARE CONFIGURATION CHANGES
the nine clip-on jumpers so that they now connect the top
two pins on the 3-pin headers labeled E1 through E9.
This section describes hardware changes necessary for
different modes of operation. It assumes that the demo
board is initially configured for 120Ω balancedE1 service.
Balanced or unbalanced cable operation is chosen by a
clip-on jumper for each channel and by the installation the
appropriate types of input and output connectors. T1/E1
rate selection is done by one DIP switch section.
100/120Ω impedance selection for balanced operation
involoves a resistor change.
75Ω Unbalanced E1 Operation
Replace the 3-circuit audio type jacks used on the
line-side inputs and outputs with BNC connectors (9
total). Wire the center pin of each BNC connector to the
adjacent circuit borad pad labeled “75”.
100Ω Balanced T1 Operation
Replace 120Ω resistor R2, R4, R6 and R8, with 100Ω
parts.
With the demo board oriented so that the power
connections are in the upper left hand corner, reposition
Replace 68Ω resistors R10, R12, R14, R16 and R18, with
62Ω parts.
Rev. 2.00
9
XRT5794ES
Qty.
4
Reference
T1,2,3,4
Description
Supplier
Input Transforner, 1:1 Ratio
Output Transformer, 1:1.266 Ratio
75Ω, 1/4W, 1% Metal Film Resistor
121Ω, 1/4W, 1% Metal Film Resistor
Pulse Eng. PE-65834
Pulse Eng. PE-65839
5
T5,6,7,8,9
R1,3,5,7
R2,4,6,8
4
4
10
R9, 10, 11,12,13, 14, 15, 68.1Ω, 1/4W, 1% Metal Film Resistor
16, 17, 18
1
2
2
R19
R20, 21
C1, 2
10 K, 2%, 5 Resistor, Thick-film Network
10 K, 2%, 9 Resistor, Thick-film Network
22µF, 16 V, Electrolytic, Axial LEad, 5mm Dia., 2mm
Spacing
15
C3, 4, 5, 6, 7, 8, 9, 10, 11, 0.1 mF, 63 V, Z5U
12, 13, 14, 15, 16, 17
Dielectric, Axial lead, 0.1” Spacing, Panasonic
1
2
1
2
2
9
9
S1
4-Position DIP Switch
CTS
CTS
Amp
S2, 3
8-Position DIP Switch
68 Pin PLCC Socket
P1, P2
P1, P2
26 Pin Dual-Row Header, Gold Pins
26 Pin Ribbon Connector For Above
3 Pin Single-Row Header, Gold
Shorting Jumper For Above Header
E1, 2, 3, 4, 5, 6, 7, 8, 9
(Select option on E1
through E9)
9
Line-Side signal connec- 3-Conductor 1/4” Audio Jack, for 3/8” Hole (Connector for
tions
Balanced Line)
3
26
4
Banana Jacks, red, Blue, Black
(GND, VSS, VDD) Pins for Digital I/O Pads
Spacers to Elevate Board
4
4-40 x 5/16” Screws for Spacers
Table 6. XR-T5794 Demo Board Parts List
Rev. 2.00
10
XRT5794ES
4 T U O X T
5 7 0 2 1
3 T U O X T
5 7 0 2 1
T U O N O M
5 7 0 2 1
2 T U O X T
5 7 0 2 1
1 T U O X T
5 7 0 2 1
TXCLK4
TXCLK2
TXPOS4
TXNEG4
TXCLK3
TXPOS3
TXNEG3
TXPOS2
TXNEG2
TXCLK1
TXPOS1
TXNEG1
RXPOS3
RXNEG3
RXPOS4
RXNEG4
LOS4
RXPOS2
RXNEG2
RXPOS1
RXNEG1
LOS2
LOS3
LOS1
2 L E S M
1 L E S M
0 L E S M
*
1
0
*
R3
R4
R5
R6
R1
R2
R7
R8
75 120
RXIN4
75 120
RXIN3
75 120
RXIN2
75 120
RXIN1
Figure 1. XR-T5794 Demo Board Component Layout
Rev. 2.00
11
XRT5794ES
V
DD
R20 10K
T1
1
1 1
TIP
R19
10K
R2
E1
0.1µF
120
C13
R9 68
RING
2 34 5 6 1 9 8 76 5 4 3 2 2 34 5 6 7 8 910
0
16
15
14
13
12
11
10
9
TIP
TIP
1
2
1
3
PE 65834
8
1
2
3
4
3
1:1
7
2
2
T5
3
4
5
6
7
8
6
5
0.1µF
R10 68
E5
1
TIP
RING
TIP
8
9
10
11
PE 65839
0.1µF
7
6
5
4
3
2
1
C14
12
13
14
3
R11 68
T6
2
T2
TIP
TIP
15
16
R4
120
R12 68
1
E6
E2
RING
3 3 3
3 4 7
4 45 55 6 6 6
3 2 01 2 0 2 1
1 1 1 2 2
1
3
RING
PE 65839
0.1µF
PE 65834
8 9 0 8 9 7 8
C15
2
1:1
MMM
S S S
E E E
L L L
01 2
L LE L LZT T
T TML L L L
20
TIP
TIP
0.1µF
P P1 P PS X X
XXOP P P P
35
3
1
MM
O O
M M
O O
D D
4 3
R13 68
/ E EE E E
T NNLNN
1 1 2 1 2
EE NE E
NNE NN
4 3M4 3
36
V
2
T7
TIP
DD
D D
1 2
V
SS
R14 68
2
6
E7
TVDD
5
TVSS
RVSS
DVSS
AVSS
TVSS
TVSS
TVDD
AVDD
VDD
44
49
59
65
68
RING
TIP
11
PE 65839
C16
21
26
64
0.1µF
RVDD
TVDD
3
1
T3
R15 68
R16 68
2
T8
TIP
XR-T5794
TIP
R6
120
41
38
32
29
RXIN1
RXIN2
RXIN3
RXIN4
TXOUT1 63
TXOUT2 66
TXOUT3
TXOUT4
MOUT
E8
E3
2
RING
1
3
RING
PE 65834
4
7
1
PE 65839
0.1µF
1:1
C17
3
67
AGND
AGND
0.1µF
TIP
TIP
3
1
R17 68
R18 68
TIP
R R RR T T T T T T T T T TT T RRRR
X X X X X X X X X X X X XXX X X X XX
NP NP NP C NP C CP NCP N P NP N
T9
2
E9
C11
L L
LL
OOE O E O E OL E OL L OEL OE OE OEOO
S S GS GS GS K GS K K S GKS G S GS GSS
1 21 1 2 2 1 1 1 2 2 2 4 4 4 3 33 3 3 4 44 3
R5 75
RING
PE 65839
3 44 4 4 4 5 5 55 5 5 11 1 1 1 1 2 2 23 3 3
T4
9 05 6 7 8
2 3 4 5 6 7 2 3 4 5 01
34 56 7 8
TIP
R8
120
E4
2
RING
1
3
PE 65834
1:1
V
SS
0.1µF
V
DD
TIP
V
SS
C12
C2
10µF
C6
0.1µF
C7
C8
C1
+
C3
C4 C5
1 35 791 1 1 1 1 222
1 3 5 791 35
P1
1 3 5 7 91 1 1 1 1 222
1 3 57 91 3 5
+
0.1µF 0.1µF
R7 75
10µF
0.1µF 0.1µF
0.1µF
P2
11 1 1 1 22 22
1 1 1 1 1 22 22
24 6 8 02 4 6 8 024
6
2 4 6 8 0 2 4 6 8 0 24 6
Figure 2. XR-T5794 Demo Board Circuit Diagram
Rev. 2.00
12
XRT5794ES
Notes
Rev. 2.00
13
XRT5794ES
Notes
Rev. 2.00
14
XRT5794ES
Notes
Rev. 2.00
15
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EXAR
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