XRT81L27_技术文档

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XRT81L27

SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

NOVEMBER 2001

REV.1.1.0

FEATURES

GENERAL DESCRIPTION

• Seven (7) Independent E1 (CEPT) Line Interface

Units (Transmitter, Receiver, and Recovery)

The XRT81L27 is an optimized seven-channel, ana-

log, 3.3V, line interface unit, fabricated using low pow-

er CMOS technology. The device contains seven in-

dependent E1 channels, including data and clock re-

covery circuits. It is primarily targeted towards the

SDH multiplexers that accommodate TU12 Tributary

Unit Frames. Line cards in these units multiplex 21 E1

channels into higher SDH rates. Devices with seven

E1 interfaces such as the XRT81L27 provide the

most efficient method of implementing 21-channel

line cards. Each channel performs the driver and re-

ceiver functions necessary to convert bipolar signals

to logical levels and vice versa.

• Transmit Output Pulses that are Compliant with the

ITU-T G.703 Pulse Template Requirement for

2.048Mbps (E1) Rates

• On-Chip Pulse Shaping for both 75Ω and 120Ω line

drivers

• Receiver Can Either Be Transformer or Capacitive-

Coupled to the Line

• Detects and Clears LOS (Loss of Signal) Per ITU-T

G.775 and ETS 300 233 (programmable from Host)

• Compliant with the ITU-T G.823 Jitter Tolerance

Requirements

The receiver input accepts transformer or capacitor

coupled signals, while the transmitter is coupled to

the line using a 1:2 step-up transformer. The same

transformer configuration can be used for both bal-

anced 120 Ω and unbalanced 75 Ω interfaces. The

Receiver Loss of Original Detection is compliant to

G.775 and in Host Mode, the number of zeros re-

ceived before RLOS is declared can be increased to

4096 bits. This feature provides the user with the flex-

ibility to implement RLOS specifications that require

greater than G.775 requirements

• 3.3V operation with 5V Input compatibility

• Low power consumption

APPLICATIONS

• SDH and lPDH Multiplexers

• E1 Digital Cross-Connect Systems

• DECT (Digital European Cordless Telephone) Base

Stations

• CSU/DSU Equipment

FIGURE 1. BLOCK DIAGRAM

SDO

SDI

Microprocessor

Serial

Interface

(MSI)

SClk

CS

RST

LBM

Channel 6

Channel 5

LBEN

SR/DR

MODE

Channel 4

Global

Control

Channel 3

Channel 2

RClkP

ICT

Channel 1

MCLK

TClkP

Channel 0

MCLK

Timing

Control

TCLKP

TPOS_n

TCLK_n

TNEG_n

PDTx_n

TAOS_n

Encoded

PDATA

TTIP_n

TX

Pulse

Shaper

Timing

Control

Line

Driver

Encoder

MUX

Encoded

NDATA

TRING_n

Remote

Loopback

Digital

Loopback

Analog

Loopback

LOS

Detect

LOS_n

RPOS_n

RClk_n

RTIP_n

Peak

Detector

Receive

Equalizer

Data & Timing

Recovery

MUX

RRING_n

Decoder

RNEG_n

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

XRT81L27

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

FIGURE 2. PIN OUT OF THE XRT81L27

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

AVDD

AGND

TClk_1

RClk_6

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

RNEG_6/LCV_6

RPOS_6/RDATA_6

LOS_6

TPOS_1/TDATA_1

TNEG_1/CODE_1

TAOS_1

RClk_5

RNEG_5/LCV_5

RPOS_5/RATA_5

LOS_5

VDD

GND

TClk_3

TPOS_3/TDATA_3

TNEG_3/CODE_3

TAOS_3

TAOS_2

TxClk_5

TNEG_2/CODE_2

TPOS_2/TDATA_2

TClk_2

TPOS_5/TDATA_5

TNEG_5/CODE_5

TAOS_5

CS/B3

SClk/B2

SDI/B1

SDO/LBM

TAOS_6

TNEG_6/CODE_6

TPOS_6/TDATA_6

TClk_6

XRT81L27

TAOS_0

TNEG_0/CODE_0

TPOS_0/TDATA_0

TClk_0

GND

VDD

RPOS_2/RDATA_2

RNEG_2/LCV_2

RClk_2

GND

VDD

TAOS_4

TNEG_4/CODE_4

LOS_2

RPOS_0/RDATA_0

RNEG_0/LCV_0

ORDERING INFORMATION

PART NUMBER

PACKAGE

OPERATING TEMPERATURE RANGE

-40^°C to +85^°C

XRT81L27IV

128 Lead TQFP

2

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XRT81L27

SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV.1.1.0

TABLE OF CONTENTS

GENERAL DESCRIPTION .................................................................................................. 1

FEATURES ................................................................................................................................................... 1

APPLICATIONS .............................................................................................................................................. 1

Figure 1. Block Diagram ................................................................................................................... 1

Figure 2. Pin Out of the XRT81L27 ................................................................................................... 2

ORDERING INFORMATION ............................................................................................................... 2

TABLE OF CONTENTS ....................................................................................................... I

PIN DESCRIPTIONS ........................................................................................................... 3

TABLE 1: PIN NUMBER BY PIN NAME ..................................................................................................... 9

ELECTRICAL CHARACTERISTICS ................................................................................. 10

TABLE 2: ABSOLUTE MAXIMUM RATINGS ............................................................................................. 10

TABLE 3: DC ELECTRICAL CHARACTERISTICS ..................................................................................... 10

TABLE 4: TRANSMITTER ELECTRICAL CHARACTERISTICS ...................................................................... 10

TABLE 5: PER CHANNEL POWER CONSUMPTION INCLUDING LINE POWER DISSIPATION, TRANSMISSION AND

RECEIVE PATHS ALL ACTIVE .................................................................................................... 11

TABLE 6: RECEIVER ELECTRICAL CHARACTERISTICS ........................................................................... 11

Figure 3. Receive Output Timing ................................................................................................... 12

Figure 4. Transmit Input Timing ..................................................................................................... 12

TABLE 7: AC ELECTRICAL CHARACTERISTICS ..................................................................................... 12

THE HARDWARE MODE ............................................................................................................................... 13

THE HOST MODE ....................................................................................................................................... 13

1.0 The Microprocessor Serial Interface (MSI) ........................................................................................... 13

1.1 MICROPROCESSOR SERIAL INTERFACE DESCRIPTION. ............................................................................ 13

USING THE MICROPROCESSOR SERIAL INTERFACE (MSI) ............................................................................ 13

1.1.1 Selection Phase ........................................................................................................................ 13

1.1.2 Data phase of the (MSI) operation ........................................................................................... 14

Figure 5. Timing Diagram for the Microprocessor Serial Interface ............................................ 14

TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMING (SEE FIGURE 5) ............................................. 15

Figure 6. Microprocessor Serial Interface Data Structure ........................................................... 15

1.2 DESCRIPTION OF THE COMMAND REGISTERS ........................................................................................ 16

TABLE 9: MICROPROCESSOR REGISTER ADDRESS AND CONTROL ........................................................ 16

TABLE 10: COMMAND CONTROL REGISTER - ADDRESS 0000 - HEX 0X00 ........................................... 16

(COMMON TO ALL SEVEN CHANNELS) ............................................................................................ 16

TABLE 11: LOCAL LOOP-BACK REGISTERS - ADDRESS: 0001, HEX 0X01 ........................................... 17

TABLE 12: REMOTE LOOP-BACK REGISTERS - ADDRESS: 0010, HEX 0X02 ......................................... 17

TABLE 13: ANALOG LOOP-BACK REGISTERS - ADDRESS: 0011, HEX 0X03 ......................................... 17

TABLE 14: TAOS REGISTERS - ADDRESS: 0100, HEX 0X04 ............................................................... 17

TABLE 15: RAOS REGISTERS - ADDRESS: 0101, HEX 0X05 ............................................................... 17

TABLE 16: PDTX REGISTERS - ADDRESS: 0110, HEX 0X06 ................................................................ 18

1.3 OPERATION OF THE COMMAND CONTROL REGISTER BITS (ADDRESS: 0000, HEX 0X00) ........................ 18

TCLKP (BIT 0) ............................................................................................................................................ 18

RCLKP (BIT 1) ........................................................................................................................................... 18

CODE (BIT 2) ............................................................................................................................................ 18

SR/DR (BIT 3) ........................................................................................................................................... 18

MUTE (BIT 4) ............................................................................................................................................ 18

EXLOS (BIT 5) .......................................................................................................................................... 18

ARAOS (BIT 6) .......................................................................................................................................... 18

1.4 CHANNEL CONTROL REGISTERS ........................................................................................................... 18

LLB[6:0] (ADDRESS 0001) ......................................................................................................................... 18

RLB[6:0] (ADDRESS 0010) ......................................................................................................................... 18

ALBX (ADDRESS 0011) .............................................................................................................................. 18

TAOS[6:0] (ADDRESS 0100) ...................................................................................................................... 18

I

XRT81L27

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

RAOS[6:0] (ADDRESS 0101) ...................................................................................................................... 18

PDTX[6:0] (ADDRESS 0110) ....................................................................................................................... 18

2.0 The transmit section ............................................................................................................................... 19

2.1 THE TRANSMIT LOGIC BLOCK. ............................................................................................................... 19

Figure 7. The Interface for the Transmission of Data From the Transmitting Terminal Equipment

to the Transmit Section of the XRT81L27 ......................................................................... 19

2.1.1 Dual-rail input mode .................................................................................................................. 19

Figure 8. Dual Rail Data from the Terminal .................................................................................... 19

2.1.2 Single-rail input mode ............................................................................................................... 19

Figure 9. Single-Rail Data From the Terminal ............................................................................... 20

2.1.3 TClk input .................................................................................................................................. 20

2.2 THE ENCODER BLOCK ........................................................................................................................... 20

2.2.1 HDB3 Encoding ......................................................................................................................... 20

Figure 10. HDB3 Encoding .............................................................................................................. 20

2.3 THE MUX BLOCK .................................................................................................................................. 20

2.3.1 Timing Control Block ................................................................................................................. 21

2.3.2 The Transmit Clock Duty Cycle Adjust Circuit .......................................................................... 21

2.3.3 Transmit All Ones ...................................................................................................................... 21

2.4 THE PULSE SHAPING CIRCUIT ............................................................................................................... 21

Figure 11. ITU-T G.703 Pulse Template .......................................................................................... 22

2.5 THE LINE DRIVER BLOCK ...................................................................................................................... 22

2.6 INTERFACING THE TRANSMIT SECTIONS OF THE XRT81L27 TO THE LINE ............................................... 22

Figure 12. Illustration of how to interface the Transmit Sections of the XRT81L27 to the Line (for

75 or 120W Applications) ................................................................................................... 23

3.0 The Receive Section ............................................................................................................................... 23

3.1 INTERFACING THE RECEIVE SECTIONS TO THE LINE ............................................................................... 23

Figure 13. Schematic for Interfacing the Receive Sections of the XRT81L27 to the Line for 75W

(Transformer-Coupled) Applications ................................................................................ 24

Figure 14. Schematic for Interfacing the Receive Sections of the XRT81L27 to the Line for 120W

(Transformer-Coupled) Applications ................................................................................ 24

3.2 CAPACITIVE-COUPLING THE RECEIVER TO THE LINE ............................................................................... 25

Figure 15. Capacitive - Coupled Receive Sections of the XRT81L27 to the Line (for Balanced

120W Applications) ............................................................................................................. 25

3.3 THE RECEIVE EQUALIZER BOCK ............................................................................................................ 25

3.4 THE PEAK DETECTOR AND SLICER BLOCK ............................................................................................. 26

3.5 THE LOS DETECTOR BLOCK ................................................................................................................. 26

Figure 16. Package Outline Drawing .............................................................................................. 27

REVISIONS ................................................................................................................................................. 28

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XRT81L27

SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

PIN DESCRIPTIONS

NOTE: I -H indicates an input pin with a 50kΩ pull-up Resistor, I-L indicates an input pin with a 50kΩ pull-down resistor.

PIN #

NAME

RClk_0

LOS_0

TYPE

O

DESCRIPTION

1

2

Receiver 0 Clock Output

Receiver 0 Loss of Signal:

O

This signal is asserted "High" to indicate loss of signal at the receive

input.

3

RST

I-H

Reset (Active-low): (Host Mode)

“Low” Resets the register contents to zero.

Loop-back Enable (Active-low): (Hardware Mode)

“Low” for Loop-back mode enable.

LBEN

RTIP_0

RRING_0

PDTx_0

4

5

6

I

Receiver 0 Bipolar Positive Input:

Receiver 0 Bipolar Negative Input:

I-H

Power-down Transmitter 0:

This pin is operational for both Host or Hardware Mode.

This pin MUST be pulled “Low” to enable TTIP_0 and TRING_0 output

buffers.

Pull this pin "High" to power-down channel 0 transmitter and set TTIP_0

and TRING_0 outputs to high impedance.

7

TTIP_0

TVDD_0

TRING_0

TGND_0

PDTx_2

TTIP_2

O

Vdd

O

Transmitter 0 Tip Output: Positive bipolar data output to the line

Transmitter 0 Positive Supply (3.3V± 5%)

Transmitter 0 Ring Output: Negative bipolar data output to the line.

Transmitter 0 Supply Ground

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Gnd

I-H

O

Power-down Transmitter 2: (see pin 6)

Transmitter 2 Tip Output: Positive bipolar data output to the line.

Transmitter 2 Positive Supply(3.3V± 5%)

Transmitter 2 Ring Output: Negative bipolar data output to the line.

Transmitter 2 Supply Ground.

TVDD_2

TRING_2

TGND_2

AVDD

Vdd

O

Gnd

AVdd

I

Analog Positive Supply(3.3V± 5%)

RTIP_2

Receiver 2 Bipolar Positive Input:

RRING_2

AGND

I

Receiver 2 Bipolar Negative Input:

Gnd

I

Analog Supply Ground.

RTIP_4

Receiver 4 Bipolar Positive Input:

RRING_4

PDTx_4

TTIP_4

I

Receiver 4 Bipolar Negative Input:

I-H

O

Power-down Transmitter 4: (see pin 6)

Transmitter 4 Tip Output: Positive bipolar data output to the line.

Transmitter 4 Positive Supply(3.3V± 5%)

Transmitter 4 Ring Output: Negative bipolar data output to the line.

TVDD_4

TRING_4

Vdd

O

3

XRT81L27

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

PIN DESCRIPTIONS

NOTE: I -H indicates an input pin with a 50kΩ pull-up Resistor, I-L indicates an input pin with a 50kΩ pull-down resistor.

PIN #

NAME

TGND_4

PDTx_6

TTIP_6

TYPE

Gnd

I-H

O

DESCRIPTION

26

Transmitter 4 Supply Ground

27

28

29

30

31

32

Power-down Transmitter 6: (see pin 6)

Transmitter 6 Tip Output: Positive bipolar data output to the line.

Transmitter 6 Positive Supply(3.3V± 5%)

TVDD_6

TRING_6

TGND_6

MODE

Vdd

O

Transmitter 6 Ring Output: Negative bipolar data output to the line.

Transmitter 6 Supply Ground

Gnd

I-L

Mode Control Input:

This pin is used to select Hardware or Host Mode control of the device.

Tie “Low” to select Host Mode

"High" to select Hardware Mode.

33

34

RClk_4

O

Receiver 4 Clock Output:

RNEG_4

Receiver 4 Negative Data Output:

In Dual-Rail mode, this signal is the receive n-rail output data.

Line Code Violation Output:

LCV_4

In Single-Rail mode, this signal outputs a "High" for one clock cycle to

indicate a code violation is detected in the received data.

If AMI coding is selected, every bipolar violation received will cause this

pin to go "High".

35

RPOS_4

RDATA_4

O

Receiver 4 Positive Data Output:

In Dual-Rail mode, this signal is the receive p-rail output data.

Receiver 4 NRZ Data Output:

In Single-Rail mode, this signal is the receive output data

36

37

38

LOS_4

TClk_4

O

I

Receiver 4 Loss of Signal: (see pin 2)

Transmitter 4 Clock Input: E1 rate at 2.048MHz ± 50ppm.

TPOS_4

I

Transmitter 4 Positive Data Input:

In Dual-Rail mode, this signal is the p-rail input data for transmitter 4.

Transmitter 4 NRZ Data Input:

In Single-Rail mode, this signal is used as the NRZ input data

TDATA_4

TNEG_4

39

40

I-L

Transmitter 4 Negative Data Input:

In Dual-Rail mode, this signal is the n-rail data input for transmitter 4.

CODE_4

TAOS_4

In Single-Rail mode (pin 69=1) and with this pin tied "High", input data

at the transmit input is encoded in HDB3 format and the substitution

code in the corresponding receive channel will be removed.

Tie this pin "Low" to enable AMI encoding and decoding.

Transmit All Ones Channel_4:

This pin is set to insert AMI all ones data to the line using MCLK as refer-

ence.

In Host Mode, this pin can be left unconnected.

41

42

VDD

GND

Vdd

Gnd

Digital Positive Supply(3.3V± 5%).

Digital Supply Ground.

4

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XRT81L27

SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

PIN DESCRIPTIONS

NOTE: I -H indicates an input pin with a 50kΩ pull-up Resistor, I-L indicates an input pin with a 50kΩ pull-down resistor.

PIN #

NAME

TYPE

DESCRIPTION

43

TClk_6

I

Transmitter 6 Clock Input: E1 rate at 2.048MHz ± 50ppm.

Transmitter 6 Positive Data/ NRZ Input: (see pin 38)

44

TPOS_6/

TDATA_6

45

TNEG_6/

CODE_6

I-L

Transmitter 6 Negative Data Input: (see pin 39)

Transmit All Ones Channel_6: (see pin 40)

46

47

TAOS_6

SDO

I-L

O

Serial Data Output: (Host Mode)

This pin is the Serial Data Output port for the Microprocessor Serial

Interface access.

LBM

I

Loop-back Mode: (Hardware Mode)

When this pin is tied "High", Analog Local loop-back is selected.

Connect this pin "Low" to select remote loop-back. Digital Local loop-

back is not supported in Hardware Mode.

48

SDI

B1

Serial Data Input Port:

Host Mode, this pin is the serial data input port (see Figure 5).

Hardware Mode, B1, together with B2 (pin 49) and B3 (pin 50) are con-

trol bits used to select which one of the seven channels to be placed in

Loop-back mode. Analog or Remote Loop-back is determined by LBM

(pin 47).

Loop-back Channel Control

B1

0

B2

0

B3

0

Chan. #

0

1

0

1

0

1

0

2

0

1

3

1

0

4

1

0

1

5

1

0

6

1

All

49

50

51

SClk

B2

I

Microprocessor Serial Interface Clock:

Host Mode, this clock signal is used to clock SDI/SDO for the Serial

Interface.

Hardware Mode, B2, together with B1 and B3 are control bits to select

which of the seven channels to be placed in Loop-back mode.(see pin 48

description)

CS

B3

Chip Select Input:

Host Mode, this pin must be asserted "Low" in order to enable commu-

nication with the device via the Serial Interface.

Hardware Mode, B3, together with B1 and B2 are control bits to select

which of the seven channels to be placed in Loop-back mode. (see pin

48 description)

TAOS_5

I-L

Transmit All Ones Channel_5: (see pin 40)

5

XRT81L27

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

PIN DESCRIPTIONS

NOTE: I -H indicates an input pin with a 50kΩ pull-up Resistor, I-L indicates an input pin with a 50kΩ pull-down resistor.

PIN #

NAME

TYPE

DESCRIPTION

52

TNEG_5/

CODE_5

I-L

Transmitter 5 Negative Data Input: (see pin 39)I

53

TPOS_5/

TDATA_5

I

Transmitter 5 Positive/ NRZ Data Input: (see pin 38)

54

55

56

57

58

TClk_5

GND

I

Transmitter 5 Clock Input: E1 rate at 2.048MHz ± 50ppm.

Digital Supply Ground

Gnd

Vdd

O

VDD

Digital Positive Supply(3.3V± 5%)

LOS_5

Receiver 5 Loss of Signal: (see pin 2)

Receiver 5 Positive/NRZ Data Output: (see pin 35)

RPOS_5/

RDATA_5

O

59

RNEG_5/

LCV_5

O

Receiver 5 Negative Data Output: (see pin 34)

60

61

62

RClk_5

LOS_6

O

Receiver 5 Clock Output.

Receiver 6 Loss of Signal: (see pin 2)

Receiver 6 Positive /NRZ Data Output: (see pin 35)

RPOS_6/

RDATA_6

63

RNEG_6/

LCV_6

O

Receiver 6 Negative Data Output: (see pin 34)

64

65

RClk_6

RClkP

O

Receiver 6 Clock Output.

I-L

Receiver Clock Output Polarity: (Hardware Mode)

"Low", All channel RPOS /RDATA and RNEG/LCV output data are

updated on the falling edge of RClk.

"High" to select data update on rising edge of RClk.

66

TClkP

I-L

Transmit Clock Polarity: (Hardware Mode)

"Low", transmit input data is sampled using the falling edge of TClk.

"High" to select rising edge of TClk for data sampling.

67

68

69

RRING_6

RTIP_6

SR/DR

I

Receiver 6 Bipolar Negative Input:

Receiver 6 Bipolar Positive Input:

I-L

Single-rail/Dual-rail Select:

In Hardware Mode and with this pin tied to "High", input transmit data

and receive output data is selected for Single-Rail mode operation.

"Low" to select Dual-Rail mode.

70

MClk

I

Master Clock Input:

This signal is an independent 2.048MHz clock with accuracy better than

±50ppm and duty cycle within 40% to 60%. The function of MCLK is to

provide timing source for the PLL clock recovery circuit, reference clock

to insert All Ones data in the transmit as well as the receive paths.

71

72

TGND_5

TRING_5

Gnd

O

Transmitter 5 Supply Ground

Transmitter 5 Ring Output: Negative bipolar data output to the line

6

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XRT81L27

SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

PIN DESCRIPTIONS

NOTE: I -H indicates an input pin with a 50kΩ pull-up Resistor, I-L indicates an input pin with a 50kΩ pull-down resistor.

PIN #

NAME

TVDD_5

TTIP_5

PDTx_5

RRING_5

RTIP_5

AGND

TYPE

Vdd

O

DESCRIPTION

Transmitter 5 Positive Supply (3.3V± 5%)

Transmitter 5 Tip Output: Positive bipolar data output to the line.

Power-down Transmitter 5: (see pin 6)

Receiver 5 Bipolar Negative Input:

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

I-H

I

Receiver 5 Bipolar Positive Input:

Gnd

I

Analog Supply Ground

RRING_3

RTIP_3

AVDD

Receiver 3 Bipolar Negative Input:

I

Receiver 3 Bipolar Positive Input:

AVdd

Gnd

O

Analog Positive Supply(3.3V± 5%)

TGND_3

TRING_3

TVDD_3

TTIP_3

PDTx_3

TGND_1

TRING_1

TVDD_1

TTIP_1

PDTx_1

RRING_1

RTIP_1

ICT

Transmitter 3 Supply Ground

Transmitter 3 Ring Output: Negative bipolar data output to the line.

Transmitter 3 Positive Supply(3.3V± 5%)

Transmitter 3 Tip Output: Positive bipolar data output to the line.

Power-down Transmitter 3: (see pin 6)

Transmitter 1 Supply Ground.

Vdd

O

I-H

Gnd

O

Transmitter 1 Ring Output: Negative bipolar data output to the line.

Transmitter 1 Positive Supply(3.3V± 5%)

Transmitter 1 Tip Output: Positive bipolar data output to the line.

Power-down Transmitter 1: (see pin 6)

Receiver 1 Bipolar Negative Input:

Vdd

O

I-H

I

Receiver 1 Bipolar Positive Input:

I-H

In-Circuit Testing (Active Low):

When this pin is tied to "Low", all output pins are forced to high imped-

ance state for in-circuit testing.

95

96

97

LOS_1

RClk_1

O

Receiver 1 Loss of Signal: (see pin 2)

Receiver 1 Clock Output:

RNEG_1/

LCV_1

Receiver 1 Negative Data Output: (see pin 34)

98

RPO_1S/

RDATA_1

O

Receiver 1 Positive/NRZ Data Output: (see pin 35)

99

LOS_3

RClk_3

O

Receiver 3 Loss of Signal: (see pin 2)

Receiver 3 Clock Output:

100

101

RNEG_3/

LCV_3

Receiver 3 Negative Data Output: (see pin 34)

7

XRT81L27

áç

SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

PIN DESCRIPTIONS

NOTE: I -H indicates an input pin with a 50kΩ pull-up Resistor, I-L indicates an input pin with a 50kΩ pull-down resistor.

PIN #

NAME

TYPE

DESCRIPTION

102

RPOS_3/

RDATA_3

O

Receiver 3 Positive/NRZ Data Output: (see pin 35)

103

104

105

106

AVDD

AGND

TClk_1

AVdd

Analog Positive Supply(3.3V± 5%)

Gnd

Analog Supply Ground

I

Transmitter 1 Clock Input: E1 rate at 2.048MHz ± 50ppm.

Transmitter 1 Positive/ NRZ Data Input: (see pin 38)

TPOS_1/

TDATA_1

107

TNEG_1/

CODE_1

I-L

Transmitter 1 Negative Data Input: (see pin 39)

108

109

110

TAOS_1

TClk_3

I-L

Transmit All Ones Channel_1: (see pin 40)

I

Transmitter 3 Clock Input: E1 rate at 2.048MHz ± 50ppm.

Transmitter 3 Positive/ NRZ Data Input: (see pin 38)

TPOS_3/

TDATA_3

111

TNEG_3/

CODE_3

I-L

Transmitter 3 Negative Data Input: (see pin 39)

112

113

114

TAOS_3

TAOS_2

I-L

Transmit All Ones Channel_4: (see pin 40)

Transmit All Ones Channel_ 2: (see pin 40)

Transmitter 2 Negative Data Input: (see pin 39)

TNEG_2/

CODE_2

115

TPOS_2/

TDATA_2

I

Transmitter 2 Positive/ NRZ Data Input: (see pin 38)

116

117

118

TClk_2

I

Transmitter 2 Clock Input: E1 rate at 2.048MHz ± 50ppm.

Transmit All Ones Channel_ 0: (see pin 40)

TAOS_0

I-L

TNEG_0/

CODE_0

Transmitter 0 Negative Data Input: (see pin 39)

119

TPOS_0/

TDATA_0

I

Transmitter 0 Positive/ NRZ Data Input: (see pin 38)

120

121

122

123

TClk_0

GND

I

Transmitter 0 Clock Input: E1 rate at 2.048MHz ± 50ppm.

Digital Supply Ground

Gnd

Vdd

O

VDD

Digital Positive Supply(3.3V± 5%)

RPOS_2/

RDATA_2

Receiver 2 Positive/NRZ Data Output: (see pin 35)

124

RNEG_2/

LCV_2

O

Receiver 2 Negative Data Output: (see pin 34)

125

126

RClk_2

LOS_2

O

Receiver 2 Clock Output:

Receiver 2 Loss of Signal: (see pin 2)

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

PIN DESCRIPTIONS

NOTE: I -H indicates an input pin with a 50kΩ pull-up Resistor, I-L indicates an input pin with a 50kΩ pull-down resistor.

PIN #

NAME

TYPE

DESCRIPTION

127

RPOS_0/

RDATA_0

O

Receiver 0 Positive /NRZ Data Output: (see pin 35)

128

RNEG_0/

LCV_0

O

Receiver 0 Negative Data Output: (see pin 34)

TABLE 1: PIN NUMBER BY PIN NAME

CHANNEL RTIP RRING TTIP TRING RCLK RPOS RNEG

LOS

2

TCLK

120

105

116

109

37

TPOS TNEG PDT TAOS TVDD TGND

0

1

2

3

4

5

6

4

5

7

9

1

127

98

128

97

119

106

115

110

38

118

107

114

111

39

6

117

108

113

112

40

8

10

87

15

82

26

71

31

93

17

80

20

77

68

92

18

79

21

76

67

90

12

85

23

74

28

88

14

83

25

72

30

96

95

91

11

86

22

75

27

89

13

84

24

73

29

125

100

33

123

102

35

124

101

34

126

99

36

60

58

59

57

54

53

52

51

64

62

63

61

43

44

45

46

GLOBAL SIGNALS

RST

3

RClkP

MClk

TClkP

ICT

65

70

66

94

MODE

SR/DR

32

69

CONTROLLER INTERFACE

SDO 47

POWER PINS

SDI

48

SClk

49

CS

50

VDD

GND

41

56

55

81

78

122

121

103

104

42

16

19

AVDD

AGND

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

ELECTRICAL CHARACTERISTICS

TABLE 2: ABSOLUTE MAXIMUM RATINGS

-65°C to +150°C

-40°C to +85°C

STORAGE TEMPERATURE

OPERATING TEMPERATURE

ESD RATING

2000V on all pins^a

-0.5 to 6.0V

SUPPLY VOLTAGE

THETA-JA

43 °C/W^b| 32 Degrees,C/W^c

6 °C/W | 5 Degrees, C/W

THETA-JC

a. Human Body Model

b. mounted on 4 (or more) layer board

c. mounted on 3 (or less) layer board

TABLE 3: DC ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

MIN

MAX

UNIT

Input High Voltage

V_IH

2.0

5.0

V

Input Low Voltage

V_IL

V_OH

V_OL

I_L

-0.5

2.4

0.8

3.5

V

Output High Voltage @ IOH = 5mA

Output Low Voltage @ IOL = 5mA

-0.5

----

0.4

V

Input Leakage Current

+ 10

µA

(except input pins with pull-up or

pull-down resistors)

Output Load Capacitance

C_L

----

25

pF

TABLE 4: TRANSMITTER ELECTRICAL CHARACTERISTICS

(VDD=3.3V + 5%, T_A= -40°C to +85°C Unless Otherwise Specified)

PARAMETER

MIN

MAX

UNIT

TEST CONDITIONS

AMI Output Pulse Amplitude:

75Ω Application

120Ω Application

Use transformer with 1:2 ratio

and 9.1Ω resistor in series with

each end of primary.

2.13

2.70

2.60

3.30

V

Output Pulse Width

224

0.95

264

1.05

ns

----

Output Pulse Width Ratio

Output Pulse Amplitude Ratio

ITU-G.703

Output Return Loss:

51KHz --102KHz

102KHz--2048KHz

2048KHz--3072KHz

8

14

10

----

dB

ETSI 300 166, CHPTT

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

TABLE 5: PER CHANNEL POWER CONSUMPTION INCLUDING LINE POWER DISSIPATION, TRANSMISSION AND RECEIVE

PATHS ALL ACTIVE

SYMBO

PARAMETER

MIN

MAX

UNIT

CONDITIONS

L

Power Consumption

PC

-

107

92

mW

75Ω load, operating at 50% Mark Density

120Ω load, operating at 50% Mark Density.

75Ω load, operating at 100% Mark Density.

120Ω load, operating at 100% Mark Density.

180

155

TABLE 6: RECEIVER ELECTRICAL CHARACTERISTICS

(VDD=3.3V + 5%, T_A= -40°C to +85°C Unless Otherwise Specified)

PARAMETER

MIN

MAX

UNIT

TEST CONDITIONS

Receiver loss of signal:

Number of consecutive zeros

before LOS is set

10

255

bit

Number of consecutive Zeros

----

4096

before EXLOS is set

Input signal level at LOS

LOS Delay

12

---

255

2

dB

bit

Cable attenuation @1024KHz

ITU-G.775, ETSI 300 233

Hysteresis

dB

Receiver Sensitivity

11

----

With nominal pulse amplitude of 3.0V for

120Ω and 2.37V for 75Ω application.

Interference Margin

Input Impedance

-18

10

----

dB

With 6dB cable loss.

KΩ

Between RTIP or RRING to ground

Jitter Tolerance:

20 Hz

700Hz

10

5

----

0.5

UIpp

dB

ITU G.823

10KHz ¾100KHz

0.3

Recovered Clock Jitter Transfer

Peaking Amplitude

Corner Frequency = 36KHz

ITU G.736

----

Return Loss:

51KHz -- 102KHz

102KHz -- 2048KHz

2048KHz -- 3072KHz

14

20

16

----

dB

ITU-G.703

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

FIGURE 3. RECEIVE OUTPUT TIMING

RClk

T₁

RClkP=0

T_PD

T_RPW

RPOS/RNEG

RClkP=1

T_RPW

T_PD

RPOS/RNEG

FIGURE 4. TRANSMIT INPUT TIMING

TClk

T ₁

TClkP=0

TPOS/TNEG

T _SU

T _HD

TClkP=1

TPOS/TNEG

T _SU

T _HD

TABLE 7: AC ELECTRICAL CHARACTERISTICS

(VDD=3.3V + 5%, T_A= -40°C to +85°C Unless Otherwise Specified)

PARAMETER

SYMBOL

MIN

MAX

UNIT

TCLK Clock Period

T₁

488.25

488.30

ns

TCLK Duty Cycle

T_DC

T_SU

T_HO

T_R

30

50

-

70

-

%

ns

Transmit Data Setup Time

Transmit Data Hold Time

TCLK Rise Time(10%/90%)

TCLK Fall Time(90%/10%)

Receive Data Rise Time

Receive Data Fall Time

Receive Data Prop. Delay

Receive Data Pulse Width

-

40

-

T_F

-

T_R

-

T_F

-

T_PD

T_RPW

20

450

-

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

If the TAOSX pin of a channel is pulled "High", the

FUNCTIONAL DESCRIPTION

channel will Transmit all ones using the MClk signal

for a timing reference. If "Low", "normal" data will be

transmitted using the TClk.

The XRT81L27 operates in two modes; Hardware or

Host. As described below, Hardware mode allows the

chip to be controlled by digital signals to put it into

various configurations. The Host mode allows a Micro

to control these configurations through a serial inter-

face.

THE HOST MODE

To configure the XRT81L27 to operate in the HOST

Mode, connect the MODE input pin (pin 32) to

Ground or leave unconnected.

THE HARDWARE MODE

When the XRT81L27 is operating in the HOST Mode,

the Microprocessor Serial Interface block is enabled.

Configuration selections are made by writing the ap-

propriate data into the on-chip Command Registers

via the Microprocessor Serial Interface.

The XRT81L27 is placed into the Hardware mode by

connecting the Mode pin (pin 32) to VDD ("High").

When the chip is in the Hardware mode the following

control pins are active: RST/LBEN (pin 3), SDO/LBM

(pin 47), SDI/B1 (pin 48), SClk/B2 (pin 49), CS/B3

(pin 50), SR/DR (pin 69), RClkP (pin 65), TClkP (pin

66). The TAOSx pins (40, 46, 51, 108, 112, 113, 117)

are used to insert "all ones" data into the individual

channels. In addition, the PDTx pins (6, 11, 22, 27,

75, 86, 91) are active in both Hardware and Host

modes to control the individual Transmit line buffers.

1.0 THE MICROPROCESSOR SERIAL INTER-

FACE (MSI)

The on-chip Command Registers of the XRT81L27

E1 Line Interface Unit IC are accessed to configure

the XRT81L27 into a variety of modes. This section

describes how to use the Microprocessor Serial Inter-

face and the Command Registers.

The RST/LBEN pin (3) is used to enable Loopback

mode. When pulled "Low" Loopback is active. SDO/

LBM (pin 47) selects the type of Loopback. With LBM

(pin 47) "High", Analog Loopback is active (Terminal

Equipment Transmit through the channel(s) selected

and back to the Receive out pins). If LBM is "Low",

Remote Loopback is selected (Receive line through

the channel and back out onto the Transmit TIP/RING

buffer onto the Transmit line. Digital Local Loopback

is not supported in Hardware mode.

1.1 MICROPROCESSOR SERIAL INTERFACE DESCRIP-

TION.

The XRT81L27 MSI uses a simple four wire interface

that is compatible with most microcontrollers. Either

hardware blocks in the micro can supply the data or

“bit-banging” can be used. This interface consists of

the following signals:

CS

(pin 50) Chip Select (Active Low)

SCLK (pin 49) Serial Clock

Pins B1, B2, and B3 are used to select the desired

Loopback channel as shown on page 5. This allows

the selection of any one of the seven channels or all

seven. SR/DR (pin 69) is used to select between Sin-

gle Rail or Dual Rail mode for data to and from the

Terminal equipment. With pin 69 tied "High", Single

Rail is selected. Dual Rail will be active if the pin is

pulled "Low". An internal pull-down will accomplish

that if the if the pin is left open.

SDI

(pin 48) Serial Data Input

(pin 47) Serial Data Output

SDO

USING THE MICROPROCESSOR SERIAL INTER-

FACE (MSI)

The user performs Read and Write operations to the

on-chip Command Registers (via the MSI) in two dis-

tinct phases:

With RClkP "Low" or open, all RPOS & RNEG lines

are updated on the falling edge of RClk. When RClkP

is "High", RPOS & RNEG are updated on the rising

edge of RClk. In Host mode the update edge is con-

trolled by the RClkP bit in the Global control latch

(R0, bit 1).

The “Selection Phase”, and

The “Data Phase”

The procedure for performing each of these phases is

presented below.The following descriptions for using

the Microprocessor Serial Interface are best under-

stood by referring to the diagram in Figure 6.

When TClkP is "Low" or open, all TPOS & TNEG

lines are sampled on the falling edge of TCLK. When

TClkP is "High", TPOS & TNEG are sampled on the

rising edge of TClk. In Host mode the sampling edge

is controlled by the TClkP bit in the Global control

register (R0, bit 0).

1.1.1 Selection Phase

In order to use the Microprocessor Serial Interface, a

chip select CS signal must be supplied to the CS in-

put pin. It is important to assert the CS pin (“Low”) at

least 50ns prior to the first rising edge of the clock

signal.

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

Once the CS input pin has been asserted, the type of

operation and the target register address must be

specified. This information is supplied to the MSI by

writing eight serial bits of information into the SDI in-

put. Each of these bits is clocked into the MSI from

the SDI input on the rising edge of SCLK. These eight

bits are identified and described next.

Bits 6 and 7:

The next two bits, (A4 and A5) must be set to “0” as

shown in Figure 6.

Bit 8:

The value of A6 is a “don’t care” but must be clocked.

1.1.2 Data phase of the (MSI) operation

The Microprocessor Serial Interface (MSI) must next

be supplied with 8 additional clocks with the relative

timing of Figure 5. Table 10 provides essential values

for both the selection and data phases of the MSI op-

eration. If the operation specified is a Read, the

XRT81L27 will output data on the SDO pin from the

addressed register. Data is output in ascending order

with the LSB first

Bit 1 - R/W (Read/Write) Bit

This bit is clocked into the SDI input on the first rising

edge of SCLK after CS has been asserted. This bit

indicates whether the current operation is a Read or

Write operation. A “1” in this bit specifies a Read from

the XRT81L27, a “0” in this bit specifies a Write to the

device.

Bits 2 through 5: The four (4) bit Address Values

(labeled A0, A1, A2 and A3)

If a Write operation has been activated, the external

hardware/Micro must supply the first seven (7) bits to

be written into the selected register. The eighth bit is

a “Don’t care” as only seven bits are used in each of

the registers. These bits are input LSB first.

The next four rising edges of the SCLK provide the 4-

bit address value for this operation. The address se-

lects the appropriate Command/Control Register in

the XRT81L27. The address bits must be supplied to

the SDI input pin in ascending order with the LSB

(least significant bit) first.

At the end of the serial shift phase the data is loaded

in parallel into the addressed register. If any register

bit was already set, that bit must be included in the in-

put bit stream. Therefore one must either keep an im-

age of the register status in the micro or do a “read-

modify-write” operation to maintain the state of each

bit that isn’t changing.

FIGURE 5. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE

t29

t21

CS

t27

t28

t22

t25

SCLK

SDI

t26

A1

t24

R/W

t23

A0

CS

SCLK

t31

t30

Hi-Z

t33

t32

D0

D2

D7

SDO

SDI

D1

Hi-Z

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMING (SEE FIGURE 5)

SYMBOL

PARAMETER

MIN.

MAX.

UNITS

t₂₁

CS "Low" to Rising Edge of SCLK Setup Time

50

ns

t₂₂

t₂₃

t₂₄

t₂₅

t₂₆

t₂₇

t₂₈

t₂₉

t₃₀

t₃₁

t₃₂

t₃₃

CS "High" to Rising Edge of SCLK Hold Time

SDI to Rising Edge of SCLK Setup Time

Rising Edge of SCLK to SDI Hold Time

SCLK “Low” Time

20

50

ns

50

240

500

50

SCLK “High” Time

SCLK Period

Rising Edge of SCLK to Rising Edge of CS Hold Time

CS Inactive Time

250

Falling Edge of SCLK to SDO Valid Time

Falling Edge of SCLK to SDO Invalid Time

Falling Edge of SCLK or Rising Edge of CS to high Z

Rise/Fall time of SDO Output

200

100

40

FIGURE 6. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SClk

SDI

R/W A0

A1

A2

A3

0

A6

D0

D1

D2

D3

D4

D6

D7

D5

High Z

D0

D1

D2

D3

D6

D7

SDO

Notes:

- Denotes a “don’t care” value

A4 and A5 are always “0”.

R/W = “1” for “Read” Operations

R/W = “0” for “Write” Operations

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

1.2 Description of the Command Registers

1111) (0x07 through 0x0F) in the address range are

reserved.

A listing of these Command Registers, their binary/

hex Addresses and their Bit-Formats are in Table 9.

All bits are reset to zero by activation of the Reset sig-

nal (RST, pin 3). All other registers (0111 through

TABLE 9: MICROPROCESSOR REGISTER ADDRESS AND CONTROL

BIT 6 BIT 5 BIT 4 BIT 3 BIT 2

GLOBAL COMMAND CONTROL REGISTER (READ/WRITE)

REGISTER

ADDRESS

BIT 7

BIT 1

BIT 0

0000/0x00

reserved

ARAOS

EXLOS

MUTE

SR/DR

CODE

RClkP

TClkP

CHANNEL CONTROL REGISTERS (READ/WRITE)

0001/0x01

0010/0x02

0011/0x03

0100/0x04

0101/0x05

0110/0x06

reserved

LLB6

RLB6

LLB5

RLB5

LLB4

RLB4

LLB3

RLB3

LLB2

RLB2

LLB1

RLB1

LLB0

RLB0

ALB6

ALB5

ALB4

ALB3

ALB2

ALB1

ALB0

TAOS6

RAOS6

PDTx6

TAOS5

RAOS5

PDTx5

TAOS4

RAOS4

PDTx4

TAOS3

RAOS3

PDTx3

TAOS2

RAOS2

PDTx2

TAOS1

RAOS1

PDTx1

TAOS0

RAOS0

PDTx0

TABLE 10: COMMAND CONTROL REGISTER - ADDRESS 0000 - HEX 0X00

(COMMON TO ALL SEVEN CHANNELS)

BIT #

NAME

FUNCTION

REGISTER TYPE

6

ARAOS

Automatic Receive All Ones:

R/W

Writing a "1" to this bit globally enables receive “all one data” insertion at

RPOS/RNEG upon receive LOS condition.

5

4

3

2

1

0

EXLOS

MUTE

SR/DR

CODE

RClkP

TClkP

Extended LOS:

R/W

Writing a "1" to this bit extends the number of zeros at the receive input to

4096 bits before LOS is declared.

Receive Output Muting:

Writing a "1" to this bit mutes the receive data output at RPOS/RNEG to a

“Low” state upon LOS detection EXCEPT when AROAS is set.

Single-rail/Dual-rail:

Writing a "1" to this bit selects single-rail mode operation.

Writing a "0" to select dual-rail mode operation.

Coding and Decoding:

In Single-Rail mode ONLY, selects HDB3 encoding and decoding when set.

Under all other conditions, AMI encoding and decoding is selected.

Receive Clock Polarity:

Writing a "1" to this bit selects, receive output data to be updated on the rising

edge of RCLK and a "0" to update on the falling edge of RClk.

Transmit Clock Polarity:

Writing a "1" to this bit selects, input data to be sampled on the rising edge of

TClk and a "0" to sample on the falling edge of TClk.

16

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

TABLE 11: LOCAL LOOP-BACK REGISTERS - ADDRESS: 0001, HEX 0X01

BIT #.

NAME

FUNCTION

REGISTER TYPE

0-6

LLB0-LLB6 Local Loop-Back:

R/W

Writing a "1" to this bit enables Local Loop-back for the channel(s) selected.

During Local loop-back, transmit input data continues to be sent to the line

unless overridden by TAOS control.

TABLE 12: REMOTE LOOP-BACK REGISTERS - ADDRESS: 0010, HEX 0X02

FUNCTION

BIT #.

NAME

REGISTER TYPE

0-6

RLB0-RLB6

Remote Loop-back:

R/W

Wring a "1" to this bit enables Remote Loop-back for the channel(s)

selected. During Remote Loop-back, receive output data is available at

RPOS/RNEG unless overridden by RAOS request

TABLE 13: ANALOG LOOP-BACK REGISTERS - ADDRESS: 0011, HEX 0X03

FUNCTION

BIT #.

NAME

REGISTER TYPE

0-6

ALB0-ALB6

Analog Loop-back:

R/W

Writing a “1” to this bit enables Analog Local Loop-back for the channel(s)

selected. Analog Loop-back ignores input data on RTIP and RRING and

internally routes data at TTIP and TRING back to the receive input. This

loop-back mode exercises most of the functional blocks of the channel. Ana-

log Loop-back has priority over other Loop-back, TAOS and RAOS requests.

TABLE 14: TAOS REGISTERS - ADDRESS: 0100, HEX 0X04

BIT #.

NAME

FUNCTION

REGISTER TYPE

0-6

TAOS0-TAOS6 Transmit All Ones

Writing a "1" to this bit enables an AMI encoded all ones data to be transmit-

R/W

ted to the line for the channel(s) selected. Transmit input data is ignored

when TAOS bit is set. Remote Loop-Back has priority over TAOS request.

TABLE 15: RAOS REGISTERS - ADDRESS: 0101, HEX 0X05

BIT NO.

NAME

FUNCTION

REGISTER TYPE

0-6

RAOS0-

RAOS6

Receive All Ones:

R/W

Writing a "1" to this bit enables all ones data to be inserted on the receive side

for the channel(s) selected. In Single-Rail mode, all ones data is a continuous

"High" signal at RPOS output and in Dual-Rail mode, a "1010" pattern is sent

to RPOS and RNEG while the receive input signal at RRTIP and RRING is

ignored. Local Loop-Back has priority over RAOS and ARAOS request.

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

TABLE 16: PDTX REGISTERS - ADDRESS: 0110, HEX 0X06

BIT NO.

NAME

FUNCTION

REGISTER TYPE

0-6

PDTx0-

PDTx6

Power-down Transmitter:

R/W

Writing a "1" to this bit shut down the transmitter channel selected and places

the TTIP/TRing driver in high impedance mode. Individual pin control is also

available to switch off the transmitter for fast redundancy application both in

Host and Hardware mode.

1.3 OPERATION OF THE COMMAND CONTROL REGIS-

TER BITS (ADDRESS: 0000, HEX 0X00)

1.4 CHANNEL CONTROL REGISTERS

These registers provide a channel by channel control

of the operation and diagnostic mode of the chip. An

individual or combination of the channels can be con-

trolled. Certain combinations of modes can not be set

as pointed out in the descriptions.

TCLKP (BIT 0)

Set to a “1”, all 7 channels will sample TPOS/TNEG

data on the rising edge of TClk. It will default to a “0”,

sampling on the falling edge.

LLB[6:0] (ADDRESS 0001)

RCLKP (BIT 1)

Setting a bit in this register causes that channel’s

transmit input data to be sent back out of the RPOS/

RNEG receive port. The transmit data will continue to

be sent to the line unless the TAOS control is en-

abled.

Set to a “1”, all channels will output RPOS/RNEG re-

ceive data on the rising edge of RClk. The default val-

ue is “0” where it will output on the falling edge.

CODE (BIT 2)

If set and if the SR/DR bit is set, will select HDB3 en-

coding for Transmit and decoding for Receive on all

channels. If CODE or SR/DR bits are “0”, AMI encod-

ing/decoding is specified.

RLB[6:0] (ADDRESS 0010)

Setting a bit in this register causes that channel’s re-

ceive data to be sent back out of the TTIP/TRING on

the line to the Remote end. The receive data will con-

tinue to be sent to the DTE unless the RAOS control

is enabled.

SR/DR (BIT 3)

If set, single rail mode for the DTE side TPOS in and

RPOS out signals. RNEG is used for Line Code Vio-

lation (LCV) status. Default state is “0”, selecting du-

al-rail operation.

ALBX (ADDRESS 0011)

Setting a bit in this register will cause the analog sig-

nal at the output to be sent back through the receive

section to the DTE equipment. This will effectively ex-

ercise most of the internal functions of that channel.

The Analog loopback has priority over the other loop-

back modes.

MUTE (BIT 4)

If set, will mute the receive outputs of a channel when

the LOS condition is detected and ARAOS is not as-

serted.

TAOS[6:0] (ADDRESS 0100)

EXLOS (BIT 5)

Setting this bit enables transmitting all ones data. A

Remote loopback (RLB) on the channel has priority

over this function.

When set, will extend the number of contiguous re-

ceived zeros to 4096 before the LOS condition is de-

clared.

RAOS[6:0] (ADDRESS 0101)

ARAOS (BIT 6)

Setting this bit inserts all ones into the receive data

stream. Local loopback has priority over RAOS and

the ARAOS signal.

When set this bit enables insertion of “all ones data”

at RPOS/RNEG when LOS is detected on that chan-

nel.

PDTX[6:0] (ADDRESS 0110)

Setting this bit places the Transmit driver into a high

impedance state. Individual pin control is also avail-

able in both the Host and Hardware modes. Care

should be taken in the usage of this feature. While the

default (reset) state of this register is zero, hence en-

abling the outputs of the channel, the “PDT” pin has

18

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XRT81L27

SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

priority. This priority allows fast switching of channels

using “external hardware”. However, if software con-

trol is to be used, the PDTx pin must be tied low as

there is an internal pull-up resistor.

• The Timing Control block

• The TX Pulse Shaper block

• The Line Driver block

2.1 THE TRANSMIT LOGIC BLOCK.

2.0 THE TRANSMIT SECTION

The purpose of the Transmit Logic Block is to accept

either Dual-Rail or Single-Rail TTL/CMOS level data

and timing information from the Terminal Equipment.

The Transmit section of the XRT81L27 consists of the

following blocks:

• THE TRANSMIT LOGIC BLOCK

• The Encoder block

• The MUX block

Figure 7 illustrates the typical interface for the trans-

mission of data between the Terminal Equipment and

the Transmit Section of the XRT81L27.

FIGURE 7. THE INTERFACE FOR THE TRANSMISSION OF DATA FROM THE TRANSMITTING TERMINAL EQUIPMENT TO

THE TRANSMIT SECTION OF THE XRT81L27

TxPOS

Transmit

Digital

TxNEG

TxClk

Transmit

Logic

Terminal

Logic

Block

Equipment

(DTE)

2.1.1 Dual-rail input mode

positive polarity pulse via the TTIP and TRING output

pins. If the XRT81L27 samples a “1” on the TNEG in-

put pin, the Transmit Section of the device generates

a negative polarity pulse via the TTIP and TRING out-

put pins. HDB3 Encoding will already have been done

on this data.

The manner that the LIU handles Dual-Rail data is

described below and illustrated in Figure 8. The

XRT81L27samples the data on the TPOS and TNEG

input pins on the falling edge of TCLK. If the

XRT81L27 samples a “1” on the TPOS input pin, the

Transmit Section of the device ultimately generates a

FIGURE 8. DUAL RAIL DATA FROM THE TERMINAL

Data

1

0

TPOS

TNEG

TCLK

2.1.2 Single-rail input mode

binary data stream) without having to convert it into a

Dual-Rail format. The Transmit Logic Block accepts

Single-Rail data via the TPOS input pin. The TClk sig-

Used if data is to be transmitted from the Terminal

Equipment to the XRT81L27 in Single-Rail format (a

19

XRT81L27

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

nal samples this input pin on the falling edge of the

TCLK clock signal and encodes it into the appropriate

bipolar line signal across the TTIP and TRING output

pins.In this mode the Transmit Logic Block ignores

the TNEG input pin.

Figure 9 illustrates the behavior of the TPOS and

TCLK signals when the Transmit Logic Block has

been configured to accept Single-Rail data from the

Terminal Equipment.

FIGURE 9. SINGLE-RAIL DATA FROM THE TERMINAL

Data

1

0

TPDATA

TCLK

2.1.3 TClk input

consecutive zeros (“0000”). If the HDB3 Encoder

finds an occurrence of four consecutive zeros, it then

substitutes these four “0’s” with either a “000V” or a

“B00V” pattern to insure that an odd number of bipo-

lar pulses exist between any two consecutive viola-

tion pulses.

TCLK is a clock input signal of 2.048 MHz. The global

signal TClkP can be used to invert the polarity of the

sampling clock relative to the TClk input pin for both

SD and DR modes.

2.2 THE ENCODER BLOCK

“B” represents a Bipolar pulse that is compliant with

the Alternating Polarity requirements of the AMI (Al-

ternate Mark Inversion) line code and “V” represents

a bipolar Violation (e.g., a bipolar pulse that violates

the Alternating Polarity requirements of the AMI line

code).

The purpose of the Encoder Block is to aid in the

Clock Recovery process at the Remote Terminal

Equipment by ensuring an upper limit on the number

of consecutive zeros that can exist in the line signal.

2.2.1 HDB3 Encoding

When the Encoder is enabled (by the global CODE

bit set and Single-Rail mode selected), it parses

through and searches the Transmit Data Stream from

the Transmit Logic Block for the occurrence of four (4)

Figure 10 illustrates the HDB3 Encoder at work with

two separate strings of four (or more) consecutive ze-

ros showing a “000V and a “B00V” usage

FIGURE 10. HDB3 ENCODING

TClk

TPOS

SR data

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Encoded

PDATA

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Encoded

NDATA

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

V

Line signal

B

0

V

2.3 THE MUX BLOCK

and send it to the timing control block. Remote loop-

back provides a path for the XRT81L27 to send re-

ceived data back over the Transmit line (TTIP -

TRING) to the “other” end of the Timing Control block

The MUX block accepts data inputs from the Encoder

block and the Remote loopback. Under control of the

channel control bits it will select the desired bit stream

20

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XRT81L27

SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

2.3.1 Timing Control Block

from 30% to 70% and to regenerate these signals

with a 50% duty cycle.

The Timing Control block contains several sub-

blocks. These functions are used to control the timing

on the input data stream such that the output meets

all system timing specifications.

The XRT81L27 Transmit Clock Duty Cycle Adjust cir-

cuit alleviates the need to supply a signal with a 50%

duty cycle to the TCLK input pin.

2.3.2 The Transmit Clock Duty Cycle Adjust Cir-

cuit

2.3.3 Transmit All Ones

In some conditions the system will control the chip

such that it will transmit “all ones” data onto the line. It

is possible that a valid TClk is not available and so the

MClk signal will be used to provide the timing. It

should be noted that the Local feedback will NOT in-

clude the “all ones” bit stream so this data is diverted

before going into the pulse shaper circuit.

The on-chip Pulse-Shaping circuitry in the Transmit

Section of the XRT81L27 has the responsibility for

generating pulses of the shape and width to comply

with the applicable pulse template requirement. The

widths of these output pulses are defined by the width

of the half-period pulses in the TCLK signal.

Allowing the widths of the pulses in the TCLK clock

signal to vary significantly could jeopardize the chip’s

ability to generate Transmit Output pulses of the ap-

propriate width, thereby failing the applicable Pulse

Template Requirement Specification. The chips ability

to generate compliant pulses could depend upon the

duty cycle of the clock signal applied to the TCLK in-

put pin.

2.4 THE PULSE SHAPING CIRCUIT

The purpose of the "Transmit Pulse Shaping" Circuit

is to generate Transmit Output pulses that comply

with the ITU-T G.703 Pulse Template Requirements

for E1 applications, even with TClk duty cycle be-

tween 30 and 70%.

As a consequence, each channel (within the

XRT81L27) will take each mark which is provided to it

via the Transmit Input Interface block, and will gener-

ate a pulse that complies with the pulse template,

presented in Figure 11, (when measured on the sec-

ondary-side of the Transmit Output Transformer).

In order to combat this phenomenon, the Transmit

Clock Duty Cycle Adjust circuit was designed into the

XRT81L27. The Transmit Clock Duty Cycle Adjust

Circuitry is a PLL that was designed to accept clock

pulses via the TCLK input pin at duty cycles ranging

21

XRT81L27

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

FIGURE 11. ITU-T G.703 PULSE TEMPLATE

269 ns

(244 + 25)

V = 100%

194 ns

(244 – 50)

Nominal pulse

50%

244 ns

219 ns

(244 – 25)

0%

488 ns

(244 + 244)

Note

– V corresponds to the nominal peak value.

2.5 THE LINE DRIVER BLOCK

2.6 INTERFACING THE TRANSMIT SECTIONS OF THE

XRT81L27 TO THE LINE

The driver block will take the TP and TN pulses out of

the Pulse Shaping circuit and apply these to the TTIP

and TRING pins. Output drive control is available

from either a dedicated signal or (in Host mode) from

one of register control bits to turn the channel “off” by

placing the drivers in a high impedance state.

In both (75Ω or 120Ω) applications, the user is ad-

vised to interface the Transmitter to the Line, using

the termination as shown in Figure 12. This includes

1:2 transformer with the intrinsic impedance of the

line used as a termination resistance.

The configuration differs only in the type of line con-

nects, The internal circuit adjusts to the load imped-

ance

22

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XRT81L27

SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

FIGURE 12. ILLUSTRATION OF HOW TO INTERFACE THE TRANSMIT SECTIONS OF THE XRT81L27 TO THE LINE (FOR

75 OR 120Ω APPLICATIONS)

TPOS_n

Ω

9.1

TTIP_n

Line

Input

1:2

Ω

Coax

75

TNEG_n

Ω

120

TRING_n

Twisted

Pair

Ω

9.1

TClk_n

XRT81L27

3.0 THE RECEIVE SECTION

couple the Receive Section to the line. Additionally,

as mentioned earlier, the specification documents for

E1 specify 75Ω termination loads, when transmitting

over coaxial cable, and 120Ω loads, when transmit-

ting over twisted-pair. Figure 13, Figure 14 and

Figure 15 present the various methods that can be

employ to interface the Receivers (of the XRT81L27)

to the line. The receive circuits of Figure 13,

The Receive Sections of the XRT81L27 consists of

the following blocks:

• The Receive Equalizer block

• The Peak Detector and Slicer block

• The LOS Detector block

• The Receive Output Interface block

Figure 14 and Figure 15 differ in the impedance at the

inputs and the line connections.

3.1 INTERFACING THE RECEIVE SECTIONS TO THE

LINE

The design of each channel (within the XRT81L27)

permits the user to transformer-couple or capacitive-

23

XRT81L27

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

FIGURE 13. SCHEMATIC FOR INTERFACING THE RECEIVE SECTIONS OF THE XRT81L27 TO THE LINE FOR 75Ω

(TRANSFORMER-COUPLED) APPLICATIONS

RPOS_n

RNEG_n

RClk_n

RTIP_n

Line

Input

1: 2

LOS_n

RRING_n

XRT81L27

FIGURE 14. SCHEMATIC FOR INTERFACING THE RECEIVE SECTIONS OF THE XRT81L27 TO THE LINE FOR 120Ω

(TRANSFORMER-COUPLED) APPLICATIONS

RPOS_n

RTIP_n

1:2

RNEG_n

Line

Input

RClk_n

RRing_n

LOS_n

XRT81L27

The Transformer used should be 1:2 step up for

Transmit direction and 2:1 step down for the Receive

direction. The following transformers are recommend-

ed: Pulse PE-65681, Pulse T1090, and HALO TG08-

1505N1.

24

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XRT81L27

SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

3.2 CAPACITIVE-COUPLING THE RECEIVER TO THE

LINE

Figure 15 presents a recommended method to use

when capacitive-coupling the Receive Section to the

line.

FIGURE 15. CAPACITIVE - COUPLED RECEIVE SECTIONS OF THE XRT81L27 TO THE LINE (FOR BALANCED 120Ω

APPLICATIONS)

RPOS1

RNEG1

RClk1

C1

30.1 Ω

RTIP1

0.1uF

C2

30.1 Ω

RRing1

RLOS1

0.1uF

3.3 THE RECEIVE EQUALIZER BOCK

amount of attenuation than the lower frequency com-

ponents. If this line signal travels over reasonably

long cable lengths, then the original square shape of

the pulses will be distorted and with inter-symbol in-

terference increases.

After a given Channel (within the XRT81L27) has re-

ceived the incoming line signal, via the RTIP_n

(where _n is the channel number) and RRING_n in-

put pins, the first block that this signal will pass

through is the Receive Equalizer block.

The purpose of this block is to equalize the incoming

distorted signal, due to cable loss. In essence, the

Receive Equalizer block accomplishes this by sub-

jecting the received line signal to frequency-depen-

dent amplification (which attempts to counter the fre-

quency-dependent loss that the line signal has expe-

rienced). By doing this, the Receive Equalizer is at-

tempting to restore the shape of the line signal so that

the received data can be recovered reliably.

As the line signal is transmitted from a given Trans-

mitting terminal, the pulse shapes (at that location)

are basically square. Hence, these pulses consist of a

combination of low and high frequency Fourier com-

ponents. As this line signal travels from the transmit-

ting terminal (via the coaxial cable or twisted pair) to

the receiving terminal, it will be subjected to frequen-

cy-dependent loss. The higher frequency compo-

nents of the signal will be subjected to a greater

25

XRT81L27

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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

3.4 THE PEAK DETECTOR AND SLICER BLOCK

LOS Condition if the signal amplitude rises back up to

–15dB typically, or above. The XRT81L27 was de-

signed to meet the ITU-T G.775 specification timing

requirements for declaring and clearing the LOS indi-

cator. In particular, the XRT81L27 will declare an LOS

between 10 and 255 UI (or E1 bit periods) after the

actual time the LOS condition occurred. Further, the

XRT81L27 will clear the LOS indicator within 10 to

255 UI after restoration of the incoming line signal.

After the incoming line signal has passed through the

Receive Equalizer block, it will next be routed to the

Slicer block. The purpose of the Slicer block is to

quantify a given bit-period (or symbol) within the in-

coming line signal as either a “1” or a “0”.

3.5 THE LOS DETECTOR BLOCK

The LOS Detector block, within each channel (of the

XRT81L27) was specifically designed to comply with

the LOS Declaration/Clearance requirements per

ITU-T G.775. As a consequence, the channel will de-

clare an LOS Condition, (by driving the LOS output

pin “High”) if the received line signal amplitude drops

to –20dB or below. Further, the channel will clear the

When operating in the Host mode, the LOS time can

be extended to 4096 zeros by the activation of the

EXLOS bit in the Command Control Register. This

will provide for those cases where the G.775 specifi-

cation value is not long enough,

26

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XRT81L27

SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

REV. 1.1.0

FIGURE 16. PACKAGE OUTLINE DRAWING

D

D1

102

65

103

64

E1

E

128

39

1

38

A₂

B

e

A

α

C

A₁

L

Note: The control dimension is the millimeter column

INCHES

MAX

MILLIMETERS

SYMBOL

MIN

MAX

1.60

0.15

A

0.055

0.002

0.063

0.006

1.40

0.05

A₁

0.053

0.057

1.35

1.45

A₂

B

0.007

0.004

0.858

0.783

0.011

0.008

0.874

0.791

0.17

0.09

0.27

0.20

C

D

D₁

E

21.80

19.90

22.20

20.10

0.622

0.547

0.638

0.555

15.80

13.90

16.20

14.10

E₁

e

0.020 BSC

0.50 BSC

L

0.018

0.030

0.45

0.75

α

0°

7°

0°

7°

27

áç

XRT81L27^{SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY}

REV. 1.1.0

REVISIONS

Rev. 1.0.1 changed package from 14x14mm 128 pins to 14x20mm 128 pins.

Rev. 1.0.2 Added info on serial processor interface. Corrected pin out for pins 33, 34, 35, 36, 37, 38, 97, 98,

101 and 102.

Rev. 1.0.3 Corrected typos in pin list (pin 29, 51, 64 and 118) and Pin out diagram (pins 47, 48 and 69).

Rev 1.0.4 “Jack Irwin” 10/19/01

Rev 1.0.5 John edits.

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order

to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of

any circuits described herein, conveys no license under any patent or other right, and makes no represen-

tation that the circuits are free of patent infringement. Charts and schedules contained here in are only for

illustration purposes and may vary depending upon a user’s specific application. While the information in

this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where

the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys-

tem or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-

tions unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury

or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo-

ration is adequately protected under the circumstances.

Datasheet November 2001.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

28


型号：	XRT81L27
厂家：	EXAR CORPORATION
描述：	SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY SEVEN路E1线路接口时钟恢复单元时钟
文件：	总30页 (文件大小：377K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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