XRT84L38IB_技术文档

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XRT84L38

OCTAL T1/E1/J1 FRAMER

FEBRUARY 2004

REV.1.0.0

and Overhead Data Input port, which permits Data

Link Terminal Equipment direct access to the out-

bound T1/E1/J1 frames Likewise, a Receive Over-

head output data port permits Data Link Terminal

Equipment direct access to the Data Link bits of the

inbound T1/E1/J1 frames.

GENERAL DESCRIPTION

The XRT84L38 is an eight-channel 1.544 Mbit/s or

2.048 Mbit/s DS1/E1/J1 framing controller. The

XRT84L38 contains an integrated DS1/E1/J1 framer

which provides DS1/E1/J1 framing and error accumu-

lation in accordance with ANSI/ITU_T specifications.

Each framer has its own framing synchronizer and

The XRT84L38 fully meets all of the latest T1/E1/J1

transmit-receive slip buffers, and can be independent- specifications: ANSI T1/E1.107-1988, ANSI T1/

ly enabled or disabled as required and can be config-

ured to frame to the common DS1/E1/J1 signal for-

mats

E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/

E1.408-1990, AT&T TR 62411 (12-90) TR54016, and

ITU G-703, G.704, G706 and G.733, AT&T Pub.

43801, and ETS 300 011, 300 233, JT G.703, JT

G.704, JT G706, I.431. Extensive test and diagnostic

functions include Loop-backs, Boundary scan, Pseu-

do Random bit sequence (PRBS) test pattern gener-

ation, Performance Monitor, Bit Error Rate (BER)

meter, forced error insertion, and LAPD unchannel-

ized data payload processing according to ITU-T

standard Q.921.

Each Framer block contains its own Transmit and Re-

ceive T1/E1/J1 Framing function including 3 HDLC

controllers to support V5.2. Each Transmit HDLC

controller encapsulates contents of the Transmit

HDLC buffers into LAPD Message frames. Each Re-

ceive HDLC controller extracts payload content of Re-

ceive LAPD Message frames from the incoming T1/

E1/J1 data stream and writes it into the Receive

HDLC buffer. Each framer also contains a Transmit

Applications and Features (next page)

FIGURE 1. XRT84L38 8-CHANNEL DS1 (T1/E1/J1) FRAMER

External Data

Link Controller

8 DS1/E1

Channels

Local PCM

Tx Overhead In

Rx Overhead Out

XRT84L38

Highway

1.544/2.048 MHz

XRT83L38

1 of 8-channels

TxPOS

TxNEG

TxLineCLK 8

8

2-Frame

Slip Buffer

Elastic Store

Tx Encoder

LIU

Interface

TPOS

TNEG

TCLK1

8

Twisted

Pair

Tx Serial

Data In

Tx1

Rx1

Tx Framer

Rx Framer

Tx Serial

Clock

Twisted

Pair

LLB

LB

RxPOS

RxNEG

RxLineCLK 8

8

2-Frame

Slip Buffer

Elastic Store

Rx Encoder

LIU

Interface

RPOS

RNEG

RCLK1

8

Rx Serial

Data Out

Rx Serial

Clock

µP

Interface

HDLC (LAPD)

Controller &

96-byte Buffer

LIU &

Loopback

Control

PRBS

Generator &

Analyser

Performance

Monitor

Tx8

8kHz sync

OSC

Rx8

DMA

Interface

Microprocessor

Interface

Signaling &

Alarms

JTAG

8-CH T1/E1/LIU

Host Mode

Back Plane

1.544-16.384 Mbit/s

WR

ALE_AS

RD

4

3

Channel

Select

Interrupt

D[7:0]

A[6:0]

RDY_DTACK

Intel/Motorola µP

Configuration, Control &

Status Monitor

System (Terminal) Side

Line Side

Memory

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

XRT84L38

OCTAL T1/E1/J1 FRAMER

REV. 1.0.0

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APPLICATIONS

• Extracts and inserts robbed bit signaling (RBS)

• High-Density T1/E1/J1 interfaces for Multiplexers,

• 3 independent HDLC Controllers for Receive and

Switches, LAN Routers and Digital Modems

Transmit on a per channel basis

• SONET/SDH terminal or Add/Drop multiplexers

• Each HDLC controller contains two 96-BYTE buff-

(ADMs)

ers

• T1/E1/J1 add/drop multiplexers (MUX)

• Timeslot assignable HDLC

• V5.1 and V5.2 Interface

• Channel Service Units (CSUs): T1/E1/J1 and Frac-

tional T1/E1/J1

•

µ

8-bit Intel/Motorola P and MIPS Power PC inter-

• Digital Access Cross-connect System (DACs)

• Digital Cross-connect Systems (DCS)

faces for configuration, control and status monitor-

ing

• Parallel search algorithm for fast frame synchroni-

zation

• Frame Relay Switches and Access Devices

(FRADS)

• Wide choice of T1 framing structures: D4, ESF,

SLC®96, TIDM and N-Frame (non-framing)

• ISDN Primary Rate Interfaces (PRA)

• PBXs and PCM channel bank

• Direct access to D and E channels for fast transmis-

sion of data link information

• T3 channelized access concentrators and M13

MUX

• PRBS and QRSS generation and detection

• Programmable Interrupt output pin

• Wireless base stations

• ATM equipment with integrated DS1 interfaces

• Multichannel DS1 Test Equipment

• T1/E1/J1 Performance Monitoring

• Voice over packet gateways

• Routers

• Supports programmed I/O, Burst and DMA modes

of Read-Write access

• Each framer block encodes and decodes the T1/

E1/J1 Frame serial data into and from the Single-

rail or Dual-rail (B8ZS) format

• Dual or single rail line side digital PCM inputs

FEATURES

• Detects and forces Red (SAI), Yellow (RAI) and

• Eight independent, full duplex DS1 Tx and Rx

Blue (AIS) Alarms

Framers

• Detects OOF, LOF, LOS errors and COFA condi-

tions

• Two 512-bit (two-frame) elastic store, PCM frame

slip buffers (FIFO) on TX and Rx provide up to

8.192 MHz asynchronous back plane connections

with jitter and wander attenuation

• Loopbacks: Local (LLB) and Line remote (LB)

• Facilitates Inverse Multiplexing for ATM

• Supports input PCM and signaling data at 1.544,

2.048, 4.096 and 8.192 Mbits. Also supports 4-

channel multiplexed 12.352/16.384 (HMVIP/H.100)

Mbit/s on the back plane bus

• Performance monitor with one second polling

• Boundary scan (IEEE 1149.1) JTAG test port

• Accepts external 8kHz Sync reference

• 3.3V CMOS operation with 5V tolerant inputs

• Programmable output clocks for Fractional T1/E1/

J1

•

°

388-pin BGA package with –40 C to +85 C opera-

tion

• Supports Channel Associated Signaling (CAS)

• Supports Common Channel Signalling (CCS)

• Direct Interface to Exar’s XRT83L38 (Octal) LIU

• Supports ISDN Primary Rate Interface (ISDN PRI)

signaling

ORDERING INFORMATION

PART NUMBER

PACKAGE

OPERATING TEMPERATURE RANGE

XRT84L38IB

388 Pin Plastic Ball Grid Array

-40°C to +85°C

2

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XRT84L38

OCTAL T1/E1/J1 FRAMER

REV.1.0.0

FIGURE 2. PIN OUT OF THE XRT84L38 TOP VIEW (SEE PIN LIST FOR NAMES AND FUNCTION)

(See pin list for pin names and function)

Top View

A

26

A1

B1

AF

AE

AD

AC

AB

AA

Y

C1

D

23

D

26

D4

E1

F1

G1

H1

J1

D4

W

V

K1

L1

U

L

23

L

24

L

25

L

26

L2

L3

L4

V3

V1

G

V3

V1

G

V3

G

V3

G

V3

V2

G

V3

V2

G

T

M1

N1

P1

R1

T1

U1

V1

W1

Y1

R

P

N

M

L

T

23

T

24

T

25

T

26

T2

T3

T4

K

XRT84L38

J

H

G

F

AA

1

AB

1

E

AC

1

AC

4

AC

23

AC

26

D

AD

1

C

AE

1

B

AF

1

AF

26

A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

3

XRT84L38

OCTAL T1/E1/J1 FRAMER

REV. 1.0.0

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TABLE OF CONTENTS

GENERAL DESCRIPTION ................................................................................................. 1

Figure 1. XRT84L38 8-channel DS1 (T1/E1/J1) Framer ................................................................... 1

APPLICATIONS .............................................................................................................................................. 2

FEATURES .................................................................................................................................................... 2

ORDERING INFORMATION ............................................................................................................... 2

Figure 2. Pin Out of the XRT84L38 Top View (see pin list for names and function) .................... 3

TABLE OF CONTENTS ....................................................................................................... I

TABLE 1: LIST BY PIN NUMBER ............................................................................................................ 16

PIN DESCRIPTIONS ........................................................................................................ 21

TRANSMIT SERIAL DATA INPUT .................................................................................................................... 21

OVERHEAD INTERFACE ............................................................................................................................... 30

RECEIVE SERIAL DATA OUTPUT .................................................................................................................. 32

RECEIVE DECODER LIU INTERFACE ............................................................................................................. 39

TRANSMIT ENCODER LIU INTERFACE ........................................................................................................... 39

TIMING ....................................................................................................................................................... 40

LIU CONTROL ............................................................................................................................................. 41

JTAG ........................................................................................................................................................ 42

MICROPROCESSOR INTERFACE .................................................................................................................... 43

GROUND PINS ............................................................................................................................................ 46

POWER SUPPLY PINS ................................................................................................................................. 46

NO CONNECT PINS ..................................................................................................................................... 47

ELECTRICAL CHARACTERISTICS ................................................................................................................... 48

ABSOLUTE MAXIMUMS ................................................................................................................................ 48

DC ELECTRICAL CHARACTERISTICS ............................................................................................................ 48

TABLE 2: XRT84L38 POWER CONSUMPTION ...................................................................................... 48

1.0 Microprocessor Interface Block ............................................................................................................ 49

TABLE 3: µC/µP SELECTION TABLE ..................................................................................................... 49

1.1 CHANNEL SELECTION WITHIN THE FRAMER ............................................................................................ 50

1.2 THE MICROPROCESSOR INTERFACE BLOCK SIGNAL ............................................................................... 50

TABLE 4: CHANNEL SELECTION ........................................................................................................... 50

Figure 3. Simplified Block Diagram of the Microprocessor Interface Block .............................. 50

TABLE 5: XRT84L38 MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH THE

INTEL AND MOTOROLA MODES ................................................................................................ 51

1.3 INTERFACING THE XRT84L38 TO THE LOCAL µC/µP VIA THE MICROPROCESSOR INTERFACE BLOCK ....... 52

1.3.1 Interfacing the Framer to the Microprocessor over an 8 bit wide bi-directional Data Bus ......... 52

TABLE 6: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS ........................................................... 52

TABLE 7: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS .................................................. 52

1.3.2 Data Access Modes .................................................................................................................. 53

Figure 4. Intel µP Interface signals during Programmed I/O Read Operation ............................ 54

Figure 5. Intel µP Interface Signals during Programmed I/O Write Operation ........................... 55

Figure 6. Motorola µP Interface signals during a Programmed I/O Read Operation ................. 56

Figure 7. Motorola µP Interface signal during Programmed I/O Write Operation ...................... 57

Figure 8. Intel µP Interface Signals, during the Initial Read Operation of a Burst Cycle .......... 58

Figure 9. Intel µP Interface Signals, during subsequent Read Operations of a Burst I/O Cycle ...

60

Figure 10. Intel µP Interface signals, during the Initial Write Operation of a Burst Cycle ........ 62

Figure 11. µP Interface Signals, during subsequent Write Operations of a Burst I/O Cycle .... 63

Figure 12. Motorola µP Interface Signals during the Initial Read Operation of a Burst Cycle . 64

Figure 13. Motorola µP Interface Signals, during subsequent Read Operations of a Burst I/O Cy-

cle ......................................................................................................................................... 65

Figure 14. Motorola µP Interface signals, during the Initial Write Operation of a Burst Cycle . 67

1.4 DMA READ/WRITE OPERATIONS ........................................................................................................... 68

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XRT84L38

OCTAL T1/E1/J1 FRAMER

REV.1.0.0

Figure 15. Motorola µP Interface Signals during subsequent Write Operations of a Burst I/O Cy-

cle ......................................................................................................................................... 68

DMA-0 Write DMA Interface ............................................................................................................................. 69

1.5 MEMORY AND REGISTER MAP .............................................................................................................. 69

1.5.1 Memory Mapped I/O Indirect Addressing ................................................................................. 69

Figure 16. DMA Mode for the XRT84L38 and a Microprocessor ................................................. 69

TABLE 8: ADDRESS MAP ..................................................................................................................... 70

1.6 DESCRIPTION OF THE CONTROL REGISTERS ......................................................................................... 71

RECEIVE SUBSTITUTION SIGNALING REGISTER (RSSR) (INDIRECT ADDRESS = 0XN02H, 0XC0H - 0XD7H) 150

TABLE 9: PMON T1/E1 RECEIVE LINE CODE (BIPOLAR) VIOLATION COUNTER ................................... 175

TABLE 10: PMON T1/E1 RECEIVE LINE CODE (BIPOLAR) VIOLATION COUNTER ................................. 175

TABLE 11: PMON T1/E1 RECEIVE FRAMING ALIGNMENT BIT ERROR COUNTER ................................. 175

TABLE 12: PMON T1/E1 RECEIVE FRAMING ALIGNMENT BIT ERROR COUNTER ................................. 175

TABLE 13: PMON T1/E1 RECEIVE SEVERELY ERRORED FRAME COUNTER ........................................ 176

TABLE 14: PMON T1/E1 RECEIVE CRC-4 BLOCK ERROR COUNTER - MSB ..................................... 176

TABLE 15: PMON T1/E1 RECEIVE CRC-4 BLOCK ERROR COUNTER - LSB ...................................... 176

TABLE 16: PMON T1/E1 RECEIVE FAR-END BLOCK ERROR COUNTER - MSB .................................. 176

TABLE 17: PMON T1/E1 RECEIVE FAR END BLOCK ERROR COUNTER .............................................. 177

TABLE 18: PMON T1/E1 RECEIVE SLIP COUNTER ............................................................................ 177

TABLE 19: PMON T1/E1 RECEIVE LOSS OF FRAME COUNTER .......................................................... 177

TABLE 20: PMON T1/E1 RECEIVE CHANGE OF FRAME ALIGNMENT COUNTER ................................... 178

TABLE 21: PMON LAPD T1/E1 FRAME CHECK SEQUENCE ERROR COUNTER ................................... 178

TABLE 22: T1/E1 PRBS BIT ERROR COUNTER MSB ........................................................................ 178

TABLE 23: T1/E1 PRBS BIT ERROR COUNTER LSB ......................................................................... 179

TABLE 24: T1/E1 TRANSMIT SLIP COUNTER ...................................................................................... 179

1.7 THE INTERRUPT STRUCTURE WITHIN THE FRAMER .............................................................................. 180

TABLE 25: LIST OF THE POSSIBLE CONDITIONS THAT CAN GENERATE INTERRUPTS, IN EACH FRAMER . 180

TABLE 26: ADDRESS OF THE BLOCK INTERRUPT STATUS REGISTERS ................................................. 181

TABLE 27: BLOCK INTERRUPT STATUS REGISTER .............................................................................. 182

TABLE 28: BLOCK INTERRUPT ENABLE REGISTER ............................................................................. 183

1.7.1 Configuring the Interrupt System, at the Framer Level ........................................................... 184

TABLE 29: INTERRUPT CONTROL REGISTER ....................................................................................... 184

2.0 The E1 Framing Structure .................................................................................................................... 186

2.1 THE SINGLE E1 FRAME ...................................................................................................................... 186

Timeslot 0 ....................................................................................................................................................... 186

Timeslot 0 octets within FAS frames .............................................................................................................. 186

Figure 17. Single E1 Frame Diagram ........................................................................................... 186

TABLE 30: BIT FORMAT OF TIMESLOT 0 OCTET WITHIN A FAS E1 FRAME .......................................... 186

Bit 0—Si (International Bit) ............................................................................................................................. 187

Bit 1—Fixed at “1” .......................................................................................................................................... 187

Bit 2—A (FAS Frame Yellow Alarm Bit) ......................................................................................................... 187

Bit 3 through 7—Sa4–Sa8 (National Bits) ...................................................................................................... 187

2.2 THE E1 MULTI-FRAME STRUCTURES ................................................................................................... 187

2.2.1 The CRC Multi-frame Structure .............................................................................................. 187

TABLE 31: BIT FORMAT OF TIMESLOT 0 OCTET WITHIN A NON-FAS E1 FRAME .................................. 187

2.2.2 CAS Multi-Frames and Channel Associated Signaling .......................................................... 188

TABLE 32: BIT FORMAT OF ALL TIMESLOT 0 OCTETS WITHIN A CRC MULTI-FRAME ............................ 188

Figure 18. Frame/Byte Format of the CAS Multi-Frame Structure ............................................ 189

Figure 19. E1 Frame Format ......................................................................................................... 190

3.0 The DS1 Framing Structure ................................................................................................................. 191

3.1 T1 SUPER FRAME FORMAT (SF) ........................................................................................................ 191

Figure 20. T1 Frame Format ......................................................................................................... 191

Figure 21. T1 Superframe PCM Format ....................................................................................... 192

TABLE 33: SUPERFRAME FORMAT ..................................................................................................... 192

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XRT84L38

OCTAL T1/E1/J1 FRAMER

REV. 1.0.0

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3.2 T1 EXTENDED SUPERFRAME FORMAT ................................................................................................. 193

Figure 22. T1 Extended Superframe Format ................................................................................ 193

TABLE 34: EXTENDED SUPERFRAME FORMAT .................................................................................... 194

3.3 SLC 96 FORMAT (SLC) ...................................................................................................................... 195

TABLE 35: SLC®96 FS BIT CONTENTS ............................................................................................. 195

4.0 The DS1 Transmit Section ................................................................................................................... 196

4.1 THE DS1 TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK ............................................................ 196

4.1.1 Description of the Transmit Payload Data Input Interface Block ............................................. 196

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ........................ 196

4.1.2 Brief Discussion of the Transmit Payload Data Input Interface Block Operating at 1.544Mbit/s

mode ................................................................................................................................................ 197

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................ 197

TABLE 36: SIGNALS FOR DIFFERENT TRANSMIT TIMING SOURCES ........................................................ 198

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ....................... 198

TABLE 37: THE TXTSB[3:0] BITS WHEN THE TRANSMIT FRACTIONAL T1 INPUT BIT IS SET TO DIFFERENT VAL-

UES ...................................................................................................................................... 199

Figure 23. Interfacing XRT84L38 to local Terminal Equipment with TxSerClk_n as Transmit Tim-

ing Source .......................................................................................................................... 200

Figure 24. Waveforms of the signals that connect the Transmit Payload Data Input Interface

block to the local Terminal Equipment with the Transmit Serial clock being the Timing

Source of the Transmit Section ....................................................................................... 201

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................ 202

Figure 25. Interfacing XRT84L38 to the local Terminal Equipment with the OSCCLK Driven Divid-

ed Clock as Transmit Timing Source .............................................................................. 203

Figure 26. Waveforms of the signals connecting the Transmit Payload Data Input Interface block

to the local Terminal Equipment with the OSCCLK Driven Divided clock as the timing

source of the Transmit Section ....................................................................................... 204

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................. 205

Figure 27. Interfacing XRT84L38 to local Terminal Equipment with Recovered Receive Line

Clock as Transmit Timing Source ................................................................................... 206

4.1.3 Brief Discussion of the Transmit High-Speed Back-Plane Interface ....................................... 207

Figure 28. Waveforms of the signals connecting the Transmit Payload Data Input Interface block

to the local Terminal Equipment with the Recovered Receive Line Clock being the timing

source of the Transmit Section ....................................................................................... 207

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ....................... 207

TABLE 38: TRANSMIT MULTIPLEX ENABLE BIT AND TRANSMIT INTERFACE MODE SELECT [1:0] BITS WITH THE

RESULTING TRANSMIT BACK-PLANE INTERFACE DATA RATES ................................................. 208

TRANSMIT MULTIPLEX ENABLE BIT = 0 ...................................................................................................... 208

TRANSMIT MULTIPLEX ENABLE BIT = 1 ...................................................................................................... 209

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ........................ 209

TABLE 39: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ..................................................... 210

Figure 29. Interfacing XRT84L38 to the local Terminal Equipment using MVIP 2.048Mbit/s Data

Bus ..................................................................................................................................... 211

Figure 30. Timing Diagram of the Input Signals to the Framer when running at MVIP 2.048Mbit/s

Mode ................................................................................................................................... 211

TABLE 40: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ..................................................... 212

Figure 31. Interfacing XRT84L38 to the local Terminal Equipment using 4.096Mbit/s Data Bus ..

213

Figure 32. Timing Diagram of the Input Signals to the Framer when running at 4.096Mbit/s Mode

213

TABLE 41: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ..................................................... 214

Figure 33. Interfacing XRT84L38 to the Local Terminal Equipment using 8.192Mbit/s Data Bus .

215

Figure 34. Timing Diagram of the Input Signals to the Framer when running at 8.192Mbit/s Mode

III

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XRT84L38

OCTAL T1/E1/J1 FRAMER

REV.1.0.0

215

FIRST OCTET OF 12.352MBIT/S DATA STREAM ......................................................................................... 216

SECOND OCTET OF 12.352MBIT/S DATA STREAM ..................................................................................... 216

THIRD OCTET OF 12.352MBIT/S DATA STREAM ......................................................................................... 216

SIXTH OCTET OF 12.352MBIT/S DATA STREAM ......................................................................................... 217

SEVENTH OCTET OF 12.352MBIT/S DATA STREAM .................................................................................... 217

EIGHTH OCTET OF 12.352MBIT/S DATA STREAM ...................................................................................... 217

NINETH OCTET OF 12.352MBIT/S DATA STREAM ....................................................................................... 217

Figure 35. Interfacing XRT84L38 to the Local Terminal Equipment using Bit-Multiplexed

12.352Mbit/s Data Bus ...................................................................................................... 218

Figure 36. Timing Diagram of the Input Signals to the Framer when running at 12.352Mbit/s Mode

218

FIRST OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 219

NINETH OCTET OF 16.384MBIT/S DATA STREAM ....................................................................................... 219

TENTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 219

THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM ............................................................................... 220

FOURTEENTH OCTET OF 16.384MBIT/S DATA STREAM .............................................................................. 220

FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 220

SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 220

Figure 37. Interfacing XRT84L38 to the Local Terminal Equipment using 16.384Mbit/s Data Bus

221

Figure 38. Timing Diagram of the Input Signals to the Framer when running at Bit-Multiplexed

16.384Mbit/s Mode ............................................................................................................ 221

FIRST OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 222

NINTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 222

ELEVENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................. 223

THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM ............................................................................... 223

FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 223

TENTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 223

TWELFTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 223

FOURTEENTH OCTET OF 16.384MBIT/S DATA STREAM .............................................................................. 223

SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 224

Figure 39. Interfacing XRT84L38 to the Local Terminal Equipment using HMVIP 16.384Mbit/s

Data Bus ............................................................................................................................ 225

Figure 40. Timing Diagram of the Input Signals to the Framer when running at HMVIP 16.384Mbit/

s Mode ............................................................................................................................... 225

FIRST OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 226

NINTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 226

ELEVENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................. 227

THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM ............................................................................... 227

FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 227

TENTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 227

TWELFTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 227

FOURTEENTH OCTET OF 16.384MBIT/S DATA STREAM .............................................................................. 227

SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 228

Figure 41. Interfacing XRT84L38 to the Local Terminal Equipment using H.100 16.384Mbit/s Data

Bus ..................................................................................................................................... 229

Figure 42. Timing Diagram of the Input Signals to the Framer when running at H.100 16.384Mbit/

s Mode ............................................................................................................................... 229

5.0 The DS1 Receive Section ..................................................................................................................... 230

5.1 THE DS1 RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK .......................................................... 230

5.1.1 Description of the Receive Payload Data Output Interface Block .......................................... 230

5.1.2 The Receive Payload Data Output Interface Block Operating at 1.544Mbit/s mode .............. 230

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H) ........................ 230

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XRT84L38

OCTAL T1/E1/J1 FRAMER

REV. 1.0.0

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SLIP BUFFER CONTROL REGISTER (SBCR) (INDIRECT ADDRESS = 0XN0H, 0X16H) .................................. 231

TABLE 42: THE RECEIVE SERIAL CLOCK AND RECEIVE SINGLE-FRAME SYNCHRONIZATION SIGNALS FOR DIF-

FERENT SLIP BUFFER SETTINGS ............................................................................................ 232

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H) ........................ 232

TABLE 43: THE RXTSB[2:0] BITS WHEN THE RECEIVE FRACTIONAL T1 OUTPUT BIT IS SET TO DIFFERENT

VALUES ................................................................................................................................ 233

Figure 43. Interfacing XRT84L38 local Terminal Equipment with Slip Buffer Bypassed and Re-

covered Receive Line Clock as Receive Timing Source ............................................... 234

Figure 44. Waveforms of the Signals Connecting the Receive Payload Data Output Interface

block to the local Terminal Equipment when the Slip Buffer is Bypassed and the Recov-

ered Line Clock is the Timing Source of the Receive Section ...................................... 235

SLIP BUFFER STATUS REGISTER (SBSR) (INDIRECT ADDRESS = 0XNAH, 0X08H) .................................... 236

Figure 45. Interfacing XRT84L38 to local Terminal Equipment with Slip Buffer Enabled or Acts

as FIFO ............................................................................................................................... 237

Figure 46. Waveforms of the Signals that Connect the Receive Payload Data Output Interface

block to the local Terminal Equipment when the Slip Buffer is Enabled .................... 238

FIFO LATENCY REGISTER (FIFOLR) (INDIRECT ADDRESS = 0XN0H, 0X17H) ............................................ 238

Figure 47. Interfacing XRT84L38 to local Terminal Equipment with Slip Buffer Enabled or Acts

as FIFO ............................................................................................................................... 239

5.1.3 High Speed Receive Back-plane Interface ............................................................................. 240

Figure 48. Waveforms of the Signals that Connect the Receive Payload Data Output Interface

block to the local Terminal Equipment when the Slip Buffer is acted as FIFO ........... 240

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H) ........................ 240

TABLE 44: RECEIVE MULTIPLEX ENABLE BIT AND RECEIVE INTERFACE MODE SELECT [1:0] BITS WITH THE

RESULTING RECEIVE BACK-PLANE INTERFACE DATA RATES ................................................... 241

RECEIVE MULTIPLEX ENABLE BIT = 0 ........................................................................................................ 241

RECEIVE MULTIPLEX ENABLE BIT = 1 ........................................................................................................ 242

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H) ........................ 242

TABLE 45: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ..................................................... 243

Figure 49. Interfacing XRT84L38 to local Terminal Equipment using MVIP 2.048Mbit/s Data Bus

244

Figure 50. Timing Diagram of Input signals to the Framer when running at MVIP 2.048Mbit/s ....

244

TABLE 46: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ..................................................... 245

Figure 51. Interfacing XRT84L38 to local Terminal Equipment using 4.096Mbit/s Data Bus .. 246

Figure 52. Timing Diagram of Input signals to the Framer when running at 4.096Mbit/s ....... 246

TABLE 47: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ..................................................... 247

Figure 53. Interfacing XRT84L38 to local Terminal Equipment using 8.192Mbit/s Data Bus .. 248

Figure 54. Timing Diagram of Input signals to the Framer when running at 8.192Mbit/s ....... 248

FIRST OCTET OF 12.352MBIT/S DATA STREAM ......................................................................................... 249

SECOND OCTET OF 12.352MBIT/S DATA STREAM ..................................................................................... 249

THIRD OCTET OF 12.352MBIT/S DATA STREAM ......................................................................................... 249

SIXTH OCTET OF 12.352MBIT/S DATA STREAM ......................................................................................... 250

SEVENTH OCTET OF 12.352MBIT/S DATA STREAM .................................................................................... 250

EIGHTH OCTET OF 12.352MBIT/S DATA STREAM ....................................................................................... 250

NINETH OCTET OF 12.352MBIT/S DATA STREAM ....................................................................................... 250

Figure 55. Interfacing XRT84L38 to local Terminal Equipment using 12.352Mbit/s Data Bus 251

Figure 56. Timing Diagram of Input signals to the Framer when running at 12.352Mbit/s ..... 251

FIRST OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 252

NINTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 252

TENTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 252

THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................ 253

FOURTEENTH OCTET OF 16.384MBIT/S DATA STREAM .............................................................................. 253

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FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 253

SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 253

Figure 57. Interfacing XRT84L38 to local Terminal Equipment using 16.384Mbit/s Data Bus 254

Figure 58. Timing Diagram of Input signals to the Framer when running at Bit-multiplexed

16.384Mbit/s ...................................................................................................................... 254

FIRST OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 255

NINTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 255

ELEVENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................. 255

THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM ............................................................................... 255

FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 256

TENTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 256

TWELFTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 256

FOURTEENTH OCTET OF 16.384MBIT/S DATA STREAM .............................................................................. 256

SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 256

Figure 59. Interfacing XRT84L38 to local Terminal Equipment using 16.384Mbit/s Data Bus 257

Figure 60. Timing Diagram of Input signals to the Framer when running at HMVIP 16.384Mbit/s

257

FIRST OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 258

NINTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 259

ELEVENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................. 259

THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM ............................................................................... 259

FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 259

TENTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 259

TWELFTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 260

FOURTEENTH OCTET OF 16.384MBIT/S DATA STREAM .............................................................................. 260

SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................. 260

Figure 61. Interfacing XRT84L38 to local Terminal Equipment using H.100 16.384Mbit/s Data Bus

261

Figure 62. Timing Diagram of Input signals to the Framer when running at H.100 16.384Mbit/s .

261

6.0 The E1 Transmit Section ...................................................................................................................... 262

6.1 THE E1 TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK ............................................................... 262

6.1.1 Description of the Transmit Payload Data Input Interface Block ............................................ 262

6.1.2 Brief Discussion of the Transmit Payload Data Input Interface Block Operating at XRT84V24 Com-

patible 2.048Mbit/s mode ................................................................................................................ 262

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ....................... 262

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................ 263

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ....................... 264

Figure 63. Interfacing XRT84L38 to local terminal equipment with TxSerClk_n as Transmit Tim-

ing Source ......................................................................................................................... 266

Figure 64. Waveforms of the signals that connect the Transmit Payload Data Input Interface

Block to the local Terminal Equipment with the Transmit Serial clock being the timing

source of the Transmit Section ....................................................................................... 267

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................ 268

Figure 65. Interfacing XRT84L38 to local terminal equipment with OSCCLK driven divided clock

as transmit timing source ................................................................................................ 269

Figure 66. Waverforms of the signals connecting the Transmit Payload Data Input Interface

block to the local Terminal Equipment with the OSCCLK driven divided clock as the tim-

ing source of the Transmit Section ................................................................................. 270

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................ 271

Figure 67. Interfacing XRT84L38 to local terminal equipment with recovered receive line clock

as transmit timing source ................................................................................................ 272

6.1.3 Brief Discussion of the Transmit High-Speed Back-Plane Interface ...................................... 273

Figure 68. Waverforms of the signals connecting the Transmit Payload Data input interface

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block to the local Terminal Equipment with the Recovered Receive Line Clock being the

timing source of transmit section ................................................................................... 273

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ....................... 273

TRANSMIT MULTIPLEX ENABLE BIT = 0 ...................................................................................................... 274

TRANSMIT MULTIPLEX ENABLE BIT = 1 ...................................................................................................... 275

TRANSMIT INTERFACE CONTROL REGISTER (TICR) ........................ (INDIRECT ADDRESS = 0XN0H, 0X20H) 275

Figure 69. Interfacing XRT84L38 to local terminal equipment using MVIP 2.048Mbit/s data bus .

276

Figure 70. Timing diagram of input signals to the framer when running at MVIP 2.048Mbit/s ......

277

Figure 71. Interfacing XRT84L38 to local terminal equipment using 4.096Mbit/s data bus .... 278

Figure 72. Timing diagram of input signals to the framer when running at 4.096Mbit/s mode .....

278

Figure 73. Interfacing XRT84L38 to local terminal equipment using 8.192Mbit/s data bus .... 279

Figure 74. Timing diagram of input signals to the framer when running at 8.192Mbit/s mode .....

280

FIRST OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 281

SECOND OCTET OF 16.384MBIT/S DATA STREAM ..................................................................................... 281

FIFTH OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 281

SIXTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 281

SEVENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 281

EIGHTH OCTET OF 16.384MBIT/S DATA STREAM ....................................................................................... 282

Figure 75. Interfacing XRT84L38 to local terminal equipment using 16.384Mbit/s data bus .. 283

Figure 76. iming signal when the framer is running at Bit-Multiplexed 16.384Mbit/s mode ... 283

FIRST OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 284

THIRD OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 284

FIFTH OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 284

SEVENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 284

SECOND OCTET OF 16.384MBIT/S DATA STREAM ..................................................................................... 285

FOURTH OCTET OF 16.384MBIT/S DATA STREAM ...................................................................................... 285

SIXTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 285

EIGHTH OCTET OF 16.384MBIT/S DATA STREAM ....................................................................................... 285

Figure 77. Interfacing XRT84L38 to local terminal equipment using 16.384Mbit/s data bus .. 286

Figure 78. Timing Signal when the framer is running at HMVIP 16.384Mbit/s mode ............... 286

FIRST OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 287

THIRD OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 287

FIFTH OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 287

SEVENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 288

SECOND OCTET OF 16.384MBIT/S DATA STREAM ..................................................................................... 288

FOURTH OCTET OF 16.384MBIT/S DATA STREAM ...................................................................................... 288

SIXTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 288

EIGHTH OCTET OF 16.384MBIT/S DATA STREAM ....................................................................................... 288

Figure 79. Interfacing XRT84L38 to local terminal equipment using 16.384Mbit/s data bus .. 289

6.2 THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK ................................................................... 290

6.2.1 Description of the Receive Payload Data Output Interface Block ........................................... 290

Figure 80. Timing signal when the framer is running at H.100 16.384Mbit/s mode ................. 290

6.2.2 Brief Discussion of the Receive Payload Data Output Interface Block Operating at XRT84V24

Compatible 2.048Mbit/s mode ......................................................................................................... 291

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H) ........................ 291

SLIP BUFFER CONTROL REGISTER (SBCR).................................... (INDIRECT ADDRESS = 0XN0H, 0X16H) 291

SLIP BUFFER CONTROL REGISTER (SBCR).................................... (INDIRECT ADDRESS = 0XN0H, 0X16H) 292

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H) ........................ 293

Figure 81. Interfacing XRT84L38 to local terminal equipment with slip buffer bypassed and re-

covered receive line clock as receive timing source ..................................................... 295

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Figure 82. Waveforms of the Signals Connecting the Receive Payload Data Output Interface

block to the local Terminal Equipment when the Slip Buffer is Bypassed and the Recov-

ered Line Clock is the Timing Source of the Receive Section ..................................... 296

SLIP BUFFER STATUS REGISTER (SBSR) ...................................... (INDIRECT ADDRESS = 0XNAH, 0X08H) 297

Figure 83. Interfacing XRT84L38 to local terminal equipment with slip buffer enabled or acts as

fifo ...................................................................................................................................... 298

Figure 84. Waveforms of the Signals that Connect the Receive Payload Data Output Interface

block to the local Terminal Equipment when the Slip Buffer is Enabled .................... 299

FIFO LATENCY REGISTER (FIFOL) (INDIRECT ADDRESS = 0XN0H, 0X17H) .............................................. 299

Figure 85. Interfacing XRT84L38 to local terminal equipment with slip buffer enabled or acts as

fifo ...................................................................................................................................... 300

6.2.3 High Speed Receive Back-plane Interface ............................................................................. 301

Figure 86. Waveforms of the Signals that Connect the Receive Payload Data Output Interface

block to the local Terminal Equipment when the Slip Buffer is acted as FIFO .......... 301

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H) ........................ 301

RECEIVE MULTIPLEX ENABLE BIT = 0 ....................................................................................................... 302

RECEIVE MULTIPLEX ENABLE BIT = 1 ....................................................................................................... 303

RECEIVE INTERFACE CONTROL REGISTER (RICR) ..........................(INDIRECT ADDRESS = 0XN0H, 0X22H) 303

Figure 87. Interfacing XRT84L38 to local terminal equipment using MVIP 2.048Mbit/s data bus .

304

Figure 88. Timing Diagram of Input signals to the Framer when running at MVIP 2.048Mbit/s ....

304

Figure 89. Interfacing XRT84L38 to local terminal equipment using 4.096Mbit/s data bus ... 305

Figure 90. Timing Diagram of input signals to the framer when running at 4.096Mbit/s mode ....

306

Figure 91. Interfacing XRT84L38 to local terminal equipment using 8.192Mbit/s data bus ... 307

Figure 92. Timing diagram of input signals to the framer when running at 8.192Mbit/s mode .....

307

FIRST OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 308

SECOND OCTET OF 16.384MBIT/S DATA STREAM ..................................................................................... 308

FIFTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 308

SIXTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 309

SEVENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 309

EIGHTH OCTET OF 16.384MBIT/S DATA STREAM ...................................................................................... 309

Figure 93. Interfacing XRT84L38 to local terminal equipment using 16.384 Mbit/s data bus 310

Figure 94. Timing signal when the framer is running at Bit-Multiplexed 16.384Mbit/s mode 310

FIRST OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 311

THIRD OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 311

FIFTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 311

SEVENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 311

SECOND OCTET OF 16.384MBIT/S DATA STREAM ..................................................................................... 312

FOURTH OCTET OF 16.384MBIT/S DATA STREAM ..................................................................................... 312

SIXTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 312

EIGHTH OCTET OF 16.384MBIT/S DATA STREAM ...................................................................................... 312

Figure 95. Interfacing XRT84L38 to local terminal equipment using 16.384Mbit/s data bus . 313

Figure 96. Timing Signal when the framer is running at HMVIP 16.384Mbit/s mode .............. 313

FIRST OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 314

THIRD OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 314

FIFTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 314

SEVENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 314

SECOND OCTET OF 16.384MBIT/S DATA STREAM ..................................................................................... 315

FOURTH OCTET OF 16.384MBIT/S DATA STREAM ..................................................................................... 315

SIXTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 315

EIGHTH OCTET OF 16.384MBIT/S DATA STREAM ...................................................................................... 315

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Figure 97. Interfacing XRT84L38 to local terminal equipment using 16.384Mbit/s data bus .. 316

Figure 98. Timing Signal when the framer is running at H.100 16.384Mbit/s mode ................. 316

7.0 DS1 Overhead Interface Block ............................................................................................................. 317

7.1 DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK .......................................................................... 317

7.1.1 Description of the DS1 Transmit Overhead Input Interface Block ........................................... 317

7.1.2 Configure the DS1 Transmit Overhead Input Interface module as source of the Facility Data Link

(FDL) bits in ESF framing format mode ........................................................................................... 317

Figure 99. Block Diagram of the DS1 Transmit Overhead Input Interface of the XRT84L38 .. 317

TRANSMIT DATA LINK SELECT REGISTER (TDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) ....................... 318

7.1.3 Configure the DS1 Transmit Overhead Input Interface module as source of the Signaling Framing

(Fs) bits in N or SLC®96 framing format mode ................................................................................ 319

Figure 100. DS1 Transmit Overhead Input Interface Timing in ESF Framing Format mode ... 319

TRANSMIT DATA LINK SELECT REGISTER (TDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) ....................... 319

7.1.4 Configure the DS1 Transmit Overhead Input Interface module as source of the Remote Signaling

(R) bits in T1DM framing format mode ............................................................................................. 320

Figure 101. DS1 Transmit Overhead Input Timing in N or SLC®96 Framing Format Mode .... 320

TRANSMIT DATA LINK SELECT REGISTER (TDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) .......................... 320

Figure 102. DS1 Transmit Overhead Input Interface module in T1DM Framing Format mode ......

320

7.2 DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ......................................................................... 321

7.2.1 Description of the DS1 Receive Overhead Output Interface Block ......................................... 321

7.2.2 Configure the DS1 Receive Overhead Output Interface module as destination of the Facility Data

Link (FDL) bits in ESF framing format mode .................................................................................... 321

Figure 103. Block Diagram of the DS1 Receive Overhead Output Interface of XRT84L38 ..... 321

RECEIVE DATA LINK SELECT REGISTER (TDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) ......................... 322

7.2.3 Configure the DS1 Receive Overhead Output Interface module as destination of the Signaling

Framing (Fs) bits in N or SLC®96 framing format mode .................................................................. 323

Figure 104. DS1 Receive Overhead Output Interface module in ESF framing format mode .. 323

RECEIVE DATA LINK SELECT REGISTER (TDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) ........................ 323

7.2.4 Configure the DS1 Receive Overhead Output Interface module as destination of the Remote Sig-

naling (R) bits in T1DM framing format mode .................................................................................. 324

Figure 105. DS1 Receive Overhead Output Interface Timing in N or SLC®96 Framing Format

mode ................................................................................................................................... 324

RECEIVE DATA LINK SELECT REGISTER (RDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) ........................ 324

Figure 106. DS1 Receive Overhead Output Interface Timing in T1DM Framing Format mode .....

325

8.0 E1 Overhead Interface Block ............................................................................................................... 326

8.1 E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ............................................................................. 326

8.1.1 Description of the E1 Transmit Overhead Input Interface Block ............................................. 326

8.1.2 Configure the E1 Transmit Overhead Input Interface module as source of the National Bit Se-

quence in E1 framing format mode .................................................................................................. 326

Figure 107. Block Diagram of the E1 Transmit Overhead Input Interface of XRT84L38 ......... 326

SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H) .................................. 327

TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) ....

327

8.2 E1 RECEIVE OVERHEAD INTERFACE .................................................................................................... 328

8.2.1 Description of the E1 Receive Overhead Output Interface Block ........................................... 328

Figure 108. E1 Transmit Overhead Input Interface Timing ........................................................ 328

8.2.2 Configure the E1 Receive Overhead Output Interface module as source of the National Bit Se-

quence in E1 framing format mode .................................................................................................. 329

Figure 109. Block Diagram of the E1 Receive Overhead Output Interface of XRT84L38 ........ 329

RECEIVE SIGNALING AND DATA LINK SELECT REGISTER (RSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0CH) ....

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Figure 110. E1 Receive Overhead Output Interface Timing ...................................................... 330

9.0 DS1 Transmit Framer Block ................................................................................................................ 331

9.1 HOW TO CONFIGURE XRT84L38 TO OPERATE IN DS1 MODE ............................................................. 331

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................ 331

FRAMING SELECT REGISTER (FSR) (INDIRECT ADDRESS = 0XN0H, 0X07H) ............................................. 331

9.2 HOW TO CONFIGURE THE FRAMER TO TRANSMIT DATA IN VARIOUS DS1 FRAMING FORMATS ............... 332

9.2.1 How to configure the framer to input framing alignment bits from different sources .............. 332

FRAMING SELECT REGISTER (FSR) (I..............................................NDIRECT ADDRESS = 0XN0H, 0X07H) 332

9.2.2 How to configure the framer to input CRC-6 bits from different sources ................................ 333

SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H) .................................. 333

9.3 HOW TO CONFIGURE THE FRAMER TO APPLY DATA AND SIGNALING CONDITIONING TO DS1 PAYLOAD DATA

ON A PER-CHANNEL BASIS .............................................................................................................................. 334

9.3.1 How to apply User IDLE Code to the DS1 payload data ........................................................ 335

TRANSMIT CHANNEL CONTROL REGISTER (TCCR) (INDIRECT ADDRESS = 0XN2H, 0X00H - 0X1FH) .......... 335

USER IDLE CODE REGISTER (UCR) (INDIRECT ADDRESS = 0XN02H, 0X20H - 0X37H) ............................ 335

9.4 HOW TO CONFIGURE THE XRT84L38 FRAMER TO APPLY ZERO CODE SUPPRESSION TO DS1 PAYLOAD DATA

ON A PER-CHANNEL BASIS .............................................................................................................................. 336

9.5 HOW TO CONFIGURE THE XRT84L38 FRAMER TO TRANSMIT ROBBED-BIT SIGNALING INFORMATION .... 336

9.5.1 Brief Discussion of Robbed-bit Signaling in DS1 Framing Format ......................................... 336

TRANSMIT CHANNEL CONTROL REGISTER (TCCR) (INDIRECT ADDRESS = 0XN2H, 0X00H - 0X1FH) ......... 336

9.5.2 Configure the framer to transmit Robbed-bit Signaling .......................................................... 337

TRANSMIT SIGNALING CONTROL REGISTER (TSCR) (INDIRECT ADDRESS = 0XN2H, 0X40H - 0X57H) ....... 338

Figure 111. Timing Diagram of the TxSig_n Input ...................................................................... 339

TRANSMIT INTERFACE CONTROL REGISTER (TICR).........................(INDIRECT ADDRESS = 0XN0H, 0X20H) 339

9.6 HOW TO CONFIGURE THE XRT84L38 FRAMER TO GENERATE AND TRANSMIT ALARMS AND ERROR INDICA-

TIONS TO REMOTE TERMINAL .......................................................................................................................... 340

9.6.1 Brief discussion of alarms and error conditions ...................................................................... 340

TRANSMIT SIGNALING CONTROL REGISTER (TSCR) (INDIRECT ADDRESS = 0XN2H, 0X40H - 0X57H) ....... 340

Figure 112. Simple Diagram of DS1 System Model .................................................................... 341

Figure 113. Generation of Yellow Alarm by the CPE upon detection of line failure ................ 342

Figure 114. Generation of AIS by the Repeater upon detection of Yellow Alarm originated by the

CPE .................................................................................................................................... 343

9.6.2 How to configure the framer to transmit AIS ........................................................................... 344

Figure 115. Generation of Yellow Alarm by the CPE upon detection of AIS originated by the Re-

peater ................................................................................................................................. 344

9.6.3 How to configure the framer to generate Red Alarm .............................................................. 345

9.6.4 How to configure the framer to transmit Yellow Alarm ........................................................... 345

ALARM GENERATION REGISTER (AGR)...........................................(INDIRECT ADDRESS = 0XN0H, 0X08H) 345

ALARM GENERATION REGISTER (AGR)...........................................(INDIRECT ADDRESS = 0XN0H, 0X08H) 347

10.0 DS1 Receive Framer Block ................................................................................................................ 348

10.1 HOW TO CONFIGURE XRT84L38 TO OPERATE IN DS1 MODE ........................................................... 348

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................ 348

FRAMING SELECT REGISTER (FSR) (INDIRECT ADDRESS = 0XN0H, 0X07H) ............................................. 348

10.2 HOW TO CONFIGURE THE FRAMER TO RECEIVE DATA IN VARIOUS DS1 FRAMING FORMATS ............... 349

10.3 HOW TO CONFIGURE THE FRAMER TO APPLY DATA AND SIGNALING CONDITIONING TO RECEIVED DS1 PAY-

LOAD DATA ON A PER-CHANNEL BASIS ............................................................................................................ 349

FRAMING SELECT REGISTER (FSR) (INDIRECT ADDRESS = 0XN0H, 0X07H) .............................................. 349

RECEIVE CHANNEL CONTROL REGISTER (RCCR) (INDIRECT ADDRESS = 0XN2H, 0X60H - 0X7FH) ........... 351

RECEIVE USER IDLE CODE REGISTER (UCR) (INDIRECT ADDRESS = 0XN02H, 0X80H - 0X97H) ............... 351

10.4 HOW TO CONFIGURE THE XRT84L38 FRAMER TO APPLY ZERO CODE SUPPRESSION TO RECEIVED DS1

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PAYLOAD DATA ON A PER-CHANNEL BASIS ...................................................................................................... 352

10.5 HOW TO CONFIGURE THE XRT84L38 FRAMER TO EXTRACT ROBBED-BIT SIGNALING INFORMATION .... 352

10.5.1 Configure the framer to receive and extract Robbed-bit Signaling ....................................... 352

RECEIVE CHANNEL CONTROL REGISTER (RCCR) (INDIRECT ADDRESS = 0XN2H, 0X60H - 0X7FH) ............ 352

RECEIVE SIGNALING CONTROL REGISTER (RSCR) (INDIRECT ADDRESS = 0XN2H, 0XA0H - 0XB7H) ......... 353

FRAMER INTERRUPT ENABLE REGISTER (FIER) (INDIRECT ADDRESS = 0XNAH, 0X05H) ........................... 353

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H) ............................... 354

FRAMER INTERRUPT STATUS REGISTER (FISR) (INDIRECT ADDRESS = 0XNAH, 0X04H) ........................... 354

SIGNALING CHANGE REGISTERS (SCR) (INDIRECT ADDRESS = 0XN0H, 0X0DH - 0X0FH) ......................... 354

RECEIVE SIGNALING REGISTER ARRAY (RSRA) (INDIRECT ADDRESS = 0XN4H, 0X00H - 0X17H) .............. 355

RECEIVE INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ......................... 355

Figure 116. Timing Diagram of the RxSig_n Output pin ............................................................. 356

RECEIVE SIGNALING CONTROL REGISTER (RSCR) (INDIRECT ADDRESS = 0XN2H, 0XA0H - 0XB7H) ......... 356

RECEIVE SIGNALING CONTROL REGISTER (RSCR) (INDIRECT ADDRESS = 0XN2H, 0XA0H - 0XB7H) ......... 357

RECEIVE SUBSTITUTION SIGNALING REGISTER (RSSR) (INDIRECT ADDRESS = 0XN02H, 0X80H - 0X97H) . 357

10.6 HOW TO CONFIGURE THE FRAMER TO DETECT ALARMS AND ERROR CONDITIONS .............................. 358

10.6.1 How to configure the framer to detect AIS Alarm .................................................................. 358

RECEIVE SIGNALING CONTROL REGISTER (RSCR) (INDIRECT ADDRESS = 0XN2H, 0X40H - 0X57H) ......... 358

ALARM GENERATION REGISTER (AGR) (INDIRECT ADDRESS = 0XN0H, 0X08H) ........................................ 359

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H) ........ 359

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) .............................. 359

10.6.2 How to configure the framer to detect Red Alarm ................................................................. 360

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ............................ 360

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ........................... 360

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H) ........ 361

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) ............................... 361

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ............................ 361

10.6.3 How to configure the framer to detect Yellow Alarm ............................................................. 362

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ............................ 362

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H) ......... 362

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) ............................... 362

10.6.4 How to configure the framer to detect Bipolar Violation ........................................................ 363

ALARM AND ERROR STATUS REGISTER (AESR).............................(INDIRECT ADDRESS = 0XNAH, 0X02H) 363

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ........................... 363

10.6.5 How to configure the framer to detect Loss of Signal ........................................................... 364

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H) ........ 364

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) ............................... 364

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ........................... 364

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H) ......... 365

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) ............................... 365

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ........................... 365

11.0 E1 Transmit Framer Block ................................................................................................................. 366

11.1 HOW TO CONFIGURE XRT84L38 TO OPERATE IN E1 MODE .............................................................. 366

11.2 HOW TO CONFIGURE THE FRAMER TO TRANSMIT AND RECEIVE DATA IN E1 FRAMING FORMAT ........... 366

11.2.1 How to configure the framer to choose FAS searching algorithm ......................................... 366

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................. 366

11.2.2 How to configure the framer to enable CRC-4 Multi-frame alignment and select the locking crite-

ria ..................................................................................................................................................... 367

11.2.3 How to configure the framer to enable CAS Multi-frame alignment ...................................... 367

FRAMING SELECT REGISTER (FSR) (INDIRECT ADDRESS = 0XN0H, 0X07H) .............................................. 367

11.2.4 How to configure the framer to input the framing alignment bits from different sources ....... 368

FRAMING SELECT REGISTER (FSR) (INDIRECT ADDRESS = 0XN0H, 0X07H) .............................................. 368

11.2.5 How to configure the framer to input CRC-4 bits from different sources ............................... 369

XI

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XRT84L38

OCTAL T1/E1/J1 FRAMER

REV.1.0.0

11.2.6 How to configure the framer to input E bits from different sources ....................................... 369

SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H) .................................. 369

SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H) ................................. 369

11.3 HOW TO CONFIGURE THE FRAMER TO APPLY DATA AND SIGNALING CONDITIONING TO E1 PAYLOAD DATA

ON A PER-CHANNEL BASIS .............................................................................................................................. 370

SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H) ................................. 370

TRANSMIT CHANNEL CONTROL REGISTER (TCCR) (INDIRECT ADDRESS = 0XN2H, 0X00H - 0X1FH) .......... 371

11.4 HOW TO CONFIGURE THE XRT84L38 FRAMER TO TRANSMIT SIGNALING INFORMATION ...................... 372

11.4.1 Brief Discussion of Common Channel Signaling in E1 Framing Format .............................. 372

11.4.2 Brief Discussion of Channel Associated Signaling in E1 Framing Format ........................... 372

USER IDLE CODE REGISTER (UCR) (INDIRECT ADDRESS = 0XN02H, 0X20H - 0X3FH) ............................. 372

11.4.3 Configure the framer to transmit Channel Associated Signaling .......................................... 373

TRANSMIT SIGNALING CONTROL REGISTER (TSCR) (INDIRECT ADDRESS = 0XN2H, 0X40H - 0X5FH) ....... 374

Figure 117. Timing Diagram of the TxSig_n Input ...................................................................... 375

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ...................... 375

Figure 118. Timing Diagram of the TxOH_n Input ...................................................................... 375

11.5 HOW TO CONFIGURE THE XRT84L38 FRAMER TO GENERATE AND TRANSMIT ALARMS AND ERROR INDICA-

TIONS TO REMOTE TERMINAL .......................................................................................................................... 376

11.5.1 Brief discussion of alarms and error conditions .................................................................... 376

TRANSMIT SIGNALING CONTROL REGISTER (TSCR) (INDIRECT ADDRESS = 0XN2H, 0X40H - 0X57H) ....... 376

Figure 119. Simple Diagram of E1 system model ....................................................................... 377

Figure 120. Generation of Yellow Alarm by the Repeater upon detection of line failure ........ 378

Figure 121. Generation of AIS by the Repeater upon detection of line failure ........................ 379

Figure 122. Generation of Yellow Alarm by the CPE upon detection of AIS originated by the Re-

peater ................................................................................................................................. 380

Figure 123. Generation of CAS Multi-frame Yellow Alarm and AIS16 by the Repeater .......... 381

11.5.2 How to configure the framer to transmit AIS ......................................................................... 382

Figure 124. Generation of CAS Multi-fram Yellow Alarm by the CPE upon detection of “AIS16”

pattern sent by the Repeater ........................................................................................... 382

11.5.3 How to configure the framer to generate Red Alarm ............................................................ 383

11.5.4 How to configure the framer to transmit Yellow Alarm ......................................................... 383

ALARM GENERATION REGISTER (AGR) (INDIRECT ADDRESS = 0XN0H, 0X08H) ........................................ 383

ALARM GENERATION REGISTER (AGR) (INDIRECT ADDRESS = 0XN0H, 0X08H) ........................................ 385

12.0 E1 Receive Framer Block ................................................................................................................... 386

12.1 HOW TO CONFIGURE XRT84L38 TO OPERATE IN E1 MODE .............................................................. 386

12.2 HOW TO CONFIGURE THE FRAMER TO RECEIVE DATA IN VARIOUS E1 FRAMING FORMATS ................. 386

12.2.1 How to configure the framer to choose FAS searching algorithm ........................................ 386

CLOCK SELECT REGISTER (CSR)...................................................(INDIRECT ADDRESS = 0XN0H, 0X00H) 386

12.2.2 How to configure the framer to enable CRC-4 Multi-frame alignment and select the locking crite-

ria ..................................................................................................................................................... 387

12.2.3 How to configure the framer to enable CAS Multi-frame alignment ..................................... 387

FRAMING SELECT REGISTER (FSR) (INDIRECT ADDRESS = 0XN0H, 0X07H) ............................................. 387

12.3 HOW TO CONFIGURE THE FRAMER TO APPLY DATA AND SIGNALING CONDITIONING TO RECEIVED E1 PAY-

LOAD DATA ON A PER-CHANNEL BASIS ............................................................................................................ 388

FRAMING SELECT REGISTER (FSR) (INDIRECT ADDRESS = 0XN0H, 0X07H) ............................................. 388

RECEIVE CHANNEL CONTROL REGISTER (RCCR) (INDIRECT ADDRESS = 0XN2H, 0X60H - 0X7FH) .......... 389

12.4 HOW TO CONFIGURE THE XRT84L38 FRAMER TO EXTRACT ROBBED-BIT SIGNALING INFORMATION ... 390

12.4.1 Configure the framer to receive and extract Robbed-bit Signaling ....................................... 390

RECEIVE USER IDLE CODE REGISTER (UCR) (INDIRECT ADDRESS = 0XN02H, 0X80H - 0X97H) .............. 390

RECEIVE SIGNALING CONTROL REGISTER (RSCR) (INDIRECT ADDRESS = 0XN2H, 0XA0H - 0XB7H) ........ 390

FRAMER INTERRUPT ENABLE REGISTER (FIER) (INDIRECT ADDRESS = 0XNAH, 0X05H) ............................ 391

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H) ............................. 391

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OCTAL T1/E1/J1 FRAMER

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FRAMER INTERRUPT STATUS REGISTER (FISR) (INDIRECT ADDRESS = 0XNAH, 0X04H) ........................... 391

SIGNALING CHANGE REGISTERS (SCR) (INDIRECT ADDRESS = 0XN0H, 0X0DH - 0X10H) ......................... 392

RECEIVE SIGNALING REGISTER ARRAY (RSRA) (INDIRECT ADDRESS = 0XN4H, 0X00H - 0X1FH) .............. 392

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ........................ 393

Figure 125. Timing diagram of RxSig_n Output pin ................................................................... 393

Figure 126. Timing diagram of the RxOH_n Output pin ............................................................. 393

RECEIVE SIGNALING CONTROL REGISTER (RSCR) (INDIRECT ADDRESS = 0XN2H, 0XA0H - 0XBFH) ......... 394

RECEIVE SIGNALING CONTROL REGISTER (RSCR) (INDIRECT ADDRESS = 0XN2H, 0XA0H - 0XBFH) ........ 394

RECEIVE SUBSTITUTION SIGNALING REGISTER (RSSR) (INDIRECT ADDRESS = 0XN02H, 0X80H - 0X9FH) 394

12.5 HOW TO CONFIGURE THE FRAMER TO DETECT ALARMS AND ERROR CONDITIONS .............................. 395

RECEIVE SIGNALING CONTROL REGISTER (RSCR) (INDIRECT ADDRESS = 0XN2H, 0X40H - 0X5FH) ......... 395

12.5.1 How to configure the framer to detect AIS Alarm .................................................................. 396

ALARM GENERATION REGISTER (AGR) (INDIRECT ADDRESS = 0XN0H, 0X08H) ........................................ 397

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H) ........ 397

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) .............................. 397

12.5.2 How to configure the framer to detect Red Alarm ................................................................. 398

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ............................ 398

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H) ........ 399

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) .............................. 399

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ........................... 399

12.5.3 How to configure the framer to detect Yellow Alarm ............................................................. 400

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ........................... 400

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H) ......... 400

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) .............................. 400

12.5.4 How to configure the framer to detect CAS Multi-frame Yellow Alarm .................................. 401

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ........................... 401

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H) ........ 401

12.5.5 How to configure the framer to detect Bipolar Violation ........................................................ 402

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) .............................. 402

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ........................... 402

12.5.6 How to configure the framer to detect Loss of Signal ........................................................... 403

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H) ........ 403

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) ............................... 403

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ............................ 403

13.0 DS1 HDLC Controller Block ............................................................................................................... 404

13.1 DS1 TRANSMIT HDLC CONTROLLER BLOCK ..................................................................................... 404

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H) ......... 404

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) ............................... 404

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ............................ 404

13.1.1 Description of the DS1 Transmit HDLC Controller Block ...................................................... 405

TRANSMIT DATA LINK SELECT REGISTER (TSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) .................... 405

13.1.2 How to configure XRT84L38 to transmit data link information through D or E Channels ..... 406

DATA LINK CONTROL REGISTER (DLCR) INDIRECT ADDRESS = 0XN0H, 0X13H) ........................................ 406

DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H) ....................................... 406

TRANSMIT CHANNEL CONTROL REGISTER (TCCR) (INDIRECT ADDRESS = 0XN2H, 0X00H - 0X1FH) .......... 406

13.1.3 Transmit BOS (Bit Oriented Signaling) Processor ................................................................ 407

TRANSMIT DATA LINK SELECT REGISTER (TSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) .................... 407

TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X14H) ............ 408

DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H) ....................................... 409

DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H) ...................................... 409

DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H) ....................................... 409

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ....................... 410

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XRT84L38

OCTAL T1/E1/J1 FRAMER

REV.1.0.0

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H) ............................. 410

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ........................................ 410

13.1.4 Transmit MOS (Message Oriented Signaling) or LAPD Controller ....................................... 411

DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H) ..................................... 411

Figure 127. LAPD Controller ......................................................................................................... 411

Figure 128. LAPD Frame Structure .............................................................................................. 412

TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X14H) ............ 415

TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X14H) ........... 416

DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H) ...................................... 416

DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H) ..................................... 417

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ..................... 417

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H) ............................. 418

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ........................................ 418

13.1.5 Transmit SLCâ96 Data link Controller .................................................................................. 419

DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H) ..................................... 419

FRAMING SELECT REGISTER (FSR) (INDIRECT ADDRESS = 0XN0H, 0X07H) ............................................. 420

TRANSMIT SLC®96 MESSAGE REGISTERS ............................................................................................... 420

TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X14H) ........... 421

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ...................... 421

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H) .............................. 422

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ........................................ 422

DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H) ..................................... 422

13.2 DS1 RECEIVE HDLC CONTROLLER BLOCK ....................................................................................... 423

13.2.1 Description of the DS1 Receive HDLC Controller Block ...................................................... 423

DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H) ..................................... 423

RECEIVE DATA LINK SELECT REGISTER (RSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0CH) ..................... 424

13.2.2 How to configure XRT84L38 to Receive data link information through D or E Channels ..... 425

DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H) ..................................... 425

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ........................................ 425

RECEIVE CHANNEL CONTROL REGISTER (RCCR) (INDIRECT ADDRESS = 0XN2H, 0X60H - 0X7FH) .......... 425

13.2.3 Receive BOS (Bit Oriented Signaling) Processor ................................................................. 426

RECEIVE DATA LINK SELECT REGISTER (RSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0CH) ..................... 426

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ..................... 426

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H) ............................. 427

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ........................................ 427

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ..................... 427

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ........................................ 428

RECEIVE DATA LINK BYTE COUNT REGISTER (RDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X15H) .............. 428

13.2.4 Receive LAPD Controller ...................................................................................................... 429

RECEIVE DATA LINK BYTE COUNT REGISTER (RDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X15H) ............. 429

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ......................................... 429

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ..................... 430

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H) ............................. 430

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ........................................ 431

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ..................... 431

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ........................................ 432

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ..................... 432

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ........................................ 432

RECEIVE DATA LINK BYTE COUNT REGISTER (RDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X15H) ............. 433

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ........................................ 433

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OCTAL T1/E1/J1 FRAMER

REV. 1.0.0

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13.2.5 Receive SLCâ96 Data link Controller .................................................................................... 434

RECEIVE SLC®96 MESSAGE REGISTERS .................................................................................................. 434

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ...................... 435

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H) .............................. 435

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ......................................... 435

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ...................... 436

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ........................................ 436

RECEIVE DATA LINK BYTE COUNT REGISTER (RDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X15H) ............. 436

14.0 E1 HDLC Controller Block .................................................................................................................. 438

14.1 E1 TRANSMIT HDLC CONTROLLER BLOCK ........................................................................................ 438

14.1.1 Description of the E1 Transmit HDLC Controller Block ......................................................... 438

SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H) .................................. 438

14.1.2 How to configure XRT84L38 to transmit data link information through the National bits (Sa4

through Sa8) .................................................................................................................................... 439

DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H) ...................................... 439

TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) ...

439

14.1.3 How to configure XRT84L38 to transmit data link information through Timeslot 16 octet .... 440

14.1.4 How to configure XRT84L38 to transmit data link information through D or E Channels ..... 440

TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) ...

440

TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) ...

440

14.1.5 Transmit BOS (Bit Oriented Signaling) Processor ................................................................ 441

14.1.6 Transmit MOS (Message Oriented Signaling) or LAPD Controller ....................................... 441

14.2 E1 RECEIVE HDLC CONTROLLER BLOCK .......................................................................................... 441

14.2.1 Description of the E1 Receive HDLC Controller Block .......................................................... 441

TRANSMIT CHANNEL CONTROL REGISTER (TCCR) (INDIRECT ADDRESS = 0XN2H, 0X00H - 0X1FH) ......... 441

14.2.2 How to configure XRT84L38 to receive data link information through the National bits (Sa4

through Sa8) .................................................................................................................................... 442

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ........................................ 442

RECEIVE SIGNALING AND DATA LINK SELECT REGISTER (RSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0CH) ....

442

14.2.3 How to configure XRT84L38 to receive data link information through Timeslot 16 octet ...... 443

RECEIVE SIGNALING AND DATA LINK SELECT REGISTER (RSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0CH) ....

443

14.2.4 How to configure XRT84L38 to receive data link information through D or E Channels ....... 444

14.2.5 Receive BOS (Bit Oriented Signaling) Processor ................................................................. 444

14.2.6 Receive LAPD Controller ...................................................................................................... 444

RECEIVE SIGNALING AND DATA LINK SELECT REGISTER (RSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0CH) ....

444

RECEIVE CHANNEL CONTROL REGISTER (RCCR) (INDIRECT ADDRESS = 0XN2H, 0X60H - 0X7FH) ........... 444

15.0 Transmit LIU Interface ........................................................................................................................ 446

16.0 Receive LIU Interface .......................................................................................................................... 446

ORDERING INFORMATION ........................................................................................................... 447

PACKAGE DIMENSIONS ............................................................................................................................. 447

REVISIONS ............................................................................................................................................... 448

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REV.1.0.0

TABLE 1: LIST BY PIN NUMBER

PIN NAME

A1

TCK

B1

TDI

C1

RxNEG_0

D1

RxLineClk_0

A2

A3

A4

A5

A6

RxTSb0_0

RxSig_0

B2

B3

B4

B5

B6

RxSerClk_0

C2

C3

C4

C5

C6

TMS

D2

D3

D4

D5

D6

RxLOS_0

TDO

RxSync_0

RxCASMSync_0

TxOHClk_0

NC

RxMSync_0

RxCRCMSync_0

TRST

RxTSb2_0

RxTSChn_0

RxTSClk_0

RxOHClk_0

RxSer_0

RxTSb3_0

Rx8kHz_0

RxTSb1_0

RxFrTD_0

TxSer_0

TxMSync_0

TxInClk_0

TxSync_0

A7

A8

TxOH_0

B7

B8

NC

C7

C8

RxOH_0

D7

D8

RxTSb4_0

TxTSb2_0

Tx12.352MHz_0

TxTSb3_0

TxOHSync_0

TxTSb0_0

TxSig_0

TxSerClk_0

A9

RxSer_1

B9

RxSerClk_1

C9

RxMSync_1

RxCRCMSync_1

D9

TxTSb1_0

TxFrTD_0

A10

A11

A12

A13

RxTSb1_1

RxFrTD_1

B10

B11

B12

B13

RxOH_1

C10

C11

C12

C13

TxTSb4_0

D10

D11

D12

D13

TxTSClk_0

RxCASMSync_1

RxSync_1

RxOHClk_1

RxTSb2_1

RxTSChn_1

RxTSClk_1

TxSync_1

NC

RxTSb0_1

RxSig_1

RxTSb4_1

TxSer_1

TxMSync_1

TxInClk_1

NC

RxTSb3_1

Rx8kHz_1

A14

A15

B14

B15

TxTSClk_1

C14

C15

TxOH_1

D14

D15

NC

TxTSb2_1

Tx12.352MHz_1

TxTSb1_1

TxFrTD_1

TxOHClk_1

TxTSb0_1

TxSig_1

A16

TxSerClk_1

B16

RxSync_2

C16

NC

D16

TxTSb3_1

TxOHSync_1

A17

A18

RxSerClk_2

B17

B18

NC

C17

C18

TxTSb4_1

RxSer_2

D17

D18

NC

RxTSb0_2

RxSig_2

RxCASMSync_2

RxTSClk_2

A19

A20

RxMSync_2

RxCRCMSync_2

B19

B20

RxTSb1_2

RxFrTD_2

C19

C20

RxOH_2

D19

D20

RxOHClk_2

TxSerClk_2

NC

RxTSb2_2

RxTSChn_2

RxTSb3_2

Rx8kHz_2

A21

A22

TxSync_2

B21

B22

RxTSb4_2

C21

C22

TxTSClk_2

D21

D22

TxOHClk_2

TxTSb4_2

TxMSync_2

TxInClk_2

TxSer_2

TxTSb1_2

TxFrTD_2

A23

A24

A25

A26

TxTSb0_2

TxSig_2

B23

B24

B25

B26

TxTSb2_2

Tx12.352MHz_2

C23

C24

C25

C26

NC

D23

D24

D25

D26

TxOH_2

RxCASMSync_3

TxTSClk_3

TxTSb3_2

TxOHSync_2

RxSer_3

RxOHClk_3

RxOH_3

RxSync_3

RxTSClk_3

RxTSb0_3

RxSig_3

RxMSync_3

RxCRCMSync_3

RxTSb1_3

RxFrTD_3

RxTSb3_3

Rx8kHz_3

16

XRT84L38

OCTAL T1E1/J1 FRAMER

REV. 1.0.0

áç

PIN NAME

E1

NC

F1

RxNEG_1

G1

RxLineClk_1

H1

RxPOS_2

E2

E3

NC

F2

F3

TxLineClk_0

G2

G3

TxLineClk_1

RxPOS_1

H2

H3

TxNEG_1

TxMX_1

TxPOS_0

TxNRZ_0

TxNEG_0

TxMX_0

TxPOS_1

TxNRZ_1

E4

RxPOS_0

F4

NC

G4

LOS_0

H4

RxLOS_1

E23

RxSerClk_3

F23

TxOH_3

G23

TxSerClk_3

H23

TxTSb1_3

TxFrTD_3

E24

RxTSb2_3

RxTSChn_3

F24

TxOHClk_3

TxSer_3

G24

TxTSb0_3

TxSig_3

H24

TxTSb3_3

TxOHSync_3

E25

E26

TxSync_3

F25

F26

G25

G26

CS

H25

H26

NC

RxTSb4_3

TxMSync_3

TxInClk_3

WR

NC

PIN NAME

J1

RxLOS_2

K1

LOS_2

L1

TxPOS_3

TxNRZ_3

M1

GPO3

CS0

J2

J3

J4

TxLineClk_2

RxNEG_2

LOS_1

K2

K3

K4

TxNEG_2

TxMX_2

L2

L3

RxPOS_3

M2

M3

LOS_3

TxPOS_2

TxNRZ_2

RxNEG_3

TxNEG_3

TxMX_3

RxLineClk_2

L4

RxLOS_3

VDD

A4

M4

RxLineClk_3

L11

L12

L13

L14

L15

L16

L23

M11

M12

M13

M14

M15

M16

M23

VDD

VSS

VDD

J23

TxTSb2_3

K23

A6

NC

Tx12.352MHz_3

J24

J25

J26

Data7

TxTSb4_3

A5

K24

K25

K26

Data6

Data5

NC

L24

L25

L26

Data4

Blast

A3

M24

M25

M26

INT

µPType2

A2

17

áç

XRT84L38

OCTAL T1E1/J1 FRAMER

REV.1.0.0

PIN NAME

N1

GPO0

SDO0

P1

GPO7

CS1

R1

GPO4

SDO1

T1

OSCClk

N2

N3

N4

GPO2

SClk0

P2

P3

P4

GPO6

SClk1

R2

R3

R4

RxPOS_4

T2

T3

T4

RxNEG_4

GPO1

SDI0

Test Mode

Reset

RxLineClk_4

TxLineClk_3

GPO5

SDI1

LOP

TxPOS_4

TxNRZ_4

N11

N12

N13

N14

N15

N16

N23

N24

N25

N26

VDD

R11

R12

R13

R14

R15

R16

R23

R24

R25

R26

VDD

VSS

T11

T12

T13

T14

T15

T16

T23

T24

T25

T26

VSS

P13

P14

VSS

VDD

µPClk

Data0

Data1

RD

VSS

VDD

VSS

A1

P23

P24

P25

P26

RDY_DTACK

µPType1

DBEn

ACK1

Indirect

µPType0

Req0

ALE_AS

Data3

Data2

A0

PIN NAME

U1

RxLOS_4

V1

TxNEG_4

TxMX_4

W1

RxNEG_5

Y1

RxLOS_5

U2

U3

8kHzRef

NC

V2

V3

LOS_4

W2

W3

RxPOS_5

Y2

Y3

TxNEG_5

TxMX_5

NC

TxPOS_5

TxNRZ_5

TxLineClk_5

U4

NC

V4

TxLineClk_4

RxOHClk_4

W4

RxLineClk_5

Y4

NC

U23

Req1

V23

W23

RxTSb3_4

Rx8kHz_4

Y23

TxSerClk_4

U24

U25

U26

RxSerClk_4

NC

V24

V25

V26

RxTSClk_4

W24

W25

W26

RxTSb0_4

RxSig_4

Y24

Y25

Y26

RxCASMSync_4

RxMSync_4

RxCRCMSync_4

RxOH_4

RxTSb2_4

RxTSChn_4

ACK0

RxSync_4

RxSer_4

RxTSb1_4

RxFrTD_4

18

XRT84L38

OCTAL T1E1/J1 FRAMER

REV. 1.0.0

áç

PIN NAME

AA1

LOS_5

AB1

RxNEG_6

AC1

TxNEG_6

TxMX_6

AD1

RxNEG_7

AA2

RxPOS_6

AB2

TxPOS_6

TxNRZ_6

AC2

RxPOS_7

AD2

TxPOS_7

TxNRZ_7

AA3

AA4

RxLOS_6

AB3

AB4

LOS_6

AC3

AC4

AC5

AC6

TxLineClk_6

TxLineClk_7

TxTSClk_7

TxSerClk_7

RxLineClk_6

RxLOS_7

AD5

AD6

TxOH_7

TxTSb1_7

TxFrTD_7

AC7

AC8

TxTSb0_7

TxSig_7

AD7

AD8

RxSerClk_7

RxMSync_7

RxSer_7

RxCRCMSync_7

AC9

AC10

AC11

AC12

RxTSClk_7

RxCASMSync_7

RxOH_7

AD9

AD10

AD11

AD12

TxSerClk_6

RxOHClk_7

TxTSb4_6

TxTSb3_6

RxCASMSync_6

TxOHSync_6

AC13

TxTSb0_6

TxSig_6

AD13

TxOHClk_6

AC14

AC15

AC16

TxOH_6

AD14

AD15

AD16

RxSync_6

RxTSb4_6

RxSerClk_6

RxTSb0_6

RxSig_6

RxTSb2_6

RxTSChn_6

AC17

AC18

TxOH_5

AD17

AD18

RxOHClk_6

TxSerClk_5

TxTSb3_5

TxOHSync_5

AC19

AC20

AC21

TxSync_5

RxOH_5

AD19

AD20

AD21

TxSer_5

TxOHClk_5

RxTSb4_5

RxTSb1_5

RxFrTD_5

AC22

RxSync_5

AD22

RxTSb0_5

RxSig_5

AA23

AA24

TxSync_4

TxOH_4

AC23

AC24

NC

AD23

AD24

RxCASMSync_5

AB24

TxTSB0_4

TxSig_4

TxTSb1_4

TxFrTD_4

RxMSync_5

RxCRCMSync_5

AA25

AA26

NC

AB25

AB26

TxTSClk_4

AC25

AC26

TxOHClk_4

AD25

AD26

RxTSClk_5

RxTSb4_4

TxSer_4

TxMSync_4

TxInClk_4

NC

19

áç

XRT84L38

OCTAL T1E1/J1 FRAMER

REV.1.0.0

PIN NAME

AE1

TxNEG_7

TxMX_7

AF1

LOS_7

AE2

AE3

AE4

RxLineClk_7

AF2

AF3

AF4

NC

TxOHClk_7

TxTSb4_7

TxTSb3_7

TxOHSync_7

AE5

AE6

TxTSb2_7

Tx12.352MHz_7

AF5

AF6

TxSer_7

TxSync_7

RxTSb4_7

TxMSync_7

TxInClk_7

AE7

AE8

RxSync_7

AF7

AF8

RxTSb3_7

Rx8kHz_7

RxTSb2_7

RxTSChn_7

AE9

RxTSb1_7

RxFrTD_7

AF9

RxTSb0_7

RxSig_7

AE10

TxSync_6

AF10

TxMSync_6

TxInClk_6

AE11

AE12

TxSer_6

AF11

AF12

NC

TxTSb2_6

Tx12.352MHz_6

TxTSb1_6

TxFrTD_6

AE13

TxTSClk_6

AF13

RxMSync_6

RxCRCMSync_6

AE14

AE15

AE16

NC

AF14

AF15

AF16

NC

RxTSClk_6

RxSer_6

RxTSb3_6

Rx8kHz_6

AE17

NC

AF17

RxTSb1_6

RxFrTD_6

AE18

AE19

TxTSb4_5

AF18

AF19

RxOH_6

TxTSb2_5

Tx12.352MHz_5

TxTSb1_5

TxFrTD_5

AE20

AE21

AE22

AE23

TxTSClk_5

AF20

AF21

AF22

AF23

TxTSb0_5

TxSig_5

RxOHClk_5

TxMSync_5

TxInClk_5

RxTSb3_5

Rx8kHz_5

NC

RxSer_5

RxTSb2_5

RxTSChn_5

AE24

AE25

AE26

TxTSb4_4

NC

AF24

AF25

AF26

NC

RxSerClk_5

TxTSb2_4

TxTSb3_4

Tx12.352MHz_4

TxOHSync_4

20

XRT84L38

OCTAL T1/E1/J1 FRAMER

áç

1.0.0

PIN DESCRIPTIONS

TRANSMIT SERIAL DATA INPUT

(Framer Channel Number indicated by _n)

SIGNAL NAME

PIN #

TYPE

DESCRIPTION

TxSer_0

TxSer_1

TxSer_2

TxSer_3

TxSer_4

TxSer_5

TxSer_6

TxSer_7

B6

A14

B22

I

Transmit Serial Data Input—Transmit Framer_n:

This input pin along with TxSerClk_n functions as the Transmit Serial input port

for Framer_n.

F25

DS1 Mode:

AB26

AD19

AE11

AF5

Any payload data applied to this pin would be inserted into a DS1 frame and

output onto the T1 line via the TxPOS_n and TxNEG_n output pins. If

Framer_n is configured accordingly, the framing alignment bits, the facility data

link bits and the CRC-6 bits can also be inserted to input pin.The signal applied

to this input pin can be latched to the Transmit Payload Data Input Interface on

either the rising edge or the falling edge of TxSerClk_n according to configura-

tions of Framer_n.

E1 Mode:

Any payload data applied to this pin would be inserted into an E1 frame and

output onto the E1 line via the TxPOS_n and TxNEG_n output pins. All data

intended to be transported via Time Slots 1 through 15 and Time slots 17

through 31, within each E1 frame, must be applied to this input pin. If Framer_n

is configured accordingly, data intended for Time Slots 0 and 16 can also be

applied to this input pin.

21

áç

XRT84L38

OCTAL T1/E1/J1 FRAMER

REV.1.0.0

TRANSMIT SERIAL DATA INPUT

(Framer Channel Number indicated by _n)

SIGNAL NAME

PIN #

TYPE

DESCRIPTION

TxSerClk_0

TxSerClk_1

TxSerClk_2

TxSerClk_3

TxSerClk_4

TxSerClk_5

TxSerClk_6

TxSerClk_7

D8

A16

D20

G23

Y23

AC18

AD9

AC6

I or O Transmit Serial Clock Signal --Transmit Framer_n:

This clock signal is used by the Transmit payload data Input Interface, to latch

the contents of the TxSer_n signal into the Octal T1/E1/J1 Framer IC. Data that

is applied at the TxSer_n input is latched into the Transmit payload data Input

Interface (for Framer_n) on either the rising edge or the falling edge of

TxSerClk_n depending on configurations of Framer_n. TxSerClk_n can either

be an input or an output.

DS1 Mode:

Transmit Back-plane Interface-1.544 MHz Clock Mode

If TxMUXEN = 0 and TxIMODE[1:0] = 00 in Transmit interface control register,

Transmit back-plane interface of Framer_n is taking data at a rate of 1.544

Mbit/s. If the Transmit Section of Framer_n has been configured to use the

TxSerClk_n signal as the timing source, then this signal will be an Input. If the

Transmit Section of Framer_n has been configured to use either the

RxLineClk_n signal or the OSCClk signal as the timing source, then

TxSerClk_n will be an Output.

Transmit Back-plane Interface-High Speed Clock Mode

If TxMUXEN ≠ 0 and TxIMODE[1:0] ≠ 00 in Transmit interface control register,

Transmit back-plane interface of Framer_n is operating at a high-speed mode

and is taking data at rates of 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, 12.352

Mbit/s or 16.384 Mbit/s. The TxSerClk_n signal will be an Input clock signal

running at 1.544 MHz.

E1 Mode:

Transmit Back-plane Interface-2.048 MHz Clock Mode

If TxMUXEN = 0 and TxIMODE[1:0] = 00 in Transmit interface control register,

Transmit back-plane interface of Framer_n is taking data at a rate of 2.048

Mbit/s. If the Transmit Section of Framer_n has been configured to use the

TxSerClk_n signal as the timing source, then this signal will be an Input. If the

Transmit Section of Framer_n has been configured to use either the

RxLineClk_n signal or the OSCClk signal as the timing source, then

TxSerClk_n will be an Output.

Transmit Back-plane Interface-High Speed Clock Mode

If TxMUXEN ≠ 0 or TxIMODE[1:0] ≠ 00 in Transmit interface control register,

Transmit back-plane interface of Framer_n is operating at a high-speed mode.

The TxSerClk_n signal will be an Input clock signal running at 2.048 MHz.

22

XRT84L38

OCTAL T1/E1/J1 FRAMER

áç

1.0.0

TRANSMIT SERIAL DATA INPUT

(Framer Channel Number indicated by _n)

SIGNAL NAME

PIN #

TYPE

DESCRIPTION

TxSync_0

TxSync_1

TxSync_2

TxSync_3

TxSync_4

TxSync_5

TxSync_6

TxSync_7

D6

A12

A21

I or O Single Frame Sync Pulse Input/Output—Transmit Framer_n:

This pin is configured to be an input if the TxSerClk_n input pin is configured

to be the timing reference for the Transmit Portion of Framer_n. This pin is con-

figured as an output if the RxLineClk_n input pin or the OSCClk input pins are

configured to be the timing reference for the Transmit portion of Framer_n.

DS1 Mode:

E25

AA23

AC19

AE10

AF6

When pin is configured to be an Input

If this pin is configured to be an input, then the user must pulse this pin "High"

for one period of TxSerClk_n, when the Transmit payload data Input Interface

(of Framer_n) is processing the first bit (F-bit) of an outbound DS1 frame.

NOTE: It is imperative that the TxSync_n input signal be synchronized with the

TxSerClk_n input signal.

When pin is configured to be an Output

If this pin is configured to be an output, then it will pulse "High", for one period

of TxSerClk_n, when the Transmit payload data Input Interface (of Framer_n)

is processing the last payload bit within an outbound DS1 frame.

E1 Mode:

When pin is configured to be an Input

If this pin is configured to be an input, then the user must pulse this pin "High"

for one period of TxSerClk_n, when the Transmit payload data Input Interface

(of Framer_n) is processing the International Bit (Si) of an outbound E1 frame.

NOTE: It is imperative that the TxSync_n input signal be synchronized with the

TxSerClk_n input signal.

When pin is configured to be an Output

If this pin is configured to be an output, then it will pulse "High", for one period

of TxSerClk_n, when the Transmit payload data Input Interface (of Framer_n)

is processing the last bit within a given outbound E1 frame.

23

áç

XRT84L38

OCTAL T1/E1/J1 FRAMER

REV.1.0.0

TRANSMIT SERIAL DATA INPUT

(Framer Channel Number indicated by _n)

SIGNAL NAME

PIN #

TYPE

DESCRIPTION

TxMSync_0

TxMSync_1

TxMSync_2

TxMSync_3

TxMSync_4

TxMSync_5

TxMSync_6

TxMSync_7

C6

B13

A22

I or O Multiframe Sync Pulse Input/Output—Framer_n:

This signal indicates the boundary of an outbound multi-frame.

DS1 Mode:

F26

Transmit Back-plane Interface-1.544 MHz Clock Mode

If TxMUXEN = 0 and TxIMODE[1:0] = 00 in Transmit interface control register,

Transmit back-plane interface of Framer_n is taking data at a rate of 1.544

Mbit/s. This pin is configured to be an Input if the TxSerClk_n input pin is con-

figured to be the timing reference for the Transmit section of Framer_n. Con-

versely, this pin will be configured as an Output if the RxLineClk input pin or

the OSCClk input pins are configured to be the timing reference for the Trans-

mit section of Framer_n.The roles of these pins when configured as input or

output, is described below.

AC26

AF21

AF10

AE6

When pin is configured to be an Input

If this pin is configured to be an input, this pin must be pulsed "High" for one

period of TxSerClk_n, the instant that the Transmit payload data Interface (of

Framer_n) is processing the first bit of a DS1 Multi-frame.

NOTE: It is imperative that the TxMSync_n input signal be synchronized with

the TxSerClk_n input signal.

When pin is configured to be an Output

If this pin is configured to be an output, then it will pulse "High", for one period

of TxSerClk_n, when the Transmit payload data Input Interface (of Framer_n)

is processing the last bit of a DS1 Multi-frame.

E1 Mode:

Transmit Back-plane Interface-2.048 MHz Clock Mode

If TxMUXEN = 0 and TxIMODE[1:0] = 00 in Transmit interface control register,

Transmit back-plane interface of Framer_n is taking data at a rate of 2.048

Mbit/s. This pin is configured to be an Input if the TxSerClk_n input pin is con-

figured to be the timing reference for the Transmit section of Framer_n. Con-

versely, this pin will be configured as an Output if the RxLineClk input pin or

the OSCClk input pins are configured to be the timing reference for the Trans-

mit section of Framer_n.

When pin is configured to be an Input

If this pin is configured to be an input, this pin must be pulsed "High" for one

period of TxSerClk_n, the instant that the Transmit payload data Interface (of

Framer_n) is processing the first International Bit (Si) of an "outbound" CRC

payload data Multiframe.

NOTES:

1. This pin is ignored if CRC Multiframe Alignment has been disabled.

2. It is imperative that the TxMSync_n input signal be synchronized with

the TxSerClk_n input signal.

When pin is configured to be an Output

If this pin is configured to be an output, then it will pulse "High", for one period

of TxSerClk_n, when the Transmit payload data Input Interface (of Framer_n)

is processing the last bit, within an "outbound" CRC Multi-frame.

NOTES:

1. This pin is inactive if CRC Multi-frame Alignment has been disabled.

2. The purpose of this output pin is to permit the Terminal Equipment to

maintain alignment with the "outbound" CRC-Multi-frame structure.

24

XRT84L38

OCTAL T1/E1/J1 FRAMER

áç

1.0.0

TRANSMIT SERIAL DATA INPUT

(Framer Channel Number indicated by _n)

SIGNAL NAME

PIN #

TYPE

DESCRIPTION

TxInClk_0

TxInClk_1

TxInClk_2

TxInClk_3

TxInClk_4

TxInClk_5

TxInClk_6

TxInClk_7

C6

B13

A22

I

Transmit Input Clock Signal -- Transmit Framer _n

If TxMUXEN ≠ 0 or TxIMODE[1:0] ≠ 00 in Transmit interface control register,

Transmit back-plane interface of Framer_n is operating at a high-speed mode.

This pin will function as an input clock signal for the high-speed Transmit back-

plane interface.

F26

AC26

AF21

AF10

AE6

DS1 Mode:

Transmit Back-plane Interface-MVIP, 2.048 MHz Clock Mode

If TxMUXEN = 0 and TxIMODE[1:0] = 01 in Transmit interface control register,

Transmit back-plane interface of Framer_n is taking data at a rate of 2.048

Mbit/s. The TxInClk_n signal will be an Input clock signal running at 2.048

MHz.

Transmit Back-plane Interface-4.096 MHz Clock Mode

If TxMUXEN = 0 and TxIMODE[1:0] = 10 in Transmit interface control register,

Transmit back-plane interface of Framer_n is taking data at a rate of 4.096

Mbit/s. The TxInClk_n signal will be an Input clock signal running at 4.096

MHz.

Transmit Back-plane Interface-8.192 MHz Clock Mode

If TxMUXEN = 0 and TxIMODE[1:0] = 11 in Transmit interface control register,

Transmit back-plane interface of Framer_n is taking data at a rate of 8.192

Mbit/s. The TxInClk_n signal will be an Input clock signal running at 8.192

MHz.

Transmit Back-plane Interface-Multiplexed at 12.352 MHz Clock Mode

If TxMUXEN = 1 and TxIMODE[1:0] = 00 in Transmit interface control register,

Transmit back-plane interface of Framer_n is taking multiplexed data at a rate

of 12.352 Mbit/s. TxInClk_0 and TxInClk_4 signals will be Input clock signals

running at 12.352 MHz. TxInClk_1, 2, 3 and TxInClk_5, 6, 7 signals are not

required. Transmit Payload data of Channel 0, 1, 2 and 3 are multiplexed and

latched into Transmit back-plane interface using clock edge of TxInClk_0 via

TxSer_0 input pin. Transmit Payload data of Channel 4, 5, 6 and 7 are multi-

plexed and latched into Transmit back-plane interface using clock edge of

TxInClk_4 via TxSer_4 input pin. Inside the Octal Framer, data will be de-multi-

plexed into 8 channels from the serial inputs of Channel 0 and 4.

Transmit Back-plane Interface-Multiplexed at 16.384 MHz Clock Mode

If TxMUXEN = 1 and TxIMODE[1:0] = 01 in Transmit interface control register,

Transmit back-plane interface of Framer_n is taking multiplexed data at a rate

of 16.384 Mbit/s. TxInClk_0 and TxInClk_4 signals will be Input clock signals

running at 16.384 MHz. TxInClk_1, 2, 3 and TxInClk_5, 6, 7 signals are not

required. Transmit Payload data of Channel 0, 1, 2 and 3 are multiplexed and

latched into Transmit back-plane interface using clock edge of TxInClk_0 via

TxSer_0 input pin. Transmit Payload data of Channel 4, 5, 6 and 7 are multi-

plexed and latched into Transmit back-plane interface using clock edge of

TxInClk_4 via TxSer_4 input pin. Inside the Octal Framer, data will be de-multi-

plexed into 8 channels from the serial inputs of Channel 0 and 4.

Transmit Back-plane Interface-HMVIP, 16.384 MHz Clock Mode

If TxMUXEN = 1 and TxIMODE[1:0] = 10 in Transmit interface control register,