74AC253_00 [FAIRCHILD]
Dual 4-Input Multiplexer with 3-STATE Outputs; 双路4输入多路复用器与3态输出
| 型号： | 74AC253_00 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual 4-Input Multiplexer with 3-STATE Outputs |
| 文件： | 总9页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised October 2000
74AC253 • 74ACT253
Dual 4-Input Multiplexer with 3-STATE Outputs
General Description
Features
The AC/ACT253 is a dual 4-input multiplexer with 3-STATE
outputs. It can select two bits of data from four sources
using common select inputs. The outputs may be individu-
ally switched to a high impedance state with a HIGH on the
respective Output Enable (OE) inputs, allowing the outputs
to interface directly with bus oriented systems.
■ ICC and IOZ reduced by 50%
■ Multifunction capability
■ Non inverting 3-STATE outputs
■ Outputs source/sink 24 mA
■ ACT253 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC253SC
74AC253SJ
M16A
M16D
N16E
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC253PC
74ACT253SC
74ACT253SJ
74ACT253MTC
74ACT253PC
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Diagrams
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
Side A Data Inputs
I
0a–I3a
I0b–I3b
Side B Data Inputs
S0, S1
OEa
Common Select Inputs
Side A Output Enable Input
Side B Output Enable Input
3-STATE Outputs
OEb
Za, Zb
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS009946
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Functional Description
Truth Table
The AC/ACT253 contains two identical 4-input multiplexers
with 3-STATE outputs. They select two bits from four
sources selected by common Select inputs (S0, S1). The
Select
Inputs
Output
Enable
Data Inputs
Outputs
Z
4-input multiplexers have individual Output Enable (OEa,
OEb) inputs which, when HIGH, force the outputs to a high
S0
S1
I0
I1
I2
I3
OE
impedance (High Z) state. This device is the logic imple-
mentation of a 2-pole, 4-position switch, where the position
of the switch is determined by the logic levels supplied to
the two select inputs. The logic equations for the outputs
are shown:
X
L
X
L
X
L
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
Z
L
L
L
H
X
X
X
X
X
X
H
L
H
H
L
L
Z
a = OEa
•
(I0a • S1 • S0 + I1a • S1 • S0
I2a • S1 • S0 + I3a • S1 • S0)
(I0b • S1 • S0 + I1b • S1 • S0
I2b • S1 • S0 + I3b • S1 • S0)
+
L
H
X
X
X
X
H
L
H
H
H
H
Z
b = OEb
•
+
L
H
X
X
H
L
If the outputs of 3-STATE devices are tied together, all but
one device must be in the high impedance state to avoid
high currents that would exceed the maximum ratings.
Designers should ensure that Output Enable signals to 3-
STATE devices whose outputs are tied together are
designed so that there is no overlap.
H
H
H
H
Address Inputs S0 and S1 are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
± 50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
± 50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.1
3.15
3.85
0.9
2.1
3.15
3.85
0.9
V
OUT = 0.1V
2.25
2.75
1.5
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
V
OUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
VIN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
OH = −12 mA
V
V
OH = −24 mA
OH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
I
OUT = 50 µA
0.1
0.1
VIN = VIL or VIH
3.0
4.5
5.5
5.5
0.36
0.36
0.36
± 0.1
0.44
0.44
0.44
± 1.0
I
I
I
OL = 12 mA
V
OL = 24 mA
OL = 24 mA (Note 2)
IIN (Note 4)
IOZ
Maximum Input Leakage Current
Maximum 3-STATE
Current
µA
µA
VI = VCC, GND
VI (OE) = VIL, VIH
VI = VCC, GND
5.5
±0.25
±2.5
V
V
V
V
O = VCC, GND
IOLD
IOHD
Minimum Dynamic
5.5
5.5
5.5
75
mA
mA
µA
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC or GND
Output Current (Note 3)
−75
40.0
ICC (Note 4) Maximum Quiescent Supply Current
4.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
3
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DC Electrical Characteristics for ACT
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
Guaranteed Limits
Minimum HIGH Level
Input Voltage
1.5
1.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
V
V
V
VIL
Maximum LOW Level
Input Voltage
1.5
V
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = −24 mA
OH = −24 mA (Note 5)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
OL = 24 mA
OL = 24 mA (Note 5)
IIN
Maximum Input
Leakage Current
Maximum 3-STATE
Current
5.5
5.5
5.5
±0.1
±1.0
±2.5
1.5
µA
µA
mA
VI = VCC, GND
VI = VIL, VIH
IOZ
±0.25
VO = VCC, GND
ICCT
Maximum
0.6
VI = VCC − 2.1V
ICC/Input
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 6)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC
−75
5.5
4.0
40.0
µA
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 7)
3.3
Units
Min
2.0
2.0
2.5
2.0
1.5
1.5
2.0
1.5
1.5
1.5
1.5
1.5
2.0
2.0
1.5
1.5
Typ
8.5
6.5
9.5
7.0
7.0
5.5
7.5
5.5
4.5
3.5
5.0
3.5
5.5
5.0
5.0
4.0
Max
15.5
11.0
16.0
11.5
14.5
10.0
13.0
9.5
Min
tPLH
Propagation Delay
2.0
1.5
2.0
1.5
1.5
1.5
1.5
1.5
1.0
1.0
1.0
1.0
1.5
1.5
1.0
1.0
17.5
12.5
18.0
13.0
17.0
11.5
15.0
11.0
8.5
ns
ns
ns
ns
ns
ns
ns
ns
Sn to Zn
5.0
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
Sn to Zn
3.3
5.0
Propagation Delay
In to Zn
3.3
5.0
Propagation Delay
In to Zn
3.3
5.0
Output Enable Time
3.3
8.0
5.0
6.0
6.5
Output Enable Time
Output Disable Time
Output Disable Time
3.3
8.0
9.0
5.0
6.0
7.0
3.3
9.5
10.0
8.5
5.0
8.0
3.3
8.0
9.0
5.0
7.0
7.5
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
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4
AC Electrical Characteristics for ACT
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 8)
Min
Typ
Max
Min
tPLH
Propagation Delay
5.0
5.0
5.0
5.0
2.0
7.0
7.5
5.5
6.5
11.5
2.0
2.5
2.0
3.0
13.0
14.5
11.0
12.5
ns
ns
ns
ns
Sn to Zn
tPHL
tPLH
tPHL
Propagation Delay
3.0
2.5
3.5
13.0
10.0
11.0
Sn to Zn
Propagation Delay
In to Zn
Propagation Delay
In to Zn
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
2.0
2.0
3.0
2.5
4.5
5.0
6.0
4.5
7.5
8.0
9.5
7.5
1.5
1.5
2.5
2.0
8.5
9.0
ns
ns
ns
ns
10.0
8.5
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
pF
V
CC = OPEN
CPD
Power Dissipation Capacitance
50.0
VCC = 5.0V
5
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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