74ACT299LCTR [FAIRCHILD]
Parallel In Parallel Out, ACT Series, 8-Bit, Bidirectional, True Output, CMOS, CQCC20, CERAMIC, LCC-20;
| 型号： | 74ACT299LCTR |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Parallel In Parallel Out, ACT Series, 8-Bit, Bidirectional, True Output, CMOS, CQCC20, CERAMIC, LCC-20 存储 |
| 文件： | 总11页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1988
Revised March 2005
74AC299 • 74ACT299
8-Input Universal Shift/Storage Register
with Common Parallel I/O Pins
General Description
Features
■ ICC and IOZ reduced by 50%
The AC/ACT299 is an 8-bit universal shift/storage register
with 3-STATE outputs. Four modes of operation are possi-
ble: hold (store), shift left, shift right and load data. The par-
allel load inputs and flip-flop outputs are multiplexed to
reduce the total number of package pins. Additional out-
puts are provided for flip-flops Q0, Q7 to allow easy serial
■ Common parallel I/O for reduced pin count
■ Additional serial inputs and outputs for expansion
■ Four operating modes: shift left, shift right, load
and store
■ 3-STATE outputs for bus-oriented applications
■ Outputs source/sink 24 mA
cascading. A separate active LOW Master Reset is used to
reset the register.
■ ACT299 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC299SC
M20B
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC299SCX_NL
(Note 1)
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
74AC299SJ
M20D
MTC20
N20A
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74AC299MTC
74AC299PC
74ACT299SC
74ACT299MTC
74ACT299PC
M20B
MTC20
N20A
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names
Description
CP
Clock Pulse Input
DS0
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
DS7
S0, S1
MR
Asynchronous Master Reset
3-STATE Output Enable Inputs
Parallel Data Inputs or
OE1, OE2
I/O0–I/O7
3-STATE Parallel Outputs
Serial Outputs
Q0, Q7
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009893
www.fairchildsemi.com
Logic Symbols
Truth Table
Inputs
Response
MR S1 S0 CP
L
H
H
H
H
X
H
L
X
H
H
L
X
Asynchronous Reset; Q0–Q7 LOW
Parallel Load; I/On
Shift Right; DS0
Qn
Q0, Q0
Q1, etc.
Q6, etc.
H
L
Shift Left, DS7
Hold
Q7, Q7
L
X
IEEE/IEC
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
LOW-to-HIGH Transition
Functional Description
The AC/ACT299 contains eight edge-triggered D-type flip-
flops and the interstage logic necessary to perform syn-
chronous shift left, shift right, parallel load and hold opera-
tions. The type of operation is determined by S0 and S1, as
shown in the Truth Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q0 and Q7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi-
ated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the rec-
ommended setup and hold times, relative to the rising edge
of CP, are observed.
A HIGH signal on either OE1 or OE2 disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, hold, load and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S0 and S1 in preparation for a paral-
lel load operation.
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2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Diode Current (IIK
VI 0.5V
)
0.5V to 7.0V
)
Supply Voltage (VCC
)
20 mA
20 mA
(Unless Otherwise Specified)
AC
VI VCC 0.5V
2.0V to 6.0V
4.5V to 5.0V
0V to VCC
DC Input Voltage (VI)
0.5V to VCC 0.5V
ACT
DC Output Diode Current (IOK
VO 0.5V
)
Input Voltage (VI)
20 mA
20 mA
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate ( V/ t)
AC Devices
0V to VCC
VO VCC 0.5V
40 C to 85 C
DC Output Voltage (VO)
0.5V to VCC 0.5V
50 mA
DC Output Source or Sink Current (IO)
DC VCC or Ground Current
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate ( V/ t)
ACT Devices
Per Output Pin (ICC or IGND
)
50 mA
125 mV/ns
Storage Temperature (TSTG
Junction Temperature (TJ)
(PDIP)
)
65 C to 150 C
140 C
VIN from 0.8V to 2.0V
V
CC @ 4.5V, 5.5V
125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. Obviously the databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild
does not recommend operation of FACT circuits outside databook specifi-
cations.
DC Electrical Characteristics for AC
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
Guaranteed Limits
V
V
V
Minimum HIGH Level
Input Voltage
1.5
2.1
2.1
3.15
3.85
0.9
V
0.1V
IH
OUT
2.25
2.75
1.5
3.15
3.85
0.9
V
or V
0.1V
CC
Maximum LOW Level
Input Voltage
V
0.1V
0.1V
IL
OUT
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
V
or V
CC
Minimum HIGH Level
Output Voltage
OH
4.4
4.4
I
50 A
OUT
5.4
5.4
V
V or V
IL IH
IN
OH
OH
OH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
12 mA
24 mA
24 mA (Note 3)
V
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
OL
0.1
0.1
V
I
50
A
OUT
0.1
0.1
V
V
or V
IH
IN
OH
OH
OH
IL
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
I
I
I
12 mA
24 mA
V
A
24 mA (Note 3)
V , GND
CC
I
Maximum Input
V
IN
I
5.5
5.5
0.1
1.0
(Note 5)
Leakage Current
I
Minimum Dynamic
Output Current (Note 4)
86
75
mA
mA
V
V
V
1.65V Max
3.85V Min
OLD
OLD
I
OHD
OHD
IN
I
(Note 5) Maximum Quiescent
Supply Current
V
or GND
CC
CC
5.5
4.0
40.0
A
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4
DC Electrical Characteristics for AC (Continued)
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
V (OE) , V
(V)
Typ
Guaranteed Limits
I
Maximum I/O Leakage Current
5.5
0.3
3.0
A
V
IL
OZT
I
IH
V
V
V
, GND
I
CC
V
, GND
O
CC
Note 3: All outputs loaded; threshold on input associated with output under test.
Note 4: Maximum test duration 20 ms, one output loaded at a time.
Note 5: I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
IN
CC
DC Electrical Characteristics for ACT
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
3.0
4.5
4.5
5.5
Typ
Guaranteed Limits
V
V
V
Minimum HIGH Level
Input Voltage
1.5
1.5
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
0.1V
IH
OUT
V
V
V
2.0
0.8
0.8
4.4
5.4
or V
0.1V
0.1V
0.1V
CC
Maximum LOW Level
Input Voltage
1.5
V
IL
OUT
1.5
or V
CC
Minimum HIGH Level
4.49
5.49
OH
I
50
A
OUT
V
V
IL
or V
IN
OH
OH
IH
4.5
5.5
4.5
5.5
0.0001
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
24 mA
24 mA (Note 6)
V
Maximum LOW Level
Output Voltage
0.001
0.001
OL
I
50
A
OUT
0.1
0.1
V
V
or V
IH
IN
OL
OL
IL
4.5
5.5
5.5
5.5
5.5
5.5
5.5
0.36
0.36
0.1
0.44
0.44
1.0
I
I
24 mA
24 mA (Note 6)
I
I
I
I
I
I
Maximum Input Leakage Current
A
mA
mA
mA
A
V
V
V
V
V
V
V
, GND
2.1V
IN
I
CC
CC
Maximum I /Input
CC
0.6
1.5
CCT
OLD
OHD
CC
I
Minimum Dynamic
75
1.65V Max
3.85V Min
OLD
OHD
IN
Output Current (Note 7)
Maximum Quiescent Supply Current
Maximum I/O
75
4.0
0.3
40.0
V
or GND
CC
V (OE)
V , V
IL IH
OZT
I
Leakage Current
5.5
3.0
A
V
V
V
, GND
I
CC
V
, GND
O
CC
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
5
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AC Electrical Characteristics for AC
V
T
25 C
T
40 C to 85 C
50 pF
Min Max
CC
A
A
C
50 pF
C
L
Symbol
Parameter
(V)
(Note 8)
3.3
Units
L
Min
90
Typ
Max
f
t
t
t
t
t
t
t
t
t
t
Maximum Input
124
173
14.0
9.5
80
105
7.0
4.5
7.0
5.0
7.5
5.0
8.5
6.0
7.5
5.0
7.5
5.0
6.0
4.0
6.0
4.0
5.5
3.0
4.5
2.0
MAX
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Frequency
5.0
130
8.5
5.5
8.5
5.5
9.0
6.0
10.0
6.5
9.0
5.5
9.0
5.5
7.0
4.5
7.0
5.0
6.5
3.5
5.5
3.5
Propagation Delay
3.3
20.5
14.0
21.5
14.5
20.5
14.5
23.0
16.0
22.5
15.5
21.5
15.0
18.0
12.5
18.0
12.5
18.5
14.0
17.0
12.5
22.0
15.0
23.0
16.0
22.5
16.0
24.5
17.5
25.0
17.0
24.0
16.5
19.5
13.5
20.5
14.0
19.5
15.0
19.0
13.5
PLH
PHL
PLH
PHL
PHL
PHL
PZH
PZL
PHZ
PLZ
CP to Q or Q (Shift Left or Right)
5.0
0
7
Propagation Delay
CP to Q or Q (Shift Left or Right)
3.3
14.5
10.0
14.5
10.0
16.0
11.0
15.5
10.5
15.0
10.0
12.0
8.5
5.0
0
7
Propagation Delay
CP to I/O
3.3
5.0
n
Propagation Delay
CP to I/O
3.3
5.0
n
Propagation Delay
MR to Q or Q
3.3
5.0
0
7
Propagation Delay
MR to I/O
3.3
5.0
n
Output Enable Time
OE to I/O
3.3
5.0
n
Output Enable Time
OE to I/O
3.3
12.5
8.0
5.0
n
Output Disable Time
OE to I/O
3.3
13.0
9.5
5.0
n
Output Disable Time
OE to I/O
3.3
11.5
8.0
5.0
n
Note 8: Voltage Range 3.3 is 3.3V 0.3V.
Voltage Range 5.0 is 5.0V 0.5V.
AC Operating Requirements for AC
V
T
25 C
T
40 C to 85 C
50 pF
Guaranteed Minimum
CC
A
A
C
50 pF
C
L
Symbol
Parameter
(V)
(Note 9)
3.3
Units
L
Typ
3.0
2.0
3.0
1.5
2.0
1.0
2.0
1.0
2.5
1.5
2.0
1.0
3.5
2.0
t
Setup Time, HIGH or LOW
8.0
8.5
5.5
0.5
1.0
6.0
4.0
0
S
ns
ns
ns
ns
ns
ns
ns
S
or S to CP
5.0
5.0
0.5
1.0
5.5
3.5
0
0
1
t
Hold Time, HIGH or LOW
or S to CP
3.3
H
S
5.0
0
1
t
Setup Time, HIGH or LOW
3.3
S
I/O to CP
n
5.0
t
Hold Time, HIGH or LOW
3.3
H
I/O to CP
n
5.0
1.0
6.5
4.0
0
1.0
7.0
4.5
0.5
1.0
5.0
3.5
t
Setup Time, HIGH or LOW
3.3
S
DS or DS to CP
5.0
0
7
t
Hold Time, HIGH or LOW
DS or DS to CP
3.3
H
5.0
1.0
4.5
3.5
0
7
t
CP Pulse Width, LOW
3.3
W
5.0
t
MR Pulse Width, LOW
3.3
5.0
3.3
5.0
4.0
2.0
0
4.5
3.5
1.5
1.5
5.0
3.5
1.5
1.5
W
ns
ns
t
Recovery Time
MR to CP
REC
0.5
Note 9: Voltage Range 3.3 is 3.3V 0.3V
Voltage Range 5.0 is 5.0V 0.5V
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6
AC Electrical Characteristics for ACT
V
T
25 C
T
40 C to 85 C
50 pF
Min Max
CC
A
A
C
50 pF
C
L
Symbol
Parameter
(V)
(Note 10)
5.0
Units
L
Min
120
4.0
Typ
Max
12.5
13.5
12.5
15.0
15.0
14.5
12.0
12.0
12.5
11.5
f
t
Maximum Input Frequency
Propagation Delay
170
8.5
110
3.0
MHz
ns
MAX
5.0
14.0
15.0
13.5
16.5
18.0
17.5
13.0
13.5
13.5
12.5
PLH
PHL
PLH
PHL
PHL
PHL
PZH
PZL
PHZ
PLZ
CP to Q or Q (Shift Left or Right)
0
7
t
t
t
t
t
t
t
t
t
Propagation Delay
CP to Q or Q (Shift Left or Right)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
4.0
4.5
5.0
4.0
4.0
2.5
2.0
2.0
2.5
9.0
8.5
3.5
4.5
4.5
4.0
3.5
1.5
1.5
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
7
Propagation Delay
CP to I/O
n
Propagation Delay
CP to I/O
9.5
n
Propagation Delay
MR to Q or Q
14.0
13.0
8.0
0
7
Propagation Delay
MR to I/O
n
Output Enable Time
OE to I/O
n
Output Enable Time
OE to I/O
8.0
n
Output Disable Time
OE to I/O
8.5
n
Output Disable Time
OE to I/O
8.0
n
Note 10: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements for ACT
V
T
25 C
50 pF
T
A
40 C to 85 C
C 50 pF
L
CC
A
C
Symbol
Parameter
(V)
(Note 11)
5.0
Units
ns
L
Typ
Guaranteed Minimum
t
Setup Time, HIGH or LOW
2.0
5.0
1.0
4.0
1.0
4.5
1.0
4.0
5.5
S
H
S
H
S
H
W
S
or S to CP
1
0
t
t
t
t
t
t
Hold Time, HIGH or LOW
or S to CP
5.0
5.0
5.0
5.0
5.0
5.0
2.0
1.5
1.0
1.5
1.0
2.0
1.0
4.5
1.0
5.0
1.0
4.5
ns
S
0
1
Setup Time, HIGH or LOW
ns
I/O to CP
n
Hold Time, HIGH or LOW
ns
I/O to CP
n
Setup Time, HIGH or LOW
ns
DS or DS to CP
0
7
Hold Time, HIGH or LOW
DS or DS to CP
ns
0
7
CP Pulse Width
HIGH or LOW
ns
t
t
MR Pulse Width, LOW
5.0
5.0
2.0
0
3.5
1.5
3.5
1.5
ns
ns
W
Recovery Time, MR to CP
REC
Note 11: Voltage Range 5.0 is 5.0V 0.5V.
Capacitance
Symbol
Parameter
Typ
4.5
Units
pF
Conditions
C
C
Input Capacitance
V
V
5.0V
5.5V
IN
CC
CC
Power Dissipation Capacitance
170
pF
PD
7
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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11
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FAIRCHILD
74ACT299MTCX_NL
Parallel In Parallel Out, ACT Series, 8-Bit, Bidirectional, True Output, CMOS, PDSO20, 4.40 MM, LEAD FREE, MO-153AC, TSSOP-20
FAIRCHILD
74ACT299MTR
ACT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, SO-20
STMICROELECTR
74ACT299PCQR
Parallel In Parallel Out, ACT Series, 8-Bit, Bidirectional, True Output, CMOS, PDIP20, PLASTIC, DIP-20
FAIRCHILD
74ACT299PCQR
ACT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP20, PLASTIC, DIP-20
TI
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