74ACT374SC [FAIRCHILD]
Octal D-Type Flip-Flop with 3-STATE Outputs; 八路D型IP- FL佛罗里达州运与三态输出
| 型号： | 74ACT374SC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal D-Type Flip-Flop with 3-STATE Outputs |
| 文件： | 总10页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised March 2005
74AC374 • 74ACT374
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
Features
The AC/ACT374 is a high-speed, low-power octal D-type
flip-flop featuring separate D-type inputs for each flip-flop
and 3-STATE outputs for bus-oriented applications. A buff-
ered Clock (CP) and Output Enable (OE) are common to
all flip-flops.
■ ICC and IOZ reduced by 50%
■ Buffered positive edge-triggered clock
■ 3-STATE outputs for bus-oriented applications
■ Outputs source/sink 24 mA
■ See 273 for reset version
■ See 377 for clock enable version
■ See 373 for transparent latch version
■ See 574 for broadside pinout version
■ See 564 for broadside pinout version with inverted
outputs
■ ACT374 has TTL-compatible inputs
Ordering Code:
Package
Order Number
Package Description
Number
74AC374SC
M20B
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC374SCX_NL
(Note 1)
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC374SJ
M20D
MTC20
N20A
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC374MTC
74AC374PC
74ACT374SC
74ACT374SJ
74ACT374MSA
74ACT374MTC
M20B
M20D
MSA20
MTC20
MTC20
74ACT374MTCX_NL
(Note 1)
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT374PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009959
www.fairchildsemi.com
Connection Diagram
Pin Descriptions
Pin Names
Description
D0–D7
CP
Data Inputs
Clock Pulse Input
OE
3-STATE Output Enable Input
3-STATE Outputs
O0–O7
Truth Table
Inputs
Outputs
Logic Symbols
Dn
H
L
CP
OE
L
On
H
L
L
X
X
H
Z
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
LOW-to-HIGH Transition
IEEE/IEC
Functional Description
The AC/ACT374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the state
of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) transi-
tion. With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Diode Current (IIK
VI 0.5V
)
0.5V to 7.0V
)
Supply Voltage (VCC
)
20 mA
20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI VCC 0.5V
ACT
DC Input Voltage (VI)
0.5V to VCC 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
VO 0.5V
)
0V to VCC
20 mA
20 mA
Operating Temperature (TA)
Minimum Input Edge Rate ( V/ t)
AC Devices
40 C to 85 C
VO VCC 0.5V
DC Output Voltage (VO)
DC Output Source
0.5V to VCC 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate ( V/ t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
(PDIP)
)
65 C to 150 C
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140 C
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
V
V
V
Minimum HIGH Level
Input Voltage
2.1
2.1
3.15
3.85
0.9
V
0.1V
IH
OUT
2.25
2.75
1.5
3.15
3.85
0.9
V
or V
0.1V
CC
Maximum LOW Level
Input Voltage
V
0.1V
0.1V
IL
OUT
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or V
CC
Minimum HIGH Level
Output Voltage
OH
4.4
4.4
I
50 A
OUT
5.4
5.4
V
V or V
IL IH
IN
OH
OH
OH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
12 mA
V
V
24 mA
24 mA (Note 3)
V
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
OL
0.1
0.1
I
50
A
OUT
0.1
0.1
V
V
or V
IH
IN
OL
OL
OL
IL
3.0
4.5
5.5
5.5
0.36
0.36
0.36
0.1
0.44
0.44
0.44
1.0
I
I
I
12 mA
24 mA
V
A
A
24 mA (Note 3)
V , GND
CC
I
I
(Note 5) Maximum Input Leakage Current
V
IN
I
Maximum 3-STATE Current
V (OE)
V , V
IL IH
OZ
I
5.5
0.25
2.5
V
V
V
V
V
V
, GND
I
CC
V
, GND
O
CC
I
I
I
Minimum Dynamic
5.5
5.5
5.5
75
75
mA
mA
A
1.65V Max
3.85V Min
OLD
OHD
OLD
Output Current (Note 4)
OHD
IN
(Note 5) Maximum Quiescent Supply Current
4.0
40.0
V
or GND
CC
CC
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
3
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DC Electrical Characteristics for ACT
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
V
V
V
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
0.1V
IH
OUT
V
V
V
1.5
2.0
0.8
0.8
4.4
5.4
or V
0.1V
0.1V
0.1V
50
CC
Maximum LOW Level
Input Voltage
1.5
V
IL
OUT
1.5
or V
CC
Minimum HIGH Level
Output Voltage
4.49
5.49
I
A
OH
OUT
V
V or V
IL IH
IN
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
I
I
I
24 mA
24 mA (Note 6)
OH
OH
OUT
V
Maximum LOW Level
Output Voltage
0.001
0.001
50
A
OL
0.1
0.1
V
V
or V
IH
IN
OL
OL
IL
4.5
5.5
5.5
0.36
0.36
0.1
0.44
0.44
1.0
V
A
I
I
24 mA
24 mA (Note 6)
I
I
I
Maximum Input
Leakage Current
Maximum
V
V
, GND
IN
I
CC
5.5
5.5
0.25
2.5
1.5
A
V
V
V
V
, V
OZ
I
IL
IH
3-STATE Current
Maximum
V
, GND
O
I
CC
0.6
mA
V
2.1V
CCT
CC
I
/Input
CC
I
I
I
Minimum Dynamic
Output Current (Note 7)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
75
75
mA
mA
A
V
V
V
1.65V Max
3.85V Min
OLD
OHD
CC
OLD
OHD
IN
4.0
40.0
V
CC
or GND
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics
V
T
25 C
T
40 C to 85
CC 50 pF
Max
CC
A
A
C
50 pF
Symbol
Parameter
(V)
(Note 8)
3.3
Units
L
L
Min
Typ
Max
Min
60
f
Maximum Clock
60
100
3.0
2.5
2.5
2.0
3.0
2.0
2.5
2.0
3.0
2.0
2.0
1.5
110
155
11.0
8.0
MAX
MHz
ns
Frequency
5.0
100
1.5
1.5
2.0
1.5
1.5
1.0
1.5
1.0
2.0
2.0
1.0
1.0
t
Propagation Delay
3.3
13.5
9.5
15.5
10.5
14.0
10.0
13.0
9.5
PLH
CP to O
5.0
n
t
Propagation Delay
CP to O
3.3
10.0
7.0
12.5
9.0
PHL
ns
5.0
n
t
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
3.3
9.5
11.5
8.5
PZH
ns
5.0
7.0
t
3.3
9.0
11.5
8.5
13.0
9.5
PZL
ns
5.0
6.5
t
3.3
10.5
8.0
12.5
11.0
11.5
8.5
14.5
12.5
12.5
10.0
PHZ
ns
5.0
t
3.3
8.0
PLZ
ns
5.0
6.5
Note 8: Voltage Range 3.3 is 3.3V 0.3V
Voltage Range 5.0 is 5.0V 0.5V
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4
AC Operating Requirements
V
T
25 C
T
40 C to 85 C
50 pF
Guaranteed Minimum
CC
A
A
C
50 pF
C
L
Symbol
Parameter
(V)
(Note 9)
3.3
Units
L
Typ
t
t
t
Setup Time, HIGH or LOW
2.0
1.0
1.0
0
5.5
6.0
4.5
1.0
1.5
6.0
4.5
S
ns
ns
ns
D
to CP
5.0
4.0
1.0
1.5
5.5
4.0
n
Hold Time, HIGH or LOW
to CP
3.3
H
W
D
5.0
n
CP Pulse Width,
HIGH or LOW
3.3
4.0
2.5
5.0
Note 9: Voltage Range 3.3 is 3.3V 0.3V
Voltage Range 5.0 is 5.0V 0.5V
AC Electrical Characteristics
V
T
25 C
T
A
40 C to 85 C
CC
A
C
50 pF
C
50 pF
Max
Symbol
Parameter
(V)
Units
L
L
(Note 10)
Min
Typ
Max
Min
f
Maximum Clock
5.0
100
160
90
2.0
1.5
MHz
ns
MAX
Frequency
t
t
Propagation Delay
5.0
5.0
2.0
2.0
8.5
8.0
10.0
9.5
11.5
11.0
PLH
PHL
CP to O
n
Propagation Delay
CP to O
ns
n
t
t
t
t
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
2.0
1.5
1.5
1.5
8.0
8.0
8.5
7.0
9.5
9.0
1.5
1.5
1.0
1.0
10.5
10.5
12.5
10.0
ns
ns
ns
ns
PZH
PZL
PHZ
PLZ
11.5
8.5
Note 10: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
V
T
25 C
T
40 C to 85 C
50 pF
Guaranteed Minimum
CC
A
A
C
50 pF
C
L
Symbol
Parameter
(V)
Units
ns
L
(Note 11)
Typ
t
Setup Time, HIGH or LOW
5.0
1.0
5.5
5.5
1.5
5.0
S
D
to CP
n
t
Hold Time, HIGH or LOW
to CP
5.0
5.0
0
1.5
5.0
ns
H
D
n
t
CP Pulse Width,
HIGH or LOW
2.5
ns
W
Note 11: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Input Capacitance
Typ
Units
Conditions
C
4.5
pF
V
OPEN
IN
CC
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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