74ACTQ02SCX [FAIRCHILD]
Quad 2-input NOR Gate ; 四2输入或非门\n
| 型号： | 74ACTQ02SCX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad 2-input NOR Gate
|
| 文件： | 总7页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1990
Revised November 1999
74ACTQ02
Quad 2-Input NOR Gate
General Description
The ACTQ02 contains four, 2-input NOR gates.
Features
■ ICC reduced by 50%
The ACTQ utilize Fairchild’s Quiet Series technology to
guarantee quiet output switching and improved dynamic
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
threshold performance. FACT Quiet Series
features
■ Improved latch-up immunity
■ Outputs source/sink 24 mA
GTO output control and undershoot corrector in addition
to a split ground bus for superior ACMOS performance.
■ ACTQ02 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACTQ02SC
74ACTQ02SJ
74ACTQ02PC
M14A
M14D
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
An, Bn
On
Description
Inputs
Outputs
FACT , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010889
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
−20 mA
+20 mA
Input Voltage (VI)
VI = VCC + 0.5V
Output Voltage (VO)
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Operating Temperature (TA)
−40°C to +85°C
125 mV/ns
DC Output Diode Current (IOK
)
Minimum Input Edge Rate (∆V/∆t)
V
V
O = −0.5V
−20 mA
+20 mA
V
IN from 0.8V to 2.0V
O = VCC + 0.5V
VCC @ 4.5V, 5.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
or Sink Current (IO)
±50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
Storage Temperature (TSTG
DC Latch-Up Source or
Sink Current
)
−65°C to +150°C
±300 mA
140°C
Junction Temperature (TJ)
PDIP
DC Electrical Characteristics
T
A = +25°C
TA = −40°C to +85°C
VCC
(V)
Symbol
Parameter
Units
Conditions
VOUT = 0.1V
Typ
1.5
Guaranteed Limits
VIH
Minimum HIGH Level
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
Input Voltage
1.5
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
1.5
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = −24 mA
OH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
5.5
5.5
5.5
5.5
5.5
0.36
0.36
± 0.1
0.44
0.44
± 1.0
1.5
I
I
OL = 24 mA
OL = 24 mA (Note 2)
IIN
Maximum Input Leakage Current
Maximum ICC/Input
µA
mA
mA
mA
µA
VI = VCC, GND
VI = VCC − 2.1V
ICCT
IOLD
IOHD
ICC
1.6
Minimum Dynamic
75
V
OLD = 1.65V Max
VOHD = 3.85V Min
IN = VCC or GND
Output Current (Note 3)
−75
20.0
Maximum Quiescent Supply Current
2.0
1.5
V
VOLP
Quiet Output
|Maximum Dynamic VOL
Figure 1, Figure 2
(Note 4)(Note 5)
5.0
5.0
5.0
5.0
1.1
−0.6
1.9
V
V
V
V
VOLV
VIHD
VILD
Quiet Output
Minimum Dynamic VOL
Figure 1, Figure 2
(Note 4)(Note 5)
−1.2
2.2
Minimum HIGH Level
Dynamic Input Voltage
(Note 4)(Note 6)
(Note 4)(Note 6)
Maximum LOW Level
Dynamic Input Voltage
1.2
0.8
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: Plastic DIP package
Note 5: Max number of outputs defined as (n). Data inputs are 0V to 3V. One output @ GND.
Note 6: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD),
0V to threshold (VIHD), f = 1 MHz.
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2
AC Electrical Characteristics
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 7)
5.0
Units
Min
2.0
2.0
Typ
5.0
5.0
Max
7.5
Min
tPLH
Propagation Delay Data to Output
Propagation Delay Data to Output
Output to Output
2.0
2.0
8.0
8.0
ns
ns
tPHL
5.0
7.5
tOSHL,
tOSLH
5.0
0.5
1.0
1.0
ns
Skew (Note 8)
Note 7: Voltage Range 5.0 is 5.0V ± 0.5V
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
Units
Conditions
CIN
4.5
75
pF
pF
V
V
CC = OPEN
CC = 5.0V
CPD
3
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FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/VOHV:
•
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
•
•
Measure VOLP and VOLV on the quiet output during the
worst case transition for active and enable. VOHP and
VOHV on the quiet output during the worst case transition
for active and enable.
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
V
ILD and VIHD:
•
Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
•
•
•
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measure-
ment.
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD
.
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 9: VOHV and VOLP are measured with respect to ground refer-
ence.
Note 10: Input pulses have the following characteristics: f = 1 MHz,
t
r = 3 ns, tf = 3 ns, skew < 150 ps.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
FIGURE 2. Simultaneous Switching Test Circuit
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4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
Package Number M14A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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