74ACTQ04MTC [FAIRCHILD]
Quiet Series Hex Inverter; 宁静系列六反相器
| 型号： | 74ACTQ04MTC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quiet Series Hex Inverter |
| 文件： | 总8页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1990
Revised February 2005
74ACTQ04
Quiet Series¥ Hex Inverter
General Description
Features
The ACTQ04 contains six inverters and utilizes Fairchild
Quiet Series technology to guarantee quiet output switch-
ing and improved dynamic threshold performance. FACT
Quiet Series features GTO output control and under-
shoot corrector in addition to a split ground bus for superior
ACMOS performance.
■ ICC reduced by 50%
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Improved latch-up immunity
■ Outputs source/sink 24 mA
■ Has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACTQ04SC
74ACTQ04SJ
74ACTQ04MTC
74ACTQ04PC
M14A
M14D
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
Inputs
An
On
Outputs
FACT , Quiet Series , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS010890
www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Diode Current (IIK
VI 0.5V
)
0.5V to 7.0V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
20 mA
20 mA
Input Voltage (VI)
VI VCC 0.5V
Output Voltage (VO)
0V to VCC
DC Input Voltage (VI)
0.5V to VCC 0.5V
Operating Temperature (TA)
40 C to 85 C
125 mV/ns
DC Output Diode Current (IOK
VO 0.5V
)
Minimum Input Edge Rate ( V/ t)
20 mA
20 mA
V
IN from 0.8V to 2.0V
VO VCC 0.5V
VCC @ 4.5V, 5.5V
DC Output Voltage (VO)
DC Output Source
0.5V to VCC 0.5V
or Sink Current (IO)
50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
50 mA
Note 1: Absolute maximum ratings are those values beyond which dam-
age to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild
does not recommend operation outside of databook specifications.
Storage Temperature (TSTG
DC Latch-up Source
or Sink Current
)
65 C to 150 C
300 mA
140 C
Junction Temperature (TJ)
PDIP
DC Electrical Characteristics for ACTQ
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
V
V
V
Minimum HIGH Level
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
0.1V
IH
OUT
V
V
V
Input Voltage
1.5
2.0
0.8
0.8
4.4
5.4
or V
0.1V
0.1V
0.1V
CC
Maximum LOW Level
Input Voltage
1.5
V
IL
OUT
1.5
or V
CC
Minimum HIGH Level
Output Voltage
4.49
5.49
OH
I
50
or V
A
OUT
V
V
IL
IN
IH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
=
24 mA
OH
OH
=
24 mA (Note 2)
V
Maximum LOW Level
Output Voltage
0.001
0.001
OL
I
50
A
OUT
0.1
0.1
V
V
or V
IN
IL
IH
4.5
5.5
5.5
5.5
5.5
5.5
5.5
5.0
0.36
0.36
0.1
0.44
0.44
1.0
I
I
= 24 mA
OL
OL
= 24 mA (Note 2)
I
I
I
I
I
Maximum Input Leakage Current
A
mA
mA
mA
A
V
V
V
V
V
V
V
, GND
2.1V
IN
I
I
CC
CC
Maximum I /Input
CC
0.6
1.5
CCT
OLD
OHD
CC
Minimum Dynamic
75
1.65V Max
3.85V Min
OLD
OHD
IN
Output Current (Note 3)
75
Maximum Quiescent Supply Current
2.0
1.5
20.0
V
or GND
CC
V
Quiet Output Maximum Dynamic V
1.1
0.6
V
Figure 1, Figure 2
(Note 4)(Note 5)
Figure 1, Figure 2
(Note 4)(Note 5)
(Note 4)(Note 6)
(Note 4)(Note 6)
OLP
OL
V
Quiet Output Minimum Dynamic V
5.0
1.2
V
OLV
OL
V
V
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
5.0
5.0
1.9
1.2
2.2
0.8
V
V
IHD
ILD
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: DIP package.
Note 5: Max number of outputs defined as (n). Data inputs are 0V to 3V. One output @ GND.
Note 6: Max number of data inputs (n) switching. (n 1) inputs switching 0V to 3V Input-under-test switching: 3V to threshold (V
),
ILD
0V to threshold (V ), f 1 MHz.
IHD
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2
AC Electrical Characteristics
V
T
25 C
T
40 C to 85 C
50 pF
Min Max
CC
A
A
Symbol
Parameter
(V)
C
50 pF
C
Units
L
L
(Note 7)
Min
Typ
Max
t
t
Propagation Delay
PLH
5.0
5.0
5.0
2.0
6.5
6.5
0.5
7.5
2.0
2.0
8.0
8.0
1.0
ns
ns
ns
Data to Output
Propagation Delay
Data to Output
Output to Output
Skew (Note 8)
PHL
2.0
7.5
1.0
t
t
OSHL
OSLH
Note 7: Voltage Range 5.0 is 5.0V 0.5V.
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
). Parameter guaranteed by design.
OSHL
OSLH
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
75
Units
Conditions
C
pF
pF
V
V
OPEN
5.0V
IN
CC
CC
C
PD
3
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V
•
OLP/VOLV and VOHP/V OHV:
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50 coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
noise characteristics of FACT
.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
•
•
Measure VOLP and VOLV on the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
Tektronics Model 7854 Oscilloscope
Procedure:
case transition.for active and enable
1. Verify Test Fixture Loading: Standard Load 50 pF,
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
500
.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
V
ILD and VIHD:
•
Monitor one of the switching outputs using a 50 coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
•
•
•
First increase the input LOW voltage level, VIL, until the
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD
.
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as V IHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
and V
are measured with respect to ground reference.
OLP
OHV
Input pulses have the following characteristics: f 1 MHz, t 3 ns, t
r
f
3 ns, skew 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
FIGURE 2. Simultaneous Switching Test Circuit
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4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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