74ACTQ18823SSC [FAIRCHILD]
18-Bit D-Type Flip-Flop with 3-STATE Outputs; 18位D型触发器带3态输出
| 型号： | 74ACTQ18823SSC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 18-Bit D-Type Flip-Flop with 3-STATE Outputs |
| 文件： | 总9页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1991
Revised November 1999
74ACTQ18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
Features
The ACTQ18823 contains eighteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP), Clear (CLR), Clock Enable (EN) and
Output Enable (OE) are common to each byte and can be
shorted together for full 18-bit operation.
■ Utilizes Fairchild’s FACT Quiet Series technology
■ Broadside pinout allows for easy board layout
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin output skew
■ Separate control logic for each byte
The ACTQ18823 utilizes Fairchild’s Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control and undershoot corrector for
superior performance.
■ Extra data width for wider address/data paths or buses
carrying parity
■ Outputs source/sink 24 mA
■ Additional specs for Multiple Output Switching
■ Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number
74ACTQ18823SSC
74ACTQ18823MTD
Package Number
MS56A
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD56
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
Description
Output Enable Input (Active LOW)
Clear (Active LOW)
Clock Enable (Active LOW)
Clock Pulse Input
CLRn
ENn
CPn
I0–I17
O0–O17
Inputs
Outputs
FACT , Quiet Series , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010953
www.fairchildsemi.com
Connection Diagram
Functional Description
The ACTQ18823 consists of eighteen D-type edge-trig-
gered flip-flops. These have 3-STATE outputs for bus sys-
tems organized with inputs and outputs on opposite sides.
The device is byte controlled with each byte functioning
identically, but independent of the other. The control pins
can be shorted together to obtain full 16-bit operation. The
following description applies to each byte. The buffered
clock (CPn) and buffered Output Enable (OEn) are com-
mon to all flip-flops within that byte. The flip-flops will store
the state of their individual D inputs that meet set-up and
hold time requirements on the LOW-to-HIGH CPn transi-
tion. With OEn LOW, the contents of the flip-flops are avail-
able at the outputs. When OEn is HIGH, the outputs go to
the impedance state. Operation of the OEn input does not
affect the state of the flip-flops. In addition to the Clock and
Output Enable pins, there are Clear (CLRn) and Clock
Enable (ENn) pins. These devices are ideal for parity bus
interfacing in high performance systems.
When CLRn is LOW and OEn is LOW, the outputs are
LOW. When CLRn is HIGH, data can be entered into the
flip-flops. When ENn is LOW, data on the inputs is trans-
ferred to the outputs on the LOW-to-HIGH clock transition.
When the ENn is HIGH, the outputs do not change state,
regardless of the data or clock input transitions.
Function Table (Note 1)
Inputs
Internal
Q
Output
On
Function
OE
CLR
EN
CP
In
H
H
H
L
X
X
L
L
L
L
H
X
X
X
X
L
L
H
Z
Z
High Z
High Z
Clear
Clear
Hold
X
X
H
H
L
X
X
X
X
L
Z
L
L
L
H
L
H
H
H
H
H
H
NC
NC
L
Z
NC
Z
Hold
H
H
L
Load
Load
Load
Load
L
H
L
H
Z
L
L
L
L
L
H
H
H
H= HIGH Voltage Level
L= LOW Voltage Level
X= Immaterial
Z= High Impedance
= LOW-to-HIGH Transition
NC= No Change
Note 1: The table represents the logic for one byte. The two bytes are independent of each other and function identically.
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2
Logic Diagrams
Byte 1 (0:8)
Byte 2 (9:17)
3
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Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
−20 mA
+20 mA
Input Voltage (VI)
VI = VCC +0.5V
Output Voltage (VO)
0V to VCC
DC Output Diode Current (IOK
)
Operating Temperature (TA)
−40°C to +85°C
125 mV/ns
V
V
O = −0.5V
−20 mA
+20 mA
Minimum Input Edge Rate (∆V/∆t)
O = VCC +0.5V
V
IN from 0.8V to 2.0V
DC Output Voltage (VO)
−0.5V to VCC + 0.5V
± 50 mA
VCC @ 4.5V, 5.5V
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
Per Output Pin
± 50 mA
Junction Temperature
PDIP/SOIC
+140°C
−65°C to +150°C
4000V
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
Storage Temperature
ESD Last Passing Voltage (Min)
DC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
VIH
Minimum HIGH
Input Voltage
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC −0.1V
OUT = 0.1V
or VCC −0.1V
V
V
V
1.5
VIL
Maximum LOW
Input Voltage
1.5
V
1.5
VOH
Minimum HIGH
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
I
I
OH = −24 mA
OH = −24 mA (Note 3)
VOL
Maximum LOW
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
VIN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
V
I
I
OL = 24 mA
OL = 24 mA (Note 3)
IOZ
Maximum 3-STATE
VI = VIL, VIH
VO = VCC, GND
5.5
±0.5
±0.1
±5.0
µA
Leakage Current
IIN
Maximum Input Leakage Current
Maximum ICC/Input
5.5
5.5
5.5
±1.0
1.5
µA
mA
µA
mA
mA
V
VI = VCC, GND
VI = VCC −2.1V
ICCT
ICC
0.6
Maximum Quiescent Supply Current
Minimum Dynamic
8.0
80.0
75
VIN = VCC or GND
VOLD = 1.65V Max
VOHD = 3.85V Min
IOLD
IOHD
VOLP
VOLV
VOHP
VOHV
VIHD
VILD
5.5
Output Current (Note 4)
−75
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
Maximum Overshoot
5.0
5.0
5.0
5.0
5.0
5.0
0.5
−0.5
0.8
(Note 6)(Note 7)
(Note 6)(Note 7)
(Note 5)(Note 7)
(Note 5)(Note 7)
(Note 5)(Note 8)
(Note 5)(Note 8)
−0.8
V
V
OH + 1.0
OH − 1.0
1.7
V
OH + 1.5
OH − 1.8
2.0
V
Minimum VCC Droop
V
V
V
Minimum High Voltage Level
Maximum Low Dynamic Input Voltage Level
V
1.2
1.2
V
Note 3: All outputs loaded; thresholds associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Worst case package.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW.
Note 7: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH.
Note 8: Maximum number of data inputs (n) switching. (n − 1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD).
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4
AC Electrical Characteristics
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 9)
Min
Typ
Max
Min
fMAX
Maximum Clock
Frequency
5.0
5.0
100
90
MHz
ns
tPHL
tPLH
tPHL
Propagation Delay
CPn to On
2.0
2.0
9.0
9.0
2.0
2.0
9.5
9.5
Propagation Delay
CLRn to On
5.0
5.0
2.0
9.0
2.0
9.5
ns
tPZL
tPZH
tPLZ
tPHZ
Output Enable Time
2.0
2.0
1.5
1.5
9.0
9.0
7.0
8.0
2.0
2.0
1.5
1.5
10.0
10.0
7.5
ns
Output Disable Time
5.0
ns
8.5
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements
VCC
(V)
T
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
L = 50 pF
Guaranteed Minimum
C
C
Symbol
Parameter
Units
(Note 10)
Typ
tS
tH
tS
tH
Setup Time, HIGH or LOW,
Input to Clock
5.0
3.0
3.0
1.5
3.0
1.5
ns
ns
ns
ns
Hold Time, HIGH or LOW,
Input to Clock
5.0
5.0
5.0
1.5
3.0
1.5
Setup Time, HIGH or LOW,
Enable to Clock
Hold Time, HIGH or LOW,
Enable to Clock
tW
CPn Pulse Width,
HIGH or LOW
5.0
4.0
4.0
ns
tW
CLRn Pulse Width,
HIGH or LOW
Recovery Time,
CLRn to CPn
5.0
5.0
4.0
6.0
4.0
6.0
ns
ns
tREC
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V.
5
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Extended AC Electrical Characteristics
T
A = −40°C to +85°C
VCC = Com
L = 50 pF
T
A = −40°C to +85°C
CC = Com
L = 250 pF
C
V
Symbol
Parameter
Units
C
16 Outputs Switching
(Note 12)
Typ
(Note 13)
Min
5.2
5.3
Max
7.6
Min
Max
9.8
tPLH
tPHL
tPHL
Propagation Delay
6.5
7.0
6.8
ns
ns
ns
ns
ns
ns
ns
ns
CPn to On
6.5
7.8
10.0
Propagation Delay
CLRn to On
4.8
5.3
6.2
5.2
7.5
tPZH
Output Enable Time
4.2
4.4
3.5
4.6
4.8
5.3
4.2
5.2
6.5
6.0
4.8
6.0
(Note 14)
(Note 15)
tPZL
tPHZ
Output Disable Time
tPZL
tOSHL
Pin to Pin Skew
CPn to On
1.0
1.0
1.0
1.5
(Note 11)
tOSLH
Pin to Pin Skew
CPn to On
(Note 11)
tOSHL
Pin to Pin Skew
CLRn to Output
Pin to Pin Skew
CPn to Output
(Note 11)
tOST
(Note 11)
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (tOST).
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (il.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 14: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 15: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol
Parameter
Input Pin Capacitance
Power Dissipation Capacitance
Typ
4.5
95
Units
pF
Conditions
CIN
V
V
CC = 5.0V
CC = 5.0V
CPD
pF
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6
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/VOHV:
•
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
•
•
Measure VOLP and VOLV on the quiet output during the
Tektronics Model 7854 Oscilloscope
Procedure:
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
1. Verify Test Fixture Loading: Standard Load 50 pF,
case active and enable transition.
500Ω.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
V
ILD and VIHD:
•
Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
•
•
•
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measure-
ment.
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD
.
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillator steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
VOHV and VOLP are measured with respect to ground reference.
Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns,
tf = 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
FIGURE 2. Simultaneous Switching Test Circuit
7
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Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS56A
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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相关型号：
74ACTQ18823SSC_NL
Bus Driver, ACT Series, 2-Func, 9-Bit, True Output, CMOS, PDSO56, 0.300 INCH, LEAD FREE, MO-118, SSOP-56
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