74F112_00 [FAIRCHILD]
Dual JK Negative Edge-Triggered Flip-Flop; 双JK负边沿触发触发器
| 型号： | 74F112_00 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual JK Negative Edge-Triggered Flip-Flop |
| 文件： | 总7页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised September 2000
74F112
Dual JK Negative Edge-Triggered Flip-Flop
Simultaneous LOW signals on SD and CD force both Q and
Q HIGH.
General Description
The 74F112 contains two independent, high-speed JK flip-
flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trig-
gering occurs at a voltage level of the clock and is not
directly related to the transition time. The J and K inputs
can change when the clock is in either state without affect-
ing the flip-flop, provided that they are in the desired state
during the recommended setup and hold times relative to
the falling edge of the clock. A LOW signal on SD or CD
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q
and Q HIGH
prevents clocking and forces Q or Q HIGH, respectively.
Ordering Code:
Order Number Package Number
Package Description
74F112SC
74F112SJ
74F112PC
M16A
M16D
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009472
www.fairchildsemi.com
Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
1.0/1.0
J1, J2, K1, K2 Data Inputs
20 µA/−0.6 mA
20 µA/−2.4 mA
20 µA/−3.0 mA
20 µA/−3.0 mA
−1 mA/20 mA
CP1, CP2
D1, CD2
SD1, SD2
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
1.0/4.0
C
1.0/5.0
1.0/5.0
Q1, Q2, Q1, Q2 Outputs
50/33.3
Truth Table
Inputs
Outputs
SD
CD
CP
X
J
X
X
X
h
l
K
X
X
X
h
h
l
Q
H
Q
L
L
H
L
H
L
X
L
H
L
X
H
H
H
H
H
H
H
H
H
H
Q0
L
Q0
H
h
l
H
L
l
Q0
Q0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Clock Transition
Q0(Q0) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
2.0
V
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
VIL
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
0.8
VCD
VOH
−1.2
Min
Min
I
I
I
IN = −18 mA
OH = −1 mA
OH = −1 mA
10% VCC
5% VCC
2.5
2.7
VOL
Output LOW
10% VCC
0.5
5.0
7.0
50
V
Min
Max
Max
Max
0.0
I
OL = 20 mA
Voltage
IIH
Input HIGH
µA
µA
µA
V
V
V
V
IN = 2.7V
IN = 7.0V
OUT = VCC
Current
IBVI
ICEX
VID
IOD
IIL
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
I
ID = 1.9 µA
All other pins grounded
IOD = 150 mV
All other pins grounded
4.75
Output Leakage
Circuit Current
Input LOW Current
V
3.75
µA
0.0
−0.6
−2.4
−3.0
−150
19
V
V
V
V
V
V
IN = 0.5V (Jn, Kn)
IN = 0.5V (CPn)
IN = 0.5V (CDn, SDn
OUT = 0V
mA
Max
)
IOS
Output Short-Circuit Current
Power Supply Current
Power Supply Current
−60
mA
mA
mA
Max
Max
Max
ICCH
ICCL
12
12
O = HIGH
19
O = LOW
3
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AC Electrical Characteristics
T
A = +25°C
T
A = 0°C to +70°C
CC = +5.0V
L = 50 pF
Max
V
CC = +5.0V
V
Symbol
Parameter
Units
C
L = 50 pF
C
Min
85
Typ
105
5.0
5.0
4.5
4.5
Max
Min
80
fMAX
Maximum Clock Frequency
MHz
ns
tPLH
tPHL
tPLH
tPHL
Propagation Delay
CPn to Qn or Qn
2.0
2.0
2.0
2.0
6.5
6.5
6.5
6.5
2.0
2.0
2.0
2.0
7.5
7.5
7.5
7.5
Propagation Delay
CDn, SDn to Qn, Qn
ns
AC Operating Requirements
T
A = +25°C
CC = +5.0V
Max
T
A = 0°C to +70°C
CC = +5.0V
Max
Symbol
Parameter
V
V
Units
Min
4.0
3.0
0
Min
5.0
3.5
0
tS(H)
Setup Time, HIGH or LOW
Jn or Kn to CPn
tS(L)
tH(H)
tH(L)
ns
Hold Time, HIGH or LOW
Jn or Kn to CPn
0
0
tW(H)
tW(L)
tW(L)
CP Pulse Width
HIGH or LOW
4.5
4.5
5.0
5.0
ns
ns
ns
Pulse Width, LOW
4.5
4.0
5.0
5.0
CDn or SDn
tREC
Recovery Time
SDn, CDn to CP
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4
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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