74FR573PC [FAIRCHILD]
Octal D-Type Latch with 3-STATE Outputs; 八D型锁存器带3态输出
| 型号： | 74FR573PC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal D-Type Latch with 3-STATE Outputs |
| 文件： | 总6页 (文件大小：55K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1991
Revised August 1999
74FR573
Octal D-Type Latch with 3-STATE Outputs
General Description
The 74FR573 is a high speed octal latch with buffered
common Latch Enable (LE) and buffered common Output
Enable (OE) inputs.
Features
■ Broadside pinout aids in PC layout
■ Functionally identical to the 74F373, 74F573
■ Outputs have current sourcing capability of 15 mA and
current sinking capability of 64 mA
This device is functionally identical to the 74F573.
■ Guaranteed pin-to-pin skew
Ordering Code:
Order Number Package Number
Package Description
74FR573SC
74FR573PC
M20B
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
OE
Output Enable Input (Active-LOW)
Latch Enable Input (Active-HIGH)
Data Inputs
LE
D0–D7
O0–O7
3-STATE Latch Outputs
© 1999 Fairchild Semiconductor Corporation
DS010903
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Functional Description
Function Table
The 74FR573 contains eight D-type latches with 3-STATE
output buffers. When the latch enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
Inputs
Output
On
OE
LE
Dn
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode, but this does not interfere with entering
new data into the latches.
L
L
H
H
L
H
L
H
L
L
X
X
On − 1
H
X
High Z State
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to 125°C
−55° to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to 5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
−0.5 to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
3-STATE Output
Current Applied to Output
in LOW State (Max)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
4000V
ESD Last Passing Voltage (Min)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
Recognized HIGH Signal
Recognized LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
IL
−1.2
V
Min
Min
Min
Min
Max
I
I
I
I
= −18 mA
CD
OH
IN
2.4
2.0
V
= −3 mA
= −15 mA
= 64 mA
= 2.7V
OH
OH
IOL
Voltage
V
V
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
0.55
5
V
OL
I
I
µA
V
IH
IN
BVI
IL
7
µA
Max
V
= 7.0V
IN
I
Input LOW Current
−150
−100
µA
µA
V
Max
Max
0.0
V
V
= 0.5V Data Inputs
IN
= 0.5V Control Inputs
IN
V
Input Leakage Test
4.75
I
= 1.9 µA,
ID
ID
All Other Pins Grounded
µA = 150 mV,
I
Output Circuit
OD
IOD
3.75
µA
0.0
Leakage Current
All Other Pins Grounded
I
I
I
I
I
I
I
I
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
20
−20
−225
50
µA
µA
mA
µA
µA
mA
mA
mA
pF
Max
Max
Max
Max
0.0
V
V
V
V
V
= 2.7V
= 0.5V
= 0.0V
OZH
OZL
OS
OUT
OUT
OUT
OUT
OUT
−100
= V
CEX
ZZ
CC
100
32
= 5.25V
Power Supply Current
Power Supply Current
Power Supply Current
Input Capacitance
26
55
32
8.0
Max
Max
Max
5.0
All Outputs HIGH
All Outputs LOW
Outputs 3-STATED
CCH
CCL
CCZ
65
40
C
IN
3
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AC Electrical Characteristics
T
= +25°C
T = 0°C to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
Symbol
Parameter
Units
C
L
Min
1.7
1.7
2.6
2.6
2.8
2.8
2.2
2.2
Typ
2.9
2.6
6.0
4.3
4.0
5.0
4.0
3.5
Max
4.5
4.5
8.5
8.5
7.4
7.4
6.3
6.3
Min
1.7
1.7
2.6
2.6
2.8
2.8
2.2
2.2
Max
t
Propagation Delay
D to O
n
4.5
4.5
8.5
8.5
7.4
7.4
6.3
6.3
PLH
ns
ns
ns
ns
t
PHL
n
t
Propagation Delay
LE to O
PLH
t
PHL
n
t
Output Enable Time
PZH
t
PZL
t
Output Disable Time
PHZ
t
PLZ
AC Operating Requirements
T
= +25°C
T = 0°C to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
Symbol
Parameter
Units
C
L
Min
1.0
1.0
2.5
2.5
5.0
Typ
−0.4
−0.7
0.9
Max
Min
1.0
1.0
2.5
2.5
5.0
Max
t (H)
Setup Time, HIGH or LOW
to LE
S
ns
t (L)
D
n
S
t
(H)
(L)
Hold Time, HIGH or LOW
to LE
H
ns
ns
t
D
0.6
H
n
t
(H)
LE Pulse Width HIGH
2.7
W
Extended AC Electrical Characteristics
T
= 0°C to +70°C
T = 0°C to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
CC
CC
C
C
= 250 pF
L
L
Symbol
Parameter
Units
Eight Outputs Switching
(Note 3)
(Note 4)
Min
1.7
1.7
2.6
2.6
2.8
2.8
2.2
2.2
Max
5.7
5.7
9.8
9.8
9.6
9.6
7.3
7.3
Min
3.4
3.4
4.5
4.5
Max
8.1
t
Propagation Delay
to O
PLH
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
D
8.1
PHL
PLH
PHL
PZH
PZL
n
n
Propagation Delay
LE to O
12.3
12.3
n
Output Enable Time
Output Disable Time
PHZ
PLZ
Pin-to-Pin Skew
for HL Transitions
Pin-to-Pin Skew
for LH Transitions
Pin-to-Pin Skew
for HL/LH Transitions
OSHL
1.3
1.3
3.0
(Note 5)
t
OSLH
(Note 5)
t
OST
(Note 5)
Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase,
i.e. all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc.
Note 4: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 5: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specifi-
cation applies to any outputs switching HIGH-to-LOW, (t
), LOW-to-HIGH, (t
) or any combination of HIGH-to-LOW and/or LOW-to-HIGH, (t
).
OSHL
OSLH
OST
Specifications guaranteed with all outputs switching in phase.
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
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device or system, or to affect its safety or effectiveness.
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