74LCX16245MEA [FAIRCHILD]
Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs; 低电压16位双向收发器，具有5V容限输入和输出
| 型号： | 74LCX16245MEA |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs |
| 文件： | 总9页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1994
Revised May 2005
74LCX16245
Low Voltage 16-Bit Bidirectional Transceiver
with 5V Tolerant Inputs and Outputs
General Description
Features
■ 5V tolerant inputs and outputs
The LCX16245 contains sixteen non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus ori-
ented applications. The device is designed for low voltage
(2.5V or 3.3V) VCC applications with capability of interfac-
■ 2.3V–3.6V VCC specifications provided
■ 4.5 ns tPD max (VCC 3.3V), 20 A ICC max
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
ing to a 5V signal environment. The device is byte con-
trolled. Each byte has separate control inputs which could
be shorted together for full 16-bit operation. The T/R inputs
determine the direction of data flow through the device.
The OE inputs disable both the A and B ports by placing
them in a high impedance state.
■
24 mA output drive (VCC 3.0V)
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
The LCX16245 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Human body model 2000V
Machine model 200V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
through a pull-up resistor: the minimum value or the
CC
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX16245G
(Note 2)(Note 3)
BGA54A
MS48A
MTD48
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LCX16245MEA
(Note 3)
74LCX16245MTD
(Note 3)
Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS012001
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Connection Diagrams
Pin Descriptions
Pin Names
Description
Output Enable Input
Transmit/Receive Input
Pin Assignment for SSOP and TSSOP
OEn
T/Rn
A0–A15
B0–B15
NC
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
B0
B2
NC
B1
T/R1
NC
OE1
NC
NC
A1
A0
A2
B4
B3
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
A3
A4
B6
B5
A5
A6
B8
B7
A7
A8
B10
B12
B14
B9
A9
A10
A12
A14
G
H
B11
B13
A11
A13
J
B15
NC
T/R2
OE2
NC
A15
Truth Tables
Inputs
Pin Assignment for FBGA
Outputs
OE1
T/R1
L
L
L
H
X
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
HIGH Z State on A0–A7, B0–B7
H
Inputs
Outputs
OE2
T/R2
L
L
L
H
X
Bus B8–B15 Data to Bus A8–A15
Bus A8–A15 Data to Bus B8–B15
H
HIGH Z State on A8–A15, B8–B15
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
(Top Thru View)
High Impedance
Logic Diagrams
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 4)
Symbol
VCC
Parameter
Supply Voltage
Value
Conditions
Units
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
V
V
VI
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE
V
0.5 to VCC 0.5 Output in HIGH or LOW State (Note 5)
IIK
DC Input Diode Current
DC Output Diode Current
50
50
VI GND
VO GND
VO VCC
mA
mA
IOK
50
IO
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
50
mA
mA
mA
C
ICC
100
IGND
TSTG
100
65 to 150
Recommended Operating Conditions (Note 6)
Symbol
Parameter
Min
2.0
1.5
0
Max
3.6
3.6
5.5
VCC
5.5
24
Units
VCC
Supply Voltage
Operating
V
V
V
Data Retention
VI
Input Voltage
VO
Output Voltage
HIGH or LOW State
3-STATE
0
0
IOH/IOL
Output Current
VCC 3.0V 3.6V
VCC 2.7V 3.0V
VCC 2.3V 2.7V
12
mA
8
TA
Free-Air Operating Temperature
40
0
85
C
t/ V
Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V
10
ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 5: I Absolute Maximum Rating must be observed.
O
Note 6: Unused inputs or I/O's must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
V
T
40 C to 85 C
Min Max
CC
A
Symbol
Parameter
Conditions
Units
(V)
2.3 2.7
2.7 3.6
2.3 2.7
2.7 3.6
2.3 3.6
2.3
V
V
V
HIGH Level Input Voltage
1.7
2.0
IH
V
V
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
IL
0.8
I
I
I
I
I
I
I
I
I
I
100
A
V
CC
0.2
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
8 mA
1.8
2.2
2.4
2.2
12 mA
18 mA
24 mA
2.7
V
V
3.0
3.0
V
LOW Level Output Voltage
100
8mA
A
2.3 3.6
2.3
0.2
0.6
0.4
0.4
0.55
5.0
5.0
OL
12 mA
16 mA
24 mA
2.7
3.0
3.0
I
I
Input Leakage Current
3-STATE I/O Leakage
0
0
V
V
V
5.5V
5.5V
2.3 3.6
2.3 3.6
A
A
A
I
I
OZ
O
V
or V
IL
I
IH
I
Power-Off Leakage Current
V or V
O
5.5V
0
10
OFF
I
3
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DC Electrical Characteristics (Continued)
V
T
40 C to 85 C
CC
A
Symbol
Parameter
Conditions
V or GND
CC
Units
(V)
Min
Max
20
I
Quiescent Supply Current
V
2.3–3.6
2.3–3.6
2.3–3.6
CC
I
A
A
3.6V V , V
5.5V (Note 7)
20
I
O
I
Increase in I per Input
V
V 0.6V
CC
500
CC
CC
IH
Note 7: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
40 C to 85 C, R
500
A
L
V
3.3V 0.3V
50 pF
V
2.7V
V
CC
2.5V 0.2V
CC
CC
Symbol
Parameter
Units
C
C
50 pF
C
L
30 pF
Max
L
L
Min
1.5
1.5
1.5
1.5
1.5
1.5
Max
4.5
4.5
6.5
6.5
6.4
6.4
1.0
1.0
Min
Max
5.2
5.2
7.2
7.2
6.9
6.9
Min
1.5
1.5
1.5
1.5
1.5
1.5
t
Propagation Delay
A to B or B to A
n
1.5
1.5
1.5
1.5
1.5
1.5
5.4
5.4
8.5
8.5
7.7
7.7
PHL
ns
ns
ns
ns
t
t
t
t
t
t
t
PLH
n
n
n
Output Enable Time
PZL
PZH
PLZ
Output Disable Time
PHZ
OSHL
OSLH
Output to Output Skew
(Note 8)
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
). Parameter guaranteed by design.
OSLH
OSHL
Dynamic Switching Characteristics
V
T
25 C
CC
A
Symbol
Parameter
Conditions
Units
(V)
3.3
2.5
3.3
2.5
Typical
0.8
V
Quiet Output Dynamic Peak V
C
C
C
C
50 pF, V
30 pF, V
50 pF, V
30 pF, V
3.3V, V
2.5V, V
3.3V, V
2.5V, V
0V
0V
0V
0V
OLP
OL
L
L
L
L
IH
IH
IH
IH
IL
IL
IL
IL
V
V
0.6
V
Quiet Output Dynamic Valley V
0.8
OLV
OL
0.6
Capacitance
Symbol
Parameter
Conditions
Typical
Units
pF
C
Input Capacitance
Input/Output Capacitance
Power Dissipation Capacitance
V
V
V
Open, V 0V or V
CC
7
8
IN
CC
CC
CC
I
C
C
3.3V, V 0V or V
CC
pF
I/O
PD
I
3.3V, V 0V or V , f 10 MHz
20
pF
I
CC
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4
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
PLH, tPHL
PZL, tPLZ
Switch
Open
t
t
6V at VCC 3.3 0.3V
VCC x 2 at VCC 2.5 0.2V
tPZH,tPHZ
GND
3-STATE Output High Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and trec Waveforms
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
VCC
Symbol
3.3V 0.3V
1.5V
2.7V
1.5V
2.5V 0.2V
VCC/2
Vmi
Vmo
Vx
1.5V
1.5V
VCC/2
VOL 0.3V
VOH 0.3V
VOL 0.3V
VOH 0.3V
VOL 0.15V
VOH 0.15V
Vy
5
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Schematic Diagram Generic for LCX Family
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6
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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