74LCX373MTCX-NL [FAIRCHILD]
Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs; 低电压八路透明锁存器，具有5V容限输入和输出
| 型号： | 74LCX373MTCX-NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs |
| 文件： | 总15页 (文件大小：747K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2006
74LCX373
Low Voltage Octal Transparent Latch
with 5V Tolerant Inputs and Outputs
Features
General Description
■ 5V tolerant inputs and outputs
The LCX373 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The device is
designed for low voltage applications with capability of
interfacing to a 5V signal environment.
■ 2.3V–3.6V V specifications provided
CC
■ 8.0ns t max (V = 3.3V), 10µA I max
PD
CC
CC
■ Power down high impedance inputs and outputs
1
The LCX373 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
■ Supports live insertion/withdrawal
■ ±24mA output drive (V = 3.0V)
CC
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance
– Human body model > 2000V
– Machine model > 200V
■ Leadless Pb-Free DQFN package
Ordering Information
Order
Number
Package
Number
Package Description
74LCX373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
74LCX373SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
2
74LCX373BQX
74LCX373MSA
74LCX373MTC
74LCX373MTCX_NL
MLP020B
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads
(DQFN), JEDEC MO-241, 2.5 x 4.5mm
MSA20
MTC20
MTC20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm
Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
3
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC
MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Notes:
1. To ensure the high impedance state during power up or down, OE should be tied to V through a pull-up resistor: the minimum
CC
value of the resistor is determined by the current-sourcing capability of the driver.
2. DQFN package available in Tape and Reel only.
3. “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
©2006 Fairchild Semiconductor Corporation
74LCX373 Rev. 2.0.0
1
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Logic Symbols
Pin Descriptions
Pin Names
Description
D0 D1 D2 D3 D4 D5 D6 D7
LE
D –D
Data Inputs
0
7
LE
Latch Enable Input
OE
OE
3-STATE Output Enable Input
3-STATE Latch Outputs
O0 O1 O2 O3 O4 O5 O6 O7
O –O
0
7
IEEE/IEC
EN
Truth Table
OE
LE
C1
Inputs
OE
Outputs
LE
X
D
O
n
D0
D1
D2
D3
D4
D5
D6
D7
1D
O0
O1
O2
O3
O4
O5
O6
O7
n
H
L
L
L
X
Z
H
L
H
X
L
H
H
L
O
0
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
Connection Diagrams
O = Previous O before HIGH-to-LOW transition of Latch
0
0
Enable
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
Functional Description
The LCX373 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
OE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
O7
D7
D6
O6
O5
D5
D4
O4
O0
D0
D1
O1
O2
D2
HIGH, data on the D inputs enters the latches. In this
n
condition the latches are transparent, i.e. a latch output
will change state each time its D input changes. When
LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the 2-state
mode. When OE is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
D3
O3
GND
LE
Pad Assignments for DQFN
VCC
OE
1
20
19
18
17
16
15
14
13
12
O0
D0
D1
O1
O2
D2
D3
O3
2
3
4
5
6
7
8
9
O7
D7
D6
O6
O5
D5
D4
O4
10
11
GND LE
(Top View)
2
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74LCX373 Rev. 2.0.0
Logic Diagram
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
D
D
D
D
D
D
D
O
O
O
O
O
O
O
O
G
G
G
G
G
G
G
G
LE
OE
O
O
O
O
O
O
O
O
7
0
1
2
3
4
5
6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
3
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74LCX373 Rev. 2.0.0
Absolute Maximum Ratings
The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The
device should not be operated at these limits.The parametric values defined in the Electrical Characteristics tables are
not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the
conditions for actual device operation.
Symbol
Parameter
Conditions
Value
Units
V
Supply Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
V
V
V
CC
I
V
DC Input Voltage
V
DC Output Voltage
Output in 3-STATE
Output in HIGH or LOW State
V < GND
O
4
−0.5 to V + 0.5
CC
I
I
DC Input Diode Current
DC Output Diode Current
−50
−50
mA
mA
IK
I
V
< GND
OK
O
V
> V
+50
O
CC
I
I
I
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±50
mA
mA
mA
°C
O
±100
CC
GND
±100
T
−65 to +150
STG
5
Recommended Operating Conditions
Symbol
Parameter
Conditions
Min.
Max.
3.6
Units
V
Supply Voltage
Operating
2.0
1.5
0
V
CC
Data Retention
3.6
V
Input Voltage
5.5
V
V
I
V
Output Voltage
HIGH or LOW State
3-STATE
0
V
CC
O
0
5.5
±24
±12
±8
I
/I
Output Current
V
V
V
= 3.0V − 3.6V
= 2.7V − 3.0V
= 2.3V − 2.7V
mA
OH OL
CC
CC
CC
T
Free-Air Operating Temperature
Input Edge Rate
−40
85
°C
A
∆t/∆V
V
= 0.8V − 2.0V, V = 3.0V
0
10
ns/V
IN
CC
Notes:
4.
I Absolute Maximum Rating must be observed.
O
5. Unused inputs must be held HIGH or LOW. They may not float.
4
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74LCX373 Rev. 2.0.0
DC Electrical Characteristics
T = −40°C to +85°C
A
Symbol
Parameter
Conditions
V
(V)
Min.
1.7
Max.
Units
CC
V
HIGH Level Input Voltage
2.3 − 2.7
2.7 − 3.6
2.3 − 2.7
2.7 − 3.6
2.3 − 3.6
2.3
V
IH
2.0
V
V
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
V
V
IL
I
I
I
I
I
I
I
I
I
I
= −100 µA
= −8 mA
= −12 mA
= −18 mA
= −24 mA
= 100 µA
= 8 mA
V
− 0.2
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
CC
1.8
2.2
2.4
2.2
2.7
3.0
3.0
V
LOW Level Output Voltage
2.3 − 3.6
2.3
0.2
0.6
V
OL
= 12 mA
= 16 mA
= 24 mA
2.7
0.4
3.0
0.4
3.0
0.55
±5.0
±5.0
I
I
Input Leakage Current
0 ≤ V ≤ 5.5V
2.3 − 3.6
2.3 − 3.6
µA
µA
I
I
3-STATE Output Leakage
0 ≤ V ≤ 5.5V,
O
OZ
V = V or V
I
IH
IL
I
I
Power-Off Leakage Current
Quiescent Supply Current
V or V = 5.5V
0
10
10
µA
µA
OFF
I
O
V = V or GND
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
CC
I
CC
6
3.6V ≤ V , V ≤ 5.5V
±10
500
I
O
∆I
Increase in I per Input
V
= V −0.6V
µA
CC
CC
IH
CC
AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500 Ω
V
CC = 3.3V ± 0.3V
VCC = 2.7V
CL = 50pF
VCC = 2.5 ± 0.2V
CL = 50pF
CL = 30pF
Symbol
, t
Parameter
Propagation Delay, D to O
n
Min.
1.5
1.5
1.5
1.5
2.5
1.5
3.3
Max.
8.0
Min.
Max.
9.0
Min.
1.5
1.5
1.5
1.5
4.0
2.0
4.0
Max.
9.6
Units
ns
t
t
t
t
t
t
t
t
1.5
1.5
1.5
1.5
2.5
1.5
3.3
PHL PLH
n
, t
Propagation Delay, LE to O
Output Enable Time
8.5
9.5
10.5
10.5
9.0
ns
PHL PLH
n
, t
8.5
9.5
ns
PZL PZH
, t
Output Disable Time
7.5
8.5
ns
PLZ PHZ
Setup Time, D to LE
ns
S
n
Hold Time, D to LE
ns
H
W
n
LE Pulse Width
ns
7
t
Output to Output Skew
1.0
ns
OSHL, OSLH
Notes:
6. Outputs disabled or 3-STATE only.
7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs
of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t ) or
OSHL
LOW-to-HIGH (t
).
OSLH
5
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74LCX373 Rev. 2.0.0
Dynamic Switching Characteristics
T = 25°C
A
Symbol
Parameter
Conditions
V
(V)
Typical
0.8
Units
CC
V
Quiet Output Dynamic Peak V
C = 50pF, V = 3.3V, V = 0V
3.3
V
OLP
OL
L
IH
IL
C = 30pF, V = 2.5V, V = 0V
2.5
3.3
2.5
0.6
L
I
IL
V
Quiet Output Dynamic Valley V
C = 50pF, V = 3.3V, V = 0V
−0.8
−0.6
V
OLV
OL
L
IH
IL
C = 30pF, V = 2.5V, V = 0V
L
I
IL
Capacitance
Symbol
Parameter
Conditions
Typical Units
C
C
C
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
V
V
V
= Open, V = 0V or V
CC
7
8
pF
pF
pF
IN
CC
CC
CC
I
= 3.3V, V = 0V or V
CC
OUT
PD
I
= 3.3V, V = 0V or V , f = 10MHz
25
I
CC
6
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74LCX373 Rev. 2.0.0
AC Loading and Waveforms (Generic for LCX Family)
V
CC
OPEN
GND
t
t
t
, t
PLH PHL
500Ω
TEST
, t
PZH PHZ
DUT
SIGNAL
V
, t
PZL PLZ
I
C
L
500Ω
Figure 1. AC Test Circuit (C includes probe and jig capacitance)
L
Test
Switch
t
, t
Open
PLH PHL
t
, t
6V at V = 3.3 ± 0.3V
CC
PZL PLZ
V
x 2 at V = 2.5 ± 0.2V
CC
CC
t
, t
GND
PZH PHZ
V
V
CC
CC
OUTPUT
CONTROL
DATA
IN
V
mi
V
mi
GND
GND
t
t
t
t
PHZ
pxx
pxx
PZH
V
V
OH
Y
DATA
OUT
DATA
OUT
V
V
mo
mo
3-STATE Output High Enable and
Disable Times for Logic
Waveform for Inverting and
Non-Inverting Functions
t
W
V
CC
DATA
V
V
CC
mi
CONTROL
IN
IN
V
mi
GND
GND
t
S
t
H
t
rec
V
CC
CONTROL
INPUT
V
mi
V
CLOCK
GND
mi
t
S
t
PHL
t
rec
t
PLH
MR
OR
CLEAR
V
mi
V
mo
OUTPUT
V
mo
Setup Time, Hold Time and
Recovery Time for Logic
Propagation Delay, Pulse Width and
Waveforms
t
rec
t
t
f
r
V
CC
OUTPUT
V
mi
CONTROL
GND
t
t
PLZ
PZL
V
V
OH
OL
90%
90%
10%
ANY
OUTPUT
DATA
OUT
V
mo
V
X
10%
V
OL
t
and t
fall
rise
3-STATE Output Low Enable and
Disable Times for Logic
Figure 2. Waveforms (Input Characteristics; f = 1MHz, t = t = 3ns)
r
f
V
CC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
1.5V
2.5V ± 0.2V
V
V
V
/ 2
/ 2
mi
CC
CC
V
1.5V
mo
V
V
+ 0.3V
− 0.3V
V
+ 0.3V
V
+ 0.15V
− 0.15V
x
y
OL
OL
OL
V
V
V
− 0.3V
V
OH
OH
OH
7
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74LCX373 Rev. 2.0.0
Schematic Diagram (Generic for LCX Family)
Input Stage
P2
P1
V
CC
Data
ESD
P5
X1
D2 N+/P–
V
DD
N1
N2
P4
GTO™
Output
Input Stage
D6
N+/P–
P3
N5
Enable
N4
ESD
D4 N+/P–
N3
8
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74LCX373 Rev. 2.0.0
Tape and Reel Specification
Tape Format for DQFN
Package
Designator
Tape
Section
Number
Cavities
Cavity
Status
Cover Tape
Status
BQX
Leader (Start End)
Carrier
125 (typ)
3000
Empty
Filled
Sealed
Sealed
Sealed
Trailer (Hub End)
75 (typ)
Empty
Tape Dimensions inches (millimeters)
Reel Dimensions inches (millimeters)
Tape Size
A
B
C
D
N
W1
W2
12 mm
13.0
(330.0)
0.059
(1.50)
0.512
(13.00)
0.795
(20.20)
2.165
(55.00)
0.488
(12.4)
0.724
(18.4)
9
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74LCX373 Rev. 2.0.0
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC),
JEDEC MS-013, 0.300" Wide Package Number M20B
10
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74LCX373 Rev. 2.0.0
Physical Dimensions (Continued) inches (millimeters) unless otherwise noted
Pb-Free 20-Lead Small Outline Package (SOP),
EIAJ TYPE II, 5.3mm Wide Package Number M20D
11
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74LCX373 Rev. 2.0.0
Physical Dimensions (Continued) inches (millimeters) unless otherwise noted
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 4.5mm Package Number MLP020B
12
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74LCX373 Rev. 2.0.0
Physical Dimensions (Continued) inches (millimeters) unless otherwise noted
20-Lead Shrink Small Outline Package (SSOP),
JEDEC MO-150, 5.3mm Wide Package Number MSA20
13
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74LCX373 Rev. 2.0.0
Physical Dimensions (Continued) inches (millimeters) unless otherwise noted
20-Lead Thin Shrink Small Outline Package (TSSOP),
JEDEC MO-153, 4.4mm Wide Package Number MTC20
14
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74LCX373 Rev. 2.0.0
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
FAST®
FASTr™
FPS™
FRFET™
GlobalOptoisolator™
GTO™
ACEx™
PowerSaver™
PowerTrench®
QFET®
SuperSOT™-6
SuperSOT™-8
SyncFET™
TCM™
ISOPLANAR™
LittleFET™
MICROCOUPLER™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
ActiveArray™
Bottomless™
Build it Now™
CoolFET™
CROSSVOLT™
DOME™
EcoSPARK™
E2CMOS™
EnSigna™
FACT™
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
µSerDes™
ScalarPump™
SILENT SWITCHER®
SMART START™
SPM™
TinyLogic®
TINYOPTO™
TruTranslation™
UHC™
HiSeC™
I2C™
MSXPro™
OCX™
OCXPro™
UltraFET®
UniFET™
VCX™
i-Lo™
ImpliedDisconnect™
IntelliMAX™
OPTOLOGIC®
OPTOPLANAR™
PACMAN™
POP™
Wire™
FACT Quiet Series™
Across the board. Around the world.™
The Power Franchise®
Programmable Active Droop™
Stealth™
SuperFET™
SuperSOT™-3
Power247™
PowerEdge™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVESTHE RIGHTTO MAKE CHANGES WITHOUTFURTHER NOTICETOANY
PRODUCTS HEREINTO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOTASSUMEANYLIABILITY
ARISING OUTOFTHEAPPLICATION OR USE OFANYPRODUCTOR CIRCUITDESCRIBED HEREIN; NEITHER DOES IT
CONVEYANYLICENSE UNDER ITS PATENTRIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILDíS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUTTHE EXPRESS WRITTENAPPROVALOF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I18
15
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74LCX373 Rev. 2.0.0
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