74LVTH16501MEAX_NL [FAIRCHILD]
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| 型号： | 74LVTH16501MEAX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 暂无描述 总线收发器 |
| 文件： | 总7页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2001
Revised March 2001
74LVTH16501
Low Voltage 18-Bit Universal Bus Transceivers
with Bushold and 3-STATE Outputs
General Description
The LVTH16501 is an 18-bit universal bus transceiver
combining D-type latches and D-type flip-flops to allow
data flow in transparent, latched, and clocked modes.
Features
■ Input and output interface capability to systems at
5V VCC
■ Bushold data inputs eliminate the need for external
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
pull-up resistors to hold unused inputs
■ Live insertion/extraction permitted
■ Power up/down high impedance provides glitch-free bus
loading
The LVTH16501 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
■ Outputs source/sink −32 mA/+64 mA
■ Functionally compatible with the 74 series 16501
■ ESD Performance:
The transceiver is designed for low voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH16501 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Human-Body Model > 2000V
Machine Model > 200V
Charged-Device Model > 1000V
Ordering Code:
Order Number
74LVTH16501MEA
74LVTH16501MTD
Package Number
MS56A
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD56
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation
DS500101
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Connection Diagram
Pin Descriptions
Pin Names
Description
A1–A18
B1–B18
Data Register A Inputs/3-STATE Outputs
Data Register B Inputs/3-STATE Outputs
CLKAB, CLKBA Clock Pulse Inputs
LEAB, LEBA
OEAB, OEBA
Latch Enable Inputs
Output Enable Inputs
Function Table (Note 1)
Inputs
Output
Bn
An
OEAB
LEAB
CLKAB
L
X
H
H
L
X
X
X
↑
X
L
Z
H
H
H
H
H
H
L
H
L
H
L
L
↑
H
X
X
H
L
H
L
B
0 (Note 2)
L
B0 (Note 3)
H = HIGH Voltage Level
X = Immaterial
L = LOW Voltage Level
Z = High Impedance
↑ = LOW-to-HIGH Clock Transition
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, and CLKBA. OEBA is active LOW
Note 2: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was HIGH before LEAB went LOW.
Note 3: Output level before the indicated steady-state input conditions
were established.
Functional Description
For A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A
data is latched if CLKAB is held at a HIGH or LOW logic
level. If LEAB is LOW, the A bus data is stored in the latch/
flip-flop on the LOW-to-HIGH transition of CLKAB. Output-
enable OEAB is active-HIGH. When OEAB is HIGH, the
outputs are active. When OEAB is LOW, the outputs are in
the high-impedance state.
Data flow for B to A is similar to that of A-to-B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active-HIGH and OEBA is active-
LOW).
Logic Diagram
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2
Absolute Maximum Ratings(Note 4)
Symbol
VCC
Parameter
Supply Voltage
Value
Conditions
Units
V
−0.5 to +4.6
−0.5 to +7.0
VI
DC Input Voltage
V
VO
DC Output Voltage
−0.5 to +7.0 Output in 3-STATE
V
−0.5 to +7.0 Output in HIGH or LOW State (Note 5)
V
IIK
IOK
IO
DC Input Diode Current
DC Output Diode Current
DC Output Current
−50
−50
VI < GND
mA
mA
V
V
V
O < GND
64
O > VCC Output at HIGH State
O > VCC Output at LOW State
mA
128
ICC
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±64
mA
mA
°C
IGND
TSTG
±128
−65 to +150
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
2.7
0
Max
Units
V
Supply Voltage
3.6
5.5
−32
64
VI
Input Voltage
V
IOH
IOL
TA
HIGH-Level Output Current
LOW-Level Output Current
mA
mA
°C
Free-Air Operating Temperature
−40
85
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0
10
ns/V
Note 4: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 5: IO Absolute Maximum Rating must be observed.
3
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DC Electrical Characteristics
VCC
T A = −40°C to +85°C
Symbol
Parameter
Units
Conditions
II = −18 mA
(V)
2.7
Min
Max
VIK
Input Clamp Diode Voltage
Input HIGH Voltage
−1.2
V
V
VIH
VIL
2.7–3.6
2.7–3.6
2.7–3.6
2.7
2.0
V
O ≤ 0.1V or
O ≥ VCC − 0.1V
Input LOW Voltage
0.8
V
VOH
Output HIGH Voltage
VCC − 0.2
2.4
V
V
I
I
I
I
I
I
I
I
OH = −100 µA
OH = −8 mA
OH = −32 mA
OL = 100 µA
OL = 24 mA
OL = 16 mA
OL = 32 mA
OL = 64 mA
3.0
2.0
V
VOL
Output LOW Voltage
2.7
0.2
0.5
V
2.7
V
3.0
0.4
V
3.0
0.5
V
3.0
0.55
V
II(HOLD)
II(OD)
II
Bushold Input Minimum Drive
75
−75
µA
µA
µA
µA
µA
µA
µA
µA
µA
VI = 0.8V
3.0
3.0
VI = 2.0V
Bushold Input Over-Drive
Current to Change State
Input Current
500
(Note 6)
−500
(Note 7)
3.6
3.6
10
±1
VI = 5.5V
Control Pins
Data Pins
VI = 0V or VCC
VI = 0V
−5
3.6
0
1
VI = VCC
IOFF
Power Off Leakage Current
Power up/down 3-STATE
Output Current
±100
0V ≤ VI or VO ≤ 5.5V
IPU/PD
VO = 0.5V to 3.0V
0–1.5V
±100
µA
VI = GND or VCC
IOZL
IOZH
IOZH
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
3.6
3.6
3.6
3.6
3.6
3.6
3.6
−5
5
µA
µA
V
V
V
O = 0.0V
O = 3.6V
+
10
µA
CC < VO ≤ 5.5V
ICCH
ICCL
ICCZ
0.19
5
mA
mA
mA
mA
Outputs HIGH
Outputs LOW
Power Supply Current
Power Supply Current
0.19
0.19
Outputs Disabled
ICCZ
+
Power Supply Current
VCC ≤ VO ≤ 5.5V,
Outputs Disabled
∆ICC
Increase in Power Supply Current
(Note 8)
3.6
0.2
mA
One Input at VCC − 0.6V
Other Inputs at VCC or GND
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics (Note 9)
VCC
T
A = 25°C
Conditions
Symbol
Parameter
Units
C
L = 50 pF, RL = 500Ω
(V)
3.3
3.3
Min
Typ
0.8
Max
VOLP
VOLV
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
V
V
(Note 10)
(Note 10)
−0.8
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
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4
AC Electrical Characteristics
T
A = −40°C to +85°C, CL = 50 pF, RL = 500 Ω
CC = 3.3 ± 0.3V VCC = 2.7V
Symbol
Parameter
V
Units
Min
150
1.3
1.3
1.5
1.5
1.3
1.3
1.3
1.3
1.7
1.7
2.1
2.1
2.4
2.4
1.0
1.7
3.3
3.3
Max
Min
Max
fMAX
CLKAB or CLKBA to B or A
Propagation Delay
150
1.3
1.3
1.5
1.5
1.3
1.3
1.3
1.3
1.7
1.7
2.4
2.4
1.6
1.6
1.0
1.7
3.3
3.3
MHz
ns
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tS
5.1
4.7
5.5
5.1
56
5.6
5.3
6.1
5.7
6.2
5.7
5.6
6.2
6.6
6.3
Data to Outputs
Propagation Delay
ns
ns
ns
ns
LEBA or LEAB to B or A
Propagation Delay
CLKBA or CLKAB to B or A
Output Enable Time
5.1
4.9
5.4
5.9
5.8
Output Disable Time
Setup Time
A before CLKAB
B before CLKBA
ns
A or B before LE, CLK HIGH
A or B before LE, CLK LOW
A or B after CLK
tH
Hold Time
ns
ns
A or B after LE
tW
Pulse Width
LE HIGH
CLK HIGH or LOW
tOSLH
tOSHL
Output to Output Skew (Note 11)
1.0
1.0
1.0
1.0
ns
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 12)
Symbol
CIN
CI/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
CC = 0V, VI = 0V or VCC
CC = 3.0V, VO = 0V or VCC
Typical
Units
pF
V
V
4
8
pF
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
5
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Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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