74LVTH273SJ [FAIRCHILD]
Low Voltage Octal D-Type Flip-Flop with Clear; 低电压八路D型触发器与Clear
| 型号： | 74LVTH273SJ |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage Octal D-Type Flip-Flop with Clear |
| 文件： | 总7页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1999
Revised March 2005
74LVTH273
Low Voltage Octal D-Type Flip-Flop with Clear
General Description
Features
The LVTH273 is a high-speed, low-power positive-edge-
triggered octal D-type flip-flop featuring separate D-type
inputs for each flip-flop. A buffered Clock (CP) and Clear
(CLR) are common to all flip-flops.
■ Input and output interface capability to systems at
5V VCC
■ Bushold on the data inputs eliminate the need for
external pull-up resistors to hold unused inputs
The state of each D-type input, one setup time before the
positive clock transition, is transferred to the corresponding
flip-flop’s output.
■ Outputs source/sink 32 mA/ 64 mA
■ Functionally compatible with the 74 series 273
■ Latch-up performance exceeds 500 mA
■ ESD performance:
The LVTH273 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
Human-body model 2000V
These octal flip-flops are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
Machine model 200V
interface to a 5V environment. The LVTH273 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Charged-device model 1000V
Ordering Code:
Package
Order Number
Package Description
Number
74LVTH273WM
74LVTH273SJ
74LVTH273MTC
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MTC20
MTC20
74LVTH273MTCX_NL
(Note 1)
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbols
IEEE/IEC
© 2005 Fairchild Semiconductor Corporation
DS500100
www.fairchildsemi.com
Connection Diagram
Pin Descriptions
Pin Names
Description
Data Inputs
D0–D7
CP
Clock Pulse Input
Clear
CLR
O0–O7
Outputs
Truth Table
Inputs
Outputs
Dn
H
L
CP
CLR
H
On
H
H
L
X
H or L
X
H
Oo
L
X
L
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
LOW-to-HIGH Transition
Previous O before HIGH-to-LOW of CP
O
o
o
Functional Description
The LVTH273 consists of eight positive-edge-triggered flip-flops with individual D-type inputs. The buffered Clock and Clear
are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP) transition. When the Clock is either HIGH or LOW, the D-input sig-
nal has no effect at the output. When the Clear (CLR) is LOW, all Outputs will be forced LOW.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 2)
Symbol
VCC
Parameter
Supply Voltage
Value
0.5 to 4.6
0.5 to 7.0
0.5 to 7.0
50
Conditions
Units
V
VI
DC Input Voltage
V
VO
IIK
IOK
IO
DC Output Voltage
Output in HIGH or LOW State (Note 3)
VI GND
V
DC Input Diode Current
DC Output Diode Current
DC Output Current
mA
mA
50
VO GND
64
VO VCC Output at HIGH State
VO VCC Output at LOW State
mA
128
ICC
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
64
mA
mA
C
IGND
TSTG
128
65 to 150
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
2.7
0
Max
3.6
5.5
32
Units
Supply Voltage
V
V
VI
Input Voltage
IOH
IOL
TA
HIGH Level Output Current
LOW Level Output Current
mA
mA
C
64
Free-Air Operating Temperature
40
0
85
t/ V
Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V
10
ns/V
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3: I Absolute Maximum Rating must be observed.
O
DC Electrical Characteristics
T
40 C to 85 C
A
V
(V)
CC
Symbol
Parameter
Units
Conditions
Min
Typ
Max
(Note 4)
V
Input Clamp Diode Voltage
Input HIGH Voltage
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
1.2
0.8
V
V
V
I
18 mA
0.1V or
IK
I
V
V
V
2.0
V
V
IH
IL
O
Input LOW Voltage
V
0.1V
A
O
CC
Output HIGH Voltage
V
0.2
I
I
I
I
I
I
I
I
100
OH
CC
OH
OH
OH
OL
OL
OL
OL
OL
2.4
2.0
V
8 mA
3.0
32 mA
V
Output LOW Voltage
2.7
0.2
0.5
100 A
OL
2.7
24 mA
16 mA
32 mA
64 mA
0.8V
3.0
0.4
V
3.0
0.5
3.0
0.55
I
Bushold Input Minimum Drive
3.0
75
75
V
V
I(HOLD)
I
I
A
A
2.0V
I
Bushold Input Over-Drive
Current to Change State
Input Current
3.0
500
500
(Note 5)
(Note 6)
I(OD)
I
3.6
3.6
10
1
A
A
V
V
V
V
5.5V
0V or V
0V
I
I
I
I
I
Control Pins
Data Pins
CC
5
A
3.6
1
A
V
CC
I
Power Off Leakage Current
Power Supply Current
Power Supply Current
0
100
0.19
5
A
0V V or V
5.5V
OFF
I
O
I
3.6
3.6
3.6
mA
mA
mA
Outputs HIGH
Outputs LOW
One Input at V
CCH
I
CCL
I
Increase in Power Supply Current
(Note 7)
0.2
0.6V
CC
CC
Other Inputs at V or GND
CC
Note 4: All typical values are at V
3.3V, T
25 C.
CC
A
3
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DC Electrical Characteristics (Continued)
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than V or GND.
CC
Dynamic Switching Characteristics (Note 8)
T
25 C
Typ
Conditions
A
V
(V)
CC
Symbol
Parameter
Units
C
50 pF, R
L
500
Min
Max
L
V
V
Quiet Output Maximum Dynamic V
3.3
3.3
0.8
0.8
V
V
(Note 9)
(Note 9)
OLP
OL
Quiet Output Minimum Dynamic V
OLV
OL
Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
40 C to 85 C
50 pF, R 500
A
C
L
L
Symbol
Parameter
Units
V
3.3V 0.3V
V
2.7V
CC
CC
Min
Typ
Max
Min
Max
(Note 10)
f
t
t
Maximum Clock Frequency
Propagation Delay
CP to O
150
1.7
1.9
150
1.7
1.9
MHz
ns
MAX
4.9
4.8
5.5
5.1
PLH
PHL
n
t
t
t
Propagation Delay CLR to O
Pulse Duration
1.6
3.3
2.3
2.3
0
4.8
1.6
3.3
2.7
2.7
0
5.4
ns
ns
PHL
W
n
Setup Time
Data HIGH or LOW before CP
CLR HIGH before CP
S
ns
ns
t
Hold Time
Data HIGH or LOW after CP
H
Note 10: All typical values are at V
3.3V, T
25 C.
CC
A
Capacitance (Note 11)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
Typical
Units
C
C
V
V
0V, V 0V or V
3
6
pF
pF
IN
CC
I
CC
3.0V, V
0V or V
CC
OUT
CC
O
Note 11: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883B, Method 3012.
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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