74VCX16838MTDX [FAIRCHILD]
Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs; 低电压16位可选择注册/缓冲器，具有3.6V容限输入和输出
| 型号： | 74VCX16838MTDX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs |
| 文件： | 总7页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1997
Revised July 2000
74VCX16838
Low Voltage 16-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs and Outputs
General Description
Features
■ Compatible with PC100 and PC133 DIMM module
The VCX16838 contains sixteen non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CP) sig-
nals. The device operates in a 16-bit word wide mode. All
outputs can be placed into 3-State through use of the OE
Pin. These devices are ideally suited for buffered or regis-
tered 168 pin and 200 pin SDRAM DIMM memory mod-
ules.
specifications
■ 1.65V–3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
■ tPD (CP to On)
3.0 ns max for 3.0V to 3.6V VCC
4.0 ns max for 2.3V to 2.7V VCC
8.0 ns max for 1.65V to 1.95V VCC
The 74VCX16838 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
■ Power-off high impedance inputs and outputs
■ Supports live insertion and withdrawal (Note 1)
The 74VCX16838 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
■ Static Drive (IOH/IOL
)
±24 mA @ 3.0V VCC
±18 mA @ 2.3V VCC
±6 mA @ 1.65V VCC
■ Uses patented noise/EMI reduction circuitry
■ Ideal for SDRAM DIMM modules
■ Latch-up performance exceeds 300 mA
■ ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX16838MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OE
Output Enable Input (Active LOW)
Inputs
I0–I15
O0–O15
CP
Outputs
Clock Pulse Input
Register Enable Input
REGE
© 2000 Fairchild Semiconductor Corporation
DS500034
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Connection Diagram
Truth Table
Inputs
Outputs
On
In
CP
↑
REGE
OE
L
H
H
L
H
L
H
L
↑
L
X
X
X
H
L
L
H
L
L
L
X
X
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Functional Description
The 74VCX16838 consists of sixteen selectable non-
inverting buffers or registers with word wide controls. Mode
functionality is selected through operation of the CP and
REGE pin as shown by the truth table. When REGE is held
at a logic “1” the device operates as a 16-bit register. Data
is transferred from In to On on the rising edge of the CP pin.
When the REGE pin is held at a logic “0” the device oper-
ates in a flow through mode and data propagates directly
from the I to the O outputs. All outputs can be 3-STATE by
holding the OE pin at a logic “1.”
Logic Diagram
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 4)
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to +4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO)
Operating
1.65V to 3.6V
1.2V to 3.6V
Outputs 3-STATE
−0.5V to +4.6V
−0.5V to VCC +0.5V
−50 mA
Data Retention Only
Input Voltage
Outputs Active (Note 3)
DC Input Diode Current (IIK) VI < 0V
−0.3V to +3.6V
Output Voltage (VO)
Output in Active States
Output in “OFF” State
Output Current in IOH/IOL
DC Output Diode Current (IOK
)
0V to VCC
V
V
O < 0V
−50 mA
+50 mA
0.0V to 3.6V
O > VCC
DC Output Source/Sink Current
(IOH/IOL
V
V
V
CC = 3.0V to 3.6V
CC = 2.3V to 2.7V
CC = 1.65V to 2.3V
±24 mA
±18 mA
)
±50 mA
DC VCC or GND Current per
Supply Pin (ICC or GND)
±6 mA
±100 mA
Free Air Operating Temperature (TA)
−40°C to +85°C
Storage Temperature Range (TSTG
)
−65°C to +150°C
Minimum Input Edge Rate (∆t/∆V)
V
IN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics (2.7V < V ≤ 3.6V)
CC
VCC
(V)
Symbol
Parameter
Conditions
Min
Max
Units
VIH
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
2.7–3.6
2.7–3.6
2.7–3.6
2.7
2.0
V
V
VIL
0.8
VOH
I
I
I
I
I
I
I
I
OH = −100 µA
OH = −12 mA
OH = −18 mA
OH = −24 mA
OL = 100 µA
OL = 12 mA
OL = 18 mA
OL = 24 mA
V
CC − 0.2
2.2
V
V
3.0
2.4
V
3.0
2.2
V
VOL
LOW Level Output Voltage
2.7–3.6
2.7
0.2
0.4
V
V
3.0
0.4
V
3.0
0.55
±5.0
V
II
Input Leakage Current
0 ≤ VI ≤ 3.6V
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
2.7–3.6
µA
IOZ
3-STATE Output Leakage
2.7–3.6
±10
µA
IOFF
ICC
Power-OFF Leakage Current
Quiescent Supply Current
0 ≤ (VI, VO) ≤ 3.6V
VI = VCC or GND
0
10
20
µA
µA
µA
µA
2.7–3.6
2.7–3.6
2.7–3.6
V
CC ≤ (VI, VO) ≤ 3.6V (Note 5)
IH = VCC −0.6V
±20
750
∆ICC
Increase in ICC per Input
V
Note 5: Outputs disabled or 3-STATE only.
3
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DC Electrical Characteristics (2.3V ≤ V ≤ 2.7V)
CC
VCC
(V)
Symbol
Parameter
Conditions
Min
Max
Units
VIH
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
2.3–2.7
2.3–2.7
2.3–2.7
2.3
1.6
V
V
VIL
0.7
VOH
I
I
I
I
I
I
I
OH = −100 µA
OH = −6 mA
OH = −12 mA
OH = −18 mA
OL = 100 µA
OL = 12 mA
OL = 18 mA
V
CC − 0.2
V
2.0
V
2.3
1.8
V
2.3
1.7
V
VOL
LOW Level Output Voltage
2.3–2.7
2.3
0.2
0.4
V
V
2.3
0.6
V
II
Input Leakage Current
0 ≤ VI ≤ 3.6V
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
2.3–2.7
±5.0
µA
IOZ
3-STATE Output Leakage
2.3–2.7
±10
µA
IOFF
ICC
Power-OFF Leakage Current
Quiescent Supply Current
0 ≤ (VI, VO) ≤ 3.6V
VI = VCC or GND
0
10
20
µA
µA
µA
2.3–2.7
2.3–2.7
VCC ≤ (VI, VO) ≤ 3.6V (Note 6)
±20
Note 6: Outputs disabled or 3-STATE only.
DC Electrical Characteristics (1.65V ≤ V < 2.3V)
CC
VCC
(V)
Symbol
Parameter
Conditions
Min
Max
Units
VIH
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
1.65 - 2.3 0.65 × VCC
1.65 - 2.3
V
V
VIL
0.35 × VCC
VOH
IOH = −100 µA
IOH = −6 mA
IOL = 100 µA
IOL = 6 mA
1.65 - 2.3 VCC − 0.2
V
1.65
1.65 - 2.3
1.65
1.25
V
VOL
LOW Level Output Voltage
0.2
0.3
V
V
II
Input Leakage Current
0 ≤ VI ≤ 3.6V
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
1.65 - 2.3
±5.0
µA
IOZ
3-STATE Output Leakage
1.65 - 2.3
±10
µA
IOFF
ICC
Power-OFF Leakage Current
Quiescent Supply Current
0 ≤ (VI, VO) ≤ 3.6V
VI = VCC or GND
0
10
20
µA
µA
µA
1.65 - 2.3
1.65 - 2.3
VCC ≤ (VI, VO) ≤ 3.6V (Note 7)
±20
Note 7: Outputs disabled or 3-STATE only.
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4
AC Electrical Characteristics (Note 8)
TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω
Symbol
Parameter
V
CC = 3.3V ± 0.3V CC = 2.5V ± 0.2V CC = 1.8V ± 0.15V
V
V
Units
Min
Max
Min
Max
Min
Max
fMAX
PHL, tPLH
Maximum Clock Frequency
250
200
100
MHz
ns
t
Prop Delay In to On
(REGE = 0)
0.8
2.5
3.0
1.0
3.5
4.0
1.5
7.0
8.0
tPHL, tPLH
Prop Delay CP to On
(REGE = 1)
0.8
1.0
1.5
ns
tPHL, tPLH
tPZL, tPZH
PLZ, tPHZ
Prop Delay REGE to On
Output Enable Time
Output Disable Time
Setup Time
0.8
0.8
0.8
1.0
0.7
1.5
3.0
3.5
3.5
1.0
1.0
1.0
1.0
0.7
1.5
4.0
4.7
3.9
1.5
1.5
1.5
2.5
1.0
4.0
8.0
9.4
7.0
ns
ns
ns
ns
ns
ns
t
tS
tH
Hold Time
tW
Pulse Width
tOSHL
tOSLH
Output to Output Skew
(Note 9)
0.5
0.5
0.75
ns
Note 8: For CL = 50PF, add approximately 300 ps to the AC maximum specification.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Extended AC Electrical Characteristics (Note 10)
T
A = −0°C to +85°C, RL = 500Ω VCC = 3.3V ± 0.3V
CL = 50 pF
Symbol
PHL, tPLH
tPHL, tPLH
PHL, tPLH
Parameter
Min
1.0
1.4
1.0
1.0
1.0
1.0
0.7
Max
2.8
3.3
3.3
3.8
3.8
Units
ns
t
Prop Delay In to On (REGE = 0)
Prop Delay CP to On (REGE = 1)
Prop Delay REGE to On
Output Enable Time
Output Disable Time
Setup Time
ns
t
ns
tPZL, tPZH
ns
tPLZ, tPHZ
ns
tS
tH
ns
Hold Time
ns
Note 10: This parameter is guaranteed by characterization but not tested.
Dynamic Switching Characteristics
T
A = +25°C
VCC
(V)
Symbol
VOLP
Parameter
Conditions
Units
Typical
0.25
0.6
Quiet Output Dynamic Peak VOL
C
C
C
L = 30 pF, VIH = VCC, VIL = 0V
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
V
V
V
0.8
VOLV
Quiet Output Dynamic Valley VOL
Quiet Output Dynamic Valley VOH
L = 30 pF, VIH = VCC, VIL = 0V
L = 30 pF, VIH = VCC, VIL = 0V
−0.25
−0.6
−0.8
1.5
VOHV
1.9
2.2
Capacitance
T
A = +25°C
Symbol
Parameter
Conditions
CC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC
Units
Typical
CIN
Input Capacitance
Output Capacitance
V
6
7
pF
pF
pF
COUT
CPD
VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V
VI = 0V or VCC, f = 10 MHz,
Power Dissipation Capacitance
20
V
CC = 1.8V, 2.5V or 3.3V
5
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AC Loading and Waveforms
TEST
SWITCH
tPLH, tPHL
Open
t
PZL, tPLZ
6V at VCC = 3.3 ± 0.3V;
VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V ± 0.15V
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. Propagation Delay, Pulse Width and trec Waveforms
FIGURE 5. Setup Time, Hold Time and Recovery Time for Low Voltage Logic
VCC
Symbol
3.3V ± 0.3V
1.5V
2.5V ± 0.2V
VCC/2
1.8V ± 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
VCC/2
VCC/2
V
OL +0.3V
V
OL +0.15V
V
OL +0.15V
VY
V
OH −0.3V
V
OH −0.15V
VOH −0.15V
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6
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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