74VCXH162373MTX [FAIRCHILD]
Low Voltage 16-Bit Transparent Latch with Bushold and 26ヘ Series Resistors in Outputs; 低电压16位透明锁存器与Bushold和26ヘ串联电阻的输出
| 型号： | 74VCXH162373MTX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit Transparent Latch with Bushold and 26ヘ Series Resistors in Outputs |
| 文件： | 总7页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2000
Revised March 2000
74VCXH162373
Low Voltage 16-Bit Transparent Latch with Bushold
and 26Ω Series Resistors in Outputs
General Description
Features
■ 1.65V–3.6V VCC supply operation
The VCXH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
■ 3.6V tolerant control inputs and outputs
■ Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
■ 26Ω series resistors in outputs
■ tPD (In to On)
3.3 ns max for 3.0V to 3.6V VCC
4.5 ns max for 2.3V to 2.7V VCC
9.0 ns max for 1.65V to 1.95V VCC
The VCXH162373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The VCXH162373 is also designed with 26Ω series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address driver, clock drivers and
bus transceivers/transmitters.
■ Static Drive (IOH/IOL
)
±12 mA @ 3.0V VCC
±8 mA @ 2.3V VCC
±3 mA @ 1.65V VCC
The 74VCXH162373 is designed for low voltage (1.65V to
3.6V) VCC applications with output compatibility up to 3.6V.
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 300 mA
■ ESD performance:
The 74VCXH162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Human body model > 2000V
Machine model > 200V
Ordering Code:
Package
Ordering Number
Number
Package Description
74VCXH162373MTD
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
MTD48
MTD48
74VCXH162373MTX
(Note 1)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: Use this Order Number to receive devices in Tape and Reel.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
Latch Enable Input
Bushold Inputs
LEn
I0–I15
O0–O15
Outputs
© 2000 Fairchild Semiconductor Corporation
DS500227
www.fairchildsemi.com
Connection Diagram
Truth Tables
Inputs
OE1
Outputs
LE1
I0–I7
O0–O7
X
H
H
L
H
L
L
L
X
L
Z
L
H
X
H
O0
Inputs
OE2
Outputs
O8–O15
LE2
I8–I15
X
H
H
L
H
L
L
L
X
L
Z
L
H
X
H
O0
H
L
= HIGH Voltage Level
= LOW Voltage Level
X
Z
O
= Immaterial (HIGH or LOW, control inputs may not float)
= High Impedance
= Previous O before HIGH-to-LOW of Latch Enable
0
0
Functional Description
The 74VCXH162373 contains sixteen edge D-type latches
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
its I input changes. When LEn is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition on LEn. The 3-
STATE outputs are controlled by the Output Enable (OEn)
input. When OEn is LOW the standard outputs are in the 2-
state mode. When OEn is HIGH, the standard outputs are
the In enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time
in the high impedance mode but this does not interfere with
entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 4)
Supply Voltage (VCC
)
−0.5V to +4.6V
DC Input Voltage (VI)
OEn, LEn
Power Supply
−0.5V to 4.6V
Operating
1.65V to 3.6V
1.2V to 3.6V
−0.3V to VCC
I0 – I15
−0.5V to VCC + 0.5V
Data Retention Only
Input Voltage
Output Voltage (VO)
Outputs 3-STATED
Outputs Active (Note 3)
DC Input Diode Current (IIK
VI < 0V
−0.5V to +4.6V
Output Voltage (VO)
Output in Active States
Output in “OFF” State
Output Current in IOH/IOL
−0.5V to VCC +0.5V
0V to VCC
)
0.0V to 3.6V
−50 mA
DC Output Diode Current (IOK
)
V
V
V
CC = 3.0V to 3.6V
CC = 2.3V to 2.7V
CC = 1.65V to 2.3V
±12 mA
±8 mA
VO < 0V
−50 mA
+50 mA
VO > VCC
±3 mA
DC Output Source/Sink Current
(IOH/IOL
Free Air Operating Temperature (TA)
−40°C to +85°C
)
±50 mA
Minimum Input Edge Rate (∆t/∆V)
DC VCC or GND Current per
Supply Pin (ICC or GND)
V
IN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
±100 mA
Storage Temperature Range (TSTG
)
−65°C to +150°C
Note 3: I Absolute Maximum Rating must be observed.
O
Note 4: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics (2.7V < V ≤ 3.6V)
CC
V
CC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
2.7–3.6
2.7–3.6
2.7–3.6
2.7
V
V
V
HIGH Level Input Voltage
2.0
V
V
IH
LOW Level Input Voltage
HIGH Level Output Voltage
0.8
IL
I
I
I
I
I
I
I
I
= −100 µA
V − 0.2
CC
V
OH
OH
OH
OH
OH
OL
OL
OL
OL
= −6 mA
= −8 mA
= −12 mA
= 100 µA
= 6 mA
2.2
2.4
2.2
V
3.0
V
3.0
V
V
LOW Level Output Voltage
2.7–3.6
2.7
0.2
0.4
V
OL
V
= 8 mA
3.0
0.55
0.8
V
= 12 mA
3.0
V
I
I
I
I
Input Leakage Current
Control Pins
Data Pins
0 ≤ V ≤ 3.6V
2.7–3.6
2.7–3.6
3.0
±5.0
±5.0
µA
µA
I
I
V = V or GND
I
CC
Bushold Input Minimum
Drive Hold Current
V
V
= 0.8V
75
−75
450
−450
I(HOLD)
I(OD)
OZ
IN
IN
µA
µA
µA
= 2.0V
3.0
Bushold Input Over-Drive
Current to Change State
3-STATE Output Leakage
(Note 5)
(Note 6)
3.6
3.6
0 ≤ V ≤ 3.6V
O
2.7–3.6
±10
V = V or V
IL
I
IH
I
I
Power-OFF Leakage Current
Quiescent Supply Current
0 ≤ (V ) ≤ 3.6V
0
10
20
µA
µA
µA
µA
OFF
CC
O
V = V or GND
2.7–3.6
2.7–3.6
2.7–3.6
I
CC
V
V
≤ (V ) ≤ 3.6V (Note 7)
±20
750
CC
O
∆I
Increase in I per Input
= V −0.6V
IH CC
CC
CC
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: Outputs disabled or 3-STATE only.
3
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DC Electrical Characteristics (2.3V ≤ V ≤ 2.7V)
CC
V
(V)
CC
Symbol
Parameter
Conditions
Min
Max
Units
V
V
V
HIGH Level Input Voltage
2.3 − 2.7
2.3 − 2.7
2.3 − 2.7
2.3
1.6
V
V
IH
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
IL
I
= −100 µA
V − 0.2
CC
V
OH
OH
I
= −4 mA
= −6 mA
= −8 mA
= 100 µA
= 6 mA
2.0
1.8
1.7
V
OH
I
2.3
V
OH
I
2.3
V
OH
V
LOW Level Output Voltage
Input Leakage Current
I
2.3 − 2.7
2.3
0.2
0.4
V
OL
OL
I
V
OL
I
= 8 mA
2.3
0.6
V
OL
I
Control Pins
Data Pins
0 ≤ V ≤ 3.6V
2.3 − 2.7
2.3 − 2.7
2.3
±5.0
±5.0
µA
µA
I
I
V = V or GND
I
CC
I
Bushold Input Minimum
Drive Hold Current
V
V
= 0.7V
45
−45
300
−300
I(HOLD)
IN
IN
µA
µA
µA
= 1.6V
2.3
I
Bushold Input Over-Drive
Current to Change State
3-STATE Output Leakage
(Note 8)
(Note 9)
2.7
I(OD)
2.7
I
0 ≤ V ≤ 3.6V
O
OZ
2.3 − 2.7
±10
V = V or V
IL
I
IH
I
Power-OFF Leakage Current
Quiescent Supply Current
0 ≤ (V ) ≤ 3.6V
0
10
20
µA
µA
µA
OFF
O
I
V = V or GND
2.3 − 2.7
2.3 − 2.7
CC
I
CC
V
≤ (V ) ≤ 3.6V (Note 10)
±20
CC
O
Note 8: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 9: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 10: Outputs disabled or 3-STATE only.
DC Electrical Characteristics (1.65V ≤ V < 2.3V)
CC
V
(V)
CC
Symbol
Parameter
Conditions
Min
Max
Units
V
V
V
HIGH Level Input Voltage
1.65 - 2.3 0.65 × V
V
V
IH
CC
LOW Level Input Voltage
HIGH Level Output Voltage
1.65 - 2.3
0.35 × V
IL
CC
I
= −100 µA
1.65 - 2.3
1.65
V − 0.2
CC
V
OH
OH
I
= −3 mA
= 100 µA
= 3 mA
1.25
V
OH
V
LOW Level Output Voltage
Input Leakage Current
I
1.65 - 2.3
1.65
0.2
0.3
V
OL
OL
I
V
OL
I
Control Pins
Data Pins
0 ≤ V ≤ 3.6V
1.65 - 2.3
1.65 - 2.3
1.65
±5.0
±5.0
µA
µA
I
I
V = V or GND
I
CC
I
Bushold Input Minimum
Drive Hold Current
V
V
= 0.57V
25
−25
200
−200
I(HOLD)
IN
IN
µA
µA
µA
= 1.07V
1.65
I
Bushold Input Over-Drive
Current to Change State
3-STATE Output Leakage
(Note 11)
(Note 12)
1.95
I(OD)
1.95
I
0 ≤ V ≤ 3.6V
O
OZ
1.65 - 2.3
±10
V = V or V
IL
I
IH
I
Power-OFF Leakage Current
Quiescent Supply Current
0 ≤ (V ) ≤ 3.6V
0
10
20
µA
µA
µA
OFF
O
I
V = V or GND
1.65 - 2.3
1.65 − 2.3
CC
I
CC
V
≤ (V ) ≤ 3.6V (Note 13)
±20
CC
O
Note 11: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 12: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 13: Outputs disabled or 3-STATE only.
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4
AC Electrical Characteristics (Note 14)
T
= −40°C to +85°C, C = 30 pF, R = 500Ω
A
L
L
Symbol
Parameter
V
= 3.3V ± 0.3V
V
= 2.5V ± 0.2V
V
= 1.8V ± 0.15V
Units
CC
CC
CC
Min
1.5
1.5
1.5
1.5
2.5
1.0
4.0
Min
0.8
0.8
0.8
0.8
1.5
1.0
1.5
Max
3.3
3.6
3.9
4.0
Min
1.0
1.0
1.0
1.0
1.5
1.0
1.5
Max
4.5
4.9
5.4
4.4
Max
9.0
9.8
9.8
7.9
t
t
t
t
t
t
t
t
t
, t
Prop Delay I to O
n
ns
ns
ns
ns
ns
ns
ns
PHL PLH
n
, t
Prop Delay LE to O
n
PHL PLH
, t
Output Enable Time
Output Disable Time
Setup Time
PZL PZH
, t
PLZ PHZ
S
Hold Time
H
Pulse Width
W
Output to Output Skew
(Note 15)
OSHL
OSLH
0.5
0.5
0.75
ns
Note 14: For C = 50 F, add approximately 300 ps to the AC maximum specification.
L
P
Note 15: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
).
OSLH
OSHL
Dynamic Switching Characteristics
T
= +25°C
V
(V)
A
CC
Symbol
Parameter
Conditions
= 30 pF, V = V , V = 0V
Units
Typical
0.15
V
V
V
Quiet Output Dynamic Peak V
C
C
C
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
OLP
OL
L
L
L
IH
CC
IL
0.25
V
0.35
Quiet Output Dynamic Valley V
Quiet Output Dynamic Valley V
= 30 pF, V = V , V = 0V
−0.15
−0.25
−0.35
1.55
OLV
OL
IH
CC
IL
V
V
= 30 pF, V = V , V = 0V
OHV
OH
IH
CC
IL
2.05
2.65
Capacitance
T
= +25°C
A
Symbol
Parameter
Conditions
= 1.8V, 2.5V or 3.3V, V = 0V or V
CC
Units
Typical
C
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
V
6
7
pF
pF
IN
CC
I
C
C
V = 0V or V , V = 1.8V, 2.5V or 3.3V
I CC CC
OUT
PD
V = 0V or V , f = 10 MHz,
I
CC
20
pF
V
= 1.8V, 2.5V or 3.3V
CC
5
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AC Loading and Waveforms
TEST
SWITCH
Open
t
PLH, tPHL
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V;
VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V ± 0.15V
GND
tPZH, tPHZ
FIGURE 1. AC Test Circuit
FIGURE 3. 3-STATE Output HIGH Enable and
Disable Times for Low Voltage Logic
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
tREC Waveforms
VCC
Symbol
3.3V ± 0.3V
1.5V
2.5V ± 0.2V
VCC/2
1.8V ± 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
VCC/2
VCC/2
V
OL +0.3V
V
OL +0.15V
V
OL +0.15V
VY
V
OH −0.3V
V
OH −0.15V
VOH −0.15V
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6
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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