74VHC4053MTCX [FAIRCHILD]
2-Channel Analog Multiplexer ; 2通道模拟多路复用器\n
| 型号： | 74VHC4053MTCX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 2-Channel Analog Multiplexer
|
| 文件： | 总11页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1994
Revised April 1999
74VHC4051 • 74VHC4052 • 74VHC4053
8-Channel Analog Multiplexer • Dual 4-Channel Analog
Multiplexer • Triple 2-Channel Analog Multiplexer
multiplexers. The binary code placed on the A, and B
select lines determine which switch in each 4 channel sec-
tion is “on”, connecting one of the four inputs in each sec-
tion to its common output. This enables the implementation
General Description
These multiplexers are digitally controlled analog switches
implemented in advanced silicon-gate CMOS technology.
These switches have low “on” resistance and low “off” leak-
of a 4-channel differential multiplexer.
ages. They are bidirectional switches, thus any analog
VHC4053: This device contains 6 switches whose outputs
input may be used as an output and vice-versa. Also these
are connected together in pairs, thus implementing a triple
switches contain linearization circuitry which lowers the
2 channel multiplexer, or the equivalent of 3 single-pole-
“on” resistance and increases switch linearity. These
double throw configurations. Each of the A, B, or C select
devices allow control of up to ±6V (peak) analog signals
lines independently controls one pair of switches, selecting
with digital control signals of 0 to 6V. Three supply pins are
one of the two switches to be “on”.
provided for VCC, ground, and VEE. This enables the con-
nection of 0–5V logic signals when VCC = 5V and an analog
Features
input range of ±5V when VEE = 5V. All three devices also
■ Wide analog input voltage range: ±6V
have an inhibit control which when high will disable all
■ Low “on” resistance: 50 typ. (VCC–VEE = 4.5V)
30 typ. (VCC–VEE = 9V)
switches to their off state. All analog inputs and outputs
and digital inputs are protected from electrostatic damage
by diodes to VCC and ground.
■ Logic level translation to enable 5V logic with ±5V ana-
log signals
VHC4051: This device connects together the outputs of 8
switches, thus achieving an 8 channel Multiplexer. The
binary code placed on the A, B, and C select lines deter-
mines which one of the eight switches is “on”, and con-
nects one of the eight inputs to the common output.
■ Low quiescent current: 80 µA maximum
■ Matched switch characteristic
■ Pin and function compatible with the 74HC4051/ 4052/
4053
VHC4052: This device connects together the outputs of 4
switches in two sets, thus achieving a pair of 4-channel
Ordering Code:
Order Number Package Number
Package Description
74VHC4051M
74VHC4051WM
74VHC4051MTC
74VHC4051N
M16A
M16B
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74VHC4052M
74VHC4052WM
74VHC4052MTC
74VHC4052N
M16A
M16B
MTC16
N16E
74VHC4053M
74VHC4053WM
74VHC4053MTC
74VHC4053N
M16A
M16B
MTC16
N16E
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation
DS011674.prf
www.fairchildsemi.com
Connection Diagrams
Truth Tables
4051
Input
“ON”
Channel
None
Y0
INH
H
L
C
X
L
B
X
L
A
X
L
L
L
L
H
L
Y1
L
L
H
H
L
Y2
L
L
H
L
Y3
L
H
H
H
H
Y4
L
L
H
L
Y5
L
H
H
Y6
Top View
L
H
Y7
4052
Inputs
“ON” Channels
INH
H
L
B
X
L
A
X
None
0X
Y
None
0Y
X
L
L
L
H
L
1X
1Y
L
H
H
2X
2Y
L
H
3X
3Y
4053
Top View
Input
“ON” Channels
INH
C
X
L
B
A
C
B
None
BX
BX
BY
BY
BX
BX
BY
BY
A
None
AX
AY
H
L
L
L
L
L
L
L
L
X
L
X
L
None
CX
CX
CX
CX
CY
CY
CY
CY
L
L
H
L
L
H
H
L
AX
AY
L
H
L
H
H
H
H
AX
AY
L
H
L
H
H
AX
AY
H
Top View
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2
Logic Diagrams
74VHC4051
74VHC4052
74VHC4053
3
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Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
Supply Voltage (VEE
Control Input Voltage (VIN
Switch I/O Voltage (VIO
Clamp Diode Current (IIK, IOK
Output Current, per pin (IOUT
)
−0.5 to +7.5V
+0.5 to −7.5V
−1.5 to VCC+1.5V
EE−0.5 to VCC+0.5V
±20 mA
Min
Max Units
)
Supply Voltage (VCC
Supply Voltage (VEE
DC Input or Output Voltage
(VIN, VOUT
)
2
0
0
6
V
V
V
)
)
−6
)
V
VCC
)
)
)
±25 mA
Operating Temperature Range
VCC or GND Current, per pin (ICC
Storage Temperature Range
)
±50 mA
(TA)
−40
+85
°C
Input Rise or Fall Times
(tr, tf)
(TSTG
)
−65°C to +150°C
Power Dissipation (PD)
(Note 3)
V
V
V
CC = 2.0V
CC = 4.5V
CC = 6.0V
1000
500
ns
ns
ns
600 mW
500 mW
S.O. Package only
Lead Temperature (TL)
(Soldering 10 seconds)
400
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
260°C
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
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4
DC Electrical Characteristics (Note 4)
T
= 25°C T = −40 to 85°C
A
A
V
V
CC
Symbol
Parameter
Conditions
Units
EE
Typ
Guaranteed Limits
V
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
4.5V
4.5V
6.0V
2.0V
4.5V
4.5V
6.0V
4.5V
4.5V
6.0V
1.5
1.5
3.15
4.2
V
V
IH
IL
3.15
4.2
0.5
1.35
1.8
160
120
100
230
110
90
V
V
Maximum LOW Level
Input Voltage
0.5
V
1.35
1.8
V
V
R
Maximum “ON” Resistance
(Note 5)
V
V
= V , I = 2.0 mA
GND
−4.5V
−6.0V
GND
40
30
20
100
40
20
15
10
5
200
150
125
280
140
120
100
25
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
µA
ON
INH
IL
S
= V to V
EE
IS
CC
(Figure 1)
V
V
= V , I = 2.0 mA
IL S
INH
= V or V
EE
GND
IS
CC
(Figure 1)
−4.5V
−6.0V
GND
80
R
Maximum “ON” Resistance
Matching
V
V
= V
IL
20
ON
INH
= V to GND
−4.5V
−6.0V
10
15
IS
CC
5
10
12
I
I
I
Maximum Control
Input Current
V
V
V
= V or GND
±.05
±0.5
N
IN
CC
= 2 − 6V
CC
Maximum Quiescent
Supply Current
= V or GND
GND
−6.0V
GND
6.0V
6.0V
6.0V
6.0V
4
8
40
80
µA
µA
nA
nA
CC
IZ
IN
CC
I
= 0 µA
OUT
Maximum Switch “OFF”
Leakage Current
(Switch Input)
V
= V or V
EE
±60
±300
±500
OS
CC
V
V
V
V
= V or V
CC
−6.0V
±100
IS
EE
= V (Figure 2)
INH
IH
I
Maximum Switch “ON”
= V to V
GND
6.0V
6.0V
±0.1
±0.2
±1.0
±2.0
µA
µA
IZ
IS
CC
EE
EE
EE
Leakage Current
VHC4051
= V
−6.0V
INH
IL
(Figure 3)
V
V
= V to V
GND
6.0V
6.0V
±0.050
±0.1
±0.5
±1.0
µA
µA
IS
CC
VHC4052
VHC4053
VHC4051
VHC4052
VHC4053
= V
−6.0V
INH
IL
(Figure 3)
V
V
= V to V
GND
6.0V
6.0V
±0.05
±0.5
±0.5
±0.5
µA
µA
IS
CC
= V
−6.0V
INH
IL
(Figure 3)
I
Maximum Switch
“OFF” Leakage
V
V
V
V
V
V
V
V
V
= V or V
GND
6.0V
6.0V
±0.1
±0.2
±1.0
±2.0
µA
µA
IZ
OS
CC
EE
EE
EE
= V or V
−6.0V
IS
EE
CC
Current (Common Pin)
= V
IH
INH
OS
= V or V
GND
6.0V
6.0V
±0.05
±0.1
±0.5
±1.0
µA
µA
CC
= V or V
−6.0V
IS
EE
CC
= V
INH
OS
IH
= V or V
GND
6.0V
6.0V
±0.05
±0.05
±0.5
±0.5
µA
µA
CC
= V or V
CC
−6.0V
IS
EE
= V
INH
IH
Note 4: For a power supply of 5V ±10% the worst case on resistances (R ) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing
ON
with this supply. Worst case V and V occur at V = 5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current occur
IH
IL
CC
IH
for CMOS at the higher voltage and so the 5.5V values should be used.
Note 5: At supply voltages (V –V ) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that
CC
EE
these devices be used to transmit digital only when using these supply voltages.
Note 6: Adjust 0 dB for f = 1 kHz (Null R1/R Attenuation).
ON
5
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AC Electrical Characteristics
V
CC = 2.0V − 6.0V, VEE = 0V − 6V, C = 50 pF (unless otherwise specified)
L
T
=25°C
T =−40 to 85°C
A
A
V
V
CC
Symbol
, t
Parameter
Conditions
Units
EE
Typ
Guaranteed Limits
t
t
t
f
Maximum Propagation Delay
Switch In to Out
GND
GND
3.3V
4.5V
25
5
35
40
15
ns
ns
PHL PLH
12
8
−4.5V 4.5V
−6.0V 6.0V
4
12
11
ns
3
7
ns
, t
Maximum Switch Turn “ON”
Delay
R
= 1 kΩ
GND
GND
3.3V
4.5V
92
200
69
250
87
58
51
210
73
46
41
ns
PZL PZH
L
ns
−4.5V 4.5V
−6.0V 6.0V
16
15
65
28
18
16
30
35
46
ns
41
ns
, t
Maximum Switch Turn “OFF”
Delay
GND
GND
3.3V
4.5V
170
58
ns
PHZ PLZ
ns
−4.5V 4.5V
−6.0V 6.0V
37
ns
32
ns
Minimum Switch
GND
4.5V
MHz
MHz
MAX
Frequency Response
−4.5V 4.5V
20 log (V /V ) = 3 dB
I
O
Control to Switch
R
= 600Ω,
V
V
= 4 V
= 8 V
0V
4.5V
1080
250
mV
mV
L
IS
IS
PP
PP
Feedthrough Noise
f = 1 MHz,
−4.5V 4.5V
C
R
= 50 pF
= 600Ω,
L
L
Crosstalk between
any Two Switches
Switch OFF Signal
Feedthrough
V
V
V
V
= 4 V
= 8 V
= 4 V
= 8 V
0V
−4.5V 4.5V
0V 4.5V
−4.5V 4.5V
4.5
−52
−50
−42
−44
dB
dB
dB
dB
IS
IS
IS
IS
PP
PP
PP
PP
f = 1 MHz
= 600Ω,
R
L
f = 1 MHz,
= V
Isolation
V
CTL
IL
THD
Sinewave Harmonic
Distortion
R
C
= 10 kΩ,
= 50 pF,
V
V
= 4 V
= 8 V
0V
4.5V
0.013
0.008
%
%
L
L
IS
IS
PP
−4.5V 4.5V
PP
f = 1 kHz
C
C
Maximum Control
Input Capacitance
Maximum Switch
Input Capacitance
5
10
10
pF
pF
IN
Input
15
90
45
30
5
IN
4051 Common
4052 Common
4053 Common
C
Maximum Feedthrough
Capacitance
pF
IN
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6
AC Test Circuits and Switching Time Waveforms
FIGURE 1. “ON” Resistance
FIGURE 2. “OFF” Channel Leakage Current
FIGURE 3. “ON” Channel Leakage Current
FIGURE 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output
FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output
FIGURE 6. tPZH, tPHZ Propagation Delay TIme Control to Signal Output
FIGURE 7. Crosstalk: Control Input to Signal Output
7
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AC Test Circuits and Switching Time Waveforms (Continued)
FIGURE 8. Crosstalk Between Any Two Switches
Typical Performance Characteristics
Typical “On” Resistance
vs Input Voltage
V
=−V
EE
CC
Special Considerations
In certain applications the external load-resistor current may include both VCC and signal line components. To avoid draw-
ing VCC current when switch current flows into the analog switch pins, the voltage drop across the switch must not exceed
1.2V (calculated from the ON resistance).
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8
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M16B
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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