74VHC4316MTC [FAIRCHILD]
Quad Analog Switch with Level Translator; 四路模拟开关与电平转换器
| 型号： | 74VHC4316MTC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad Analog Switch with Level Translator |
| 文件： | 总9页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1994
Revised April 1999
74VHC4316
Quad Analog Switch with Level Translator
inputs are protected from electrostatic damage by diodes
to VCC and ground.
General Description
These devices are digitally controlled analog switches
implemented in advanced silicon-gate CMOS technology.
These switches have low “on” resistance and low “off” leak-
ages. They are bidirectional switches, thus any analog
input may be used as an output and vice-versa. Three sup-
ply pins are provided on the 4316 to implement a level
translator which enables this circuit to operate with 0V–6V
logic levels and up to ±6V analog switch levels. The 4316
also has a common enable input in addition to each
switch's control which when HIGH will disable all switches
to their off state. All analog inputs and outputs and digital
Features
■ Typical switch enable time: 20 ns
■ Wide analog input voltage range: ±6V
■ Low “on” resistance: 50 typ. (VCC−VEE = 4.5V)
30 typ. (VCC−VEE = 9V)
■ Low quiescent current: 80 µA maximum (74VHC)
■ Matched switch characteristics
■ Individual switch controls plus a common enable
■ Pin functional compatible with 74HC4316
Ordering Code:
Order Number Package Number
Package Description
74VHC4316M
74VHC4316WM
74VHC4316MTC
74VHC4316N
M16A
M16B
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Truth Table
Connection Diagram
Inputs
Switch
I/O–O/I
“OFF”
“OFF”
“ON”
E
H
L
CTL
X
L
L
H
Top View
Logic Diagram
© 1999 Fairchild Semiconductor Corporation
DS011678.prf
www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
Supply Voltage (VEE
DC Control Input Voltage (VIN
DC Switch I/O Voltage (VIO
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to +7.5V
+0.5 to −7.5V
−1.5 to VCC+1.5V
EE−0.5 to VCC+0.5V
±20 mA
Min
Max Units
)
Supply Voltage (VCC
Supply Voltage (VEE
DC Input or Output Voltage
(VIN, VOUT
)
2
0
0
6
V
V
V
)
)
−6
)
V
VCC
)
)
)
±25 mA
Operating Temperature Range (TA) −40
+85
°C
)
±50 mA
Input Rise or Fall Times
Storage Temperature Range (TSTG
Power Dissipation (PD) (Note 3)
S.O. Package only
)
−65°C to +150°C
600 mW
(tr, tf)
V
V
V
V
CC = 2.0V
CC = 4.5V
CC = 6.0V
CC = 12.0V
1000
500
400
250
ns
ns
ns
ns
500 mW
Lead Temperature (TL)
(Soldering 10 seconds)
260°C
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
T
= 25°C
T = −40°C to +85°C
A
A
V
V
CC
Symbol
Parameter
Conditions
Units
EE
Typ
Guaranteed Limits
V
V
Minimum HIGH
Level Input
Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
4.5V
4.5V
6.0V
1.5
1.5
IH
3.15
4.2
0.5
1.35
1.8
170
85
3.15
4.2
V
Maximum LOW
Level Input
Voltage
0.5
IL
1.35
1.8
V
R
Minimum “ON”
Resistance
(Note 5)
V
= V ,
IH
GND
−4.5V
−6.0V
100
40
200
105
85
Ω
ON
CTL
I
= 2.0 mA
S
V
= V to V
EE
30
70
IS
CC
(Figure 1)
= V
V
,
IH
GND
GND
−4.5V
−6.0V
GND
−4.5V
−6.0V
GND
2.0V
4.5V
4.5V
6.0V
4.5V
4.5V
6.0V
6.0V
100
40
50
20
10
5
180
80
215
100
75
CTL
I
= 2.0 mA
S
V
= V or V
60
IS
CC
EE
(Figure 1)
40
60
R
Maximum “ON”
Resistance
V
V
= V
IH
15
20
ON
CTL
= V to V
10
15
Ω
IS
CC
EE
Matching
5
10
15
I
I
Maximum Control
Input Current
Maximum Switch
“OFF” Leakage
Current
V
= V or GND
±0.1
±1.0
µA
IN
IN
CC
V
V
V
= V or V
CC EE
IZ
OS
= V or V
CC
GND
6.0V
6.0V
±30
±50
±300
±500
nA
IS
EE
= V
−6.0V
CTL
IL
(Figure 2)
I
I
Maximum Switch
“ON” Leakage
Current
V
V
V
= V to V
CC EE
IZ
IS
= V
,
IH
GND
6.0V
6.0V
±20
±30
±75
nA
CTL
= OPEN
−6.0V
±150
OS
(Figure 3)
Maximum Quiescent
Supply Current
V
= V or GND
GND
6.0V
6.0V
1.0
4.0
10
40
µA
CC
IN
CC
I
= 0 µA
−6.0V
OUT
Note 4: For a power supply of 5V ±10% the worst case on resistances (R ) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing
ON
with this supply. Worst case V and V occur at V = 5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current occurs
IH
IL
CC
IH
for CMOS at the higher voltage and so the 5.5V values should be used.
Note 5: At supply voltages (V –V ) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that
CC
EE
these devices be used to transmit digital only when using these supply voltages.
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2
AC Electrical Characteristics
V
CC = 2.0V − 6.0V, VEE = 0V − 6V, C = 50 pF unless otherwise specified
L
T
=+25°C
T =−40°C to +85°C
A
A
V
V
CC
Symbol
, t
Parameter
Conditions
Units
EE
Typ
Guaranteed Limits
t
Maximum Propagation
Delay Switch In to
Out
GND
GND
−4.5V
−6.0V
GND
GND
−4.5V
−6.0V
GND
GND
−4.5V
−6.0V
GND
GND
−4.5V
−6.0V
GND
GND
−4.5V
−6.0V
0V
3.3V
4.5V
4.5V
6.0V
3.3V
4.5V
4.5V
6.0V
3.3V
4.5V
4.5V
6.0V
3.3V
4.5V
4.5V
6.0V
3.3V
4.5V
4.5V
6.0V
4.5
15
5
30
37
13
PHL PLH
10
8
ns
4
12
3
7
11
t
, t
Maximum Switch Turn
“ON” Delay
R
= 1 kΩ
25
20
15
14
35
25
20
20
27
20
19
18
42
28
23
21
40
100
97
35
32
30
120
43
PZL PZH
L
ns
ns
ns
ns
(Control)
39
37
t
, t
Maximum Switch Turn
“OFF” Delay
R
= 1 kΩ
145
50
180
63
PHZ PLZ
L
(Control)
44
55
44
55
t
, t
Maximum Switch
Turn “ON” Delay
(Enable)
120
41
150
52
PZL PZH
38
48
36
45
t
, t
Maximum Switch
Turn “OFF” Delay
(Enable)
155
53
190
67
PLZ PHZ
47
59
47
59
Minimum Frequency
R
= 600Ω, V = 2V
IS PP
L
Response (Figure 7)
at (V –V /2)
−4.5V
4.5V
MHz
mV
dB
CC
EE
20 log (V /V )= −3 dB
(Note 6)(Note 7)
OS IS
Control to Switch
Feedthrough Noise
(Figure 8)
R
C
= 600Ω, f = 1 MHz
0V
4.5V
4.5V
100
250
L
L
= 50 pF
−4.5V
(Note 7)(Note 8)
Crosstalk Between
any Two Switches
(Figure 9)
R
= 600Ω, f = 1 MHz
0V
4.5V
4.5V
−52
−50
L
−4.5V
Switch OFF Signal
Feedthrough
R
= 600Ω, f = 1 MHz
L
V
= V
0V
4.5V
4.5V
−42
−44
dB
CTL
IL
Isolation
−4.5V
(Figure 10)
(Note 7)(Note 8)
= 10 KΩ, C = 50 pF,
THD
Sinewave Harmonic
Distortion
R
L
L
f = 1 KHz
%
(Figure 11)
V
V
= 4 V
= 8 V
0V
4.5V
4.5V
0.013
0.008
5
IS
PP
−4.5V
IS
PP
C
C
C
C
Maximum Control
Input Capacitance
Maximum Switch
Input Capacitance
Maximum Feedthrough
Capacitance
pF
pF
pF
pF
IN
IN
IN
PD
35
0.5
15
V
= GND
CTL
Power Dissipation
Capacitance
Note 6: Adjust 0 dBm for f = 1 kHz (Null R /Ron Attenuation).
L
Note 7: V is centered at V –V /2.
IS
CC
EE
Note 8: Adjust for 0 dBm.
3
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AC Test Circuits and Switching Time Waveforms
FIGURE 1. “ON” Resistance
FIGURE 2. “OFF” Channel Leakage Current
FIGURE 3. “ON” Channel Leakage Current
FIGURE 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output
FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output
FIGURE 6. tPZH, tPHZ Propagation Delay Time Control to Signal Output
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4
AC Test Circuits and Switching Time Waveforms (Continued)
FIGURE 7. Frequency Response
FIGURE 8. Crosstalk: Control Input to Signal Output
FIGURE 9. Crosstalk between Any Two Switches
FIGURE 10. Switch OFF Signal Feedthrough Isolation
FIGURE 11. Sinewave Distortion
5
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Typical Performance Characteristics
Typical “ON” Resistance
Typical Crosstalk between
Any Two Switches
Typical Frequency Response
Special Considerations
In certain applications the external load-resistor current may include both VCC and signal line components. To avoid draw-
ing VCC current when switch current flows into the analog switch input pins, the voltage drop across the switch must not
exceed 0.6V (calculated from the ON resistance).
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6
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M16B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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