74VHC74MTCX_NL [FAIRCHILD]
Dual D-Type Flip-Flop with Preset and Clear; 双D型触发器与预置和清除
| 型号： | 74VHC74MTCX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual D-Type Flip-Flop with Preset and Clear |
| 文件： | 总8页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1992
Revised February 2005
74VHC74
Dual D-Type Flip-Flop with Preset and Clear
General Description
Features
The VHC74 is an advanced high speed CMOS Dual D-
Type Flip-Flop fabricated with silicon gate CMOS technol-
ogy. It achieves the high speed operation similar to equiva-
lent Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The signal level applied to the D input is
transferred to the Q output during the positive going transi-
tion of the CK pulse. CLR and PR are independent of the
CK and are accomplished by setting the appropriate input
LOW.
■ High Speed: fMAX 170 MHz (typ) at TA 25 C
■ High noise immunity: VNIH VNIL 28% VCC (min)
■ Power down protection is provided on all inputs
■ Low power dissipation: ICC
2 A (max) at TA 25 C
■ Pin and function compatible with 74HC74
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Ordering Code:
Package
Order Number
Package Description
Number
74VHC74M
M14A
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC74MX_NL
74VHC74SJ
M14D
74VHC74MTC
MTC14
MTC14
74VHC74MTCX_NL
(Note 1)
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74VHC74N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDED J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS011505
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Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Truth Table
Inputs
CLR PR
Outputs
Function
Pin Names
D1, D2
Description
Data Inputs
D
CK
X
Q
L
Q
H
L
L
H
L
H
L
X
X
X
L
Clear
CK1, CK2
Clock Pulse Inputs
Direct Clear Inputs
Direct Preset Inputs
Output
X
H
Preset
CLR1, CLR2
PR1, PR2
L
X
H (Note 2) H (Note 2)
H
H
H
H
H
H
L
H
H
L
Q1, Q1, Q2, Q2
H
X
Qn
Qn
No Change
Note 2: This configuration is nonstable; that is, it will not persist when pre-
set and clear inputs return to their inactive (HIGH) state.
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2
Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions (Note 4)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Input Diode Current (IIK
Output Diode Current (IOK
DC Output Current (IOUT
DC VCC/GND Current (ICC
)
0.5V to 7.0V
0.5V to 7.0V
0.5V to VCC 0.5V
20 mA
)
Supply Voltage (VCC
Input Voltage (VIN
Output Voltage (VOUT
Operating Temperature (TOPR
)
2.0V to 5.5V
0V to 5.5V
0V to VCC
)
)
)
)
)
20 mA
)
40 C to 85 C
)
25 mA
Input Rise and Fall Time (tr, tf)
VCC 3.3V 0.3V
)
50 mA
0
100 ns/V
Storage Temperature (TSTG
Lead Temperature (TL)
Soldering (10 seconds)
)
65 C to 150 C
VCC 5.0V 0.5V
0 20 ns/V
Note 3: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading varai-
bles. Fairchild does not recommend operation outside databook specifica-
tions.
260 C
Note 4: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
T
25 C
Typ
T
A
40 C to 85 C
Max
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Min
Max
Min
1.50
0.7 V
V
V
V
HIGH Level Input
Voltage
2.0
1.50
IH
V
V
3.0 5.5 0.7 V
2.0
CC
CC
LOW Level Input
Voltage
0.50
0.50
0.3 V
IL
3.0 5.5
0.3 V
CC
CC
HIGH Level Output
Voltage
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
1.9
2.0
3.0
4.5
1.9
2.9
V
V
V I
IH OH
50 A
OH
IN
2.9
4.4
V
V
V
V
or V
IL
4.4
2.58
3.94
2.48
3.80
I
I
4 mA
8 mA
OH
OH
V
LOW Level Output
Voltage
0.0
0.0
0.0
0.1
0.1
0.1
0.1
V I
IH OL
50 A
OL
IN
or V
IL
0.1
0.1
0.36
0.36
0.1
0.44
0.44
1.0
I
I
4 mA
8 mA
OL
OL
I
I
Input Leakage Current
0
5.5
5.5
A
A
V
V
5.5V or GND
V or GND
CC
IN
CC
IN
Quiescent Supply Current
2.0
20.0
IN
3
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AC Electrical Characteristics
T
25 C
Typ
T
40 C to 85 C
Min Max
V
(V)
A
A
CC
Symbol
Parameter
Units
MHz
MHz
ns
Conditions
Min
80
Max
f
Maximum Clock
3.3 0.3
125
75
70
45
C
C
C
C
C
C
C
C
C
C
C
C
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
MAX
L
Frequency
50
L
5.0 0.5
3.3 0.3
5.0 0.5
3.3 0.3
5.0 0.5
130
90
170
115
6.7
9.2
4.6
6.1
7.6
10.1
4.8
6.3
4
110
75
L
L
t
Propagation Delay
Time (CK-Q, Q)
11.9
15.4
7.3
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
14.0
17.5
8.5
PLH
L
t
PHL
L
L
ns
9.3
10.5
14.5
18.0
9.0
L
t
Propagation Delay Time
(CLR, PR -Q, Q)
12.3
15.8
7.7
PLH
L
ns
t
PHL
L
L
ns
9.7
11.0
10
L
C
C
Input Capacitance
Power Dissipation
Capacitance
10
pF
pF
V
Open
IN
CC
25
(Note 5)
PD
Note 5: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained from the equation: I (opr.)
CC
C
* V * f
I /2 (per F/F).
CC
PD
CC
IN
AC Operating Requirements
V
(V)
(Note 6)
T
25 C
T
40 C to 85 C
Guaranteed Minimum
CC
A
A
Symbol
Parameter
Minimum Pulse Width (CK)
Units
Typ
t
t
(L)
3.3
6.0
7.0
5.0
W
ns
(H)
5.0
5.0
W
t
t
t
(L)
Minimum Pulse Width (CLR, PR)
Minimum Setup Time
3.3
5.0
3.3
5.0
3.3
5.0
6.0
5.0
6.0
5.0
0.5
0.5
7.0
5.0
7.0
5.0
0.5
0.5
W
ns
ns
ns
S
Minimum Hold Time
H
t
Minimum Recovery Time (CLR, PR)
3.3
5.0
5.0
3.0
5.0
3.0
REC
ns
Note 6: V is 3.3 0.3V or 5.0 0.5V
CC
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4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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