74VHCT373A [FAIRCHILD]
Octal D-Type Latch with 3-STATE Outputs; 八D型锁存器带3态输出
| 型号： | 74VHCT373A |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal D-Type Latch with 3-STATE Outputs |
| 文件： | 总8页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1997
Revised April 2005
74VHCT373A
Octal D-Type Latch with 3-STATE Outputs
General Description
Features
The VHCT373A is an advanced high speed CMOS octal D-
type latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type
latch is controlled by a latch enable input (LE) and an out-
put enable input (OE). The latches appear transparent to
data when latch enable (LE) is HIGH. When LE is LOW, the
data that meets the setup time is latched. When the OE
input is HIGH, the eight outputs are in a high impedance
state.
■ High speed: tPD 7.7 ns (typ) at TA 25 C
■ High Noise Immunity: VIH 2.0V, VIL 0.8V
■ Power Down Protection is provided on all inputs and
outputs
■ Low Power Dissipation:
ICC
4 A (max) @ TA 25 C
■ Pin and Function Compatible with 74HCT373
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Note 1: Outputs in OFF-State.
Ordering Code:
Order Number
74VHCT373AM
74VHCT373ASJ
74VHCT373AMTC
74VHCT373AN
Package Number
M20B
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
M20D
MTC20
N20A
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Connection Diagram
IEEE/IEC
© 2005 Fairchild Semiconductor Corporation
DS500027
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Pin Descriptions
Truth Table
Pin Names
Description
Data Inputs
Inputs
OE
Outputs
On
D0–D7
LE
Dn
LE
Latch Enable Input
X
H
H
L
H
L
L
L
X
L
Z
L
OE
Output Enable Input
3-STATE Outputs
O0–O7
H
X
H
O0
H
L
Z
X
O
HIGH Voltage Level
LOW Voltage Level
High Impedance
Immaterial
Previous O before HIGH-to-LOW transition of Latch Enable
0
0
Functional Description
The VHCT373A contains eight D-type latches with 3-
STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the Dn inputs enters the latches. In
this condition the latches are transparent, i.e., a latch out-
put will change state each time its D input changes. When
LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the HIGH-
to-LOW transition of LE. The 3-STATE standard outputs
are controlled by the Output Enable (OE) input. When OE
is LOW, the standard outputs are in the 2-state mode.
When OE is HIGH, the standard outputs are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 6)
Supply Voltage (VCC
)
0.5V to 7.0V
0.5V to 7.0V
DC Input Voltage (VIN
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to 5.5V
DC Output Voltage (VOUT
)
Input Voltage (VIN
)
(Note 3)
0.5V to VCC 0.5V
0.5V to 7.0V
20 mA
Output Voltage (VOUT
)
(Note 4)
(Note 3)
0V to VCC
0V to 5.5V
Input Diode Current (IIK
)
(Note 4)
Output Diode Current (IOK
(Note 5)
)
Operating Temperature (TOPR
)
40 C to 85 C
20 mA
25 mA
Input Rise and Fall Time (tr, tf)
VCC 5.0 0.5V
DC Output Current (IOUT
)
0 ns/V 20 ns/V
Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
DC VCC/GND Current (ICC
)
75 mA
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
65 C to 150 C
260 C
Note 3: HIGH or LOW state.
I
absolute maximum rating must be
OUT
observed.
Note 4: When outputs are in OFF-State or when V
OV.
CC
Note 5: V
GND, V
V
(Outputs Active).
OUT
OUT
CC
Note 6: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
T
25 C
Typ
T
40 C to 85 C
Min Max
V
(V)
A
A
CC
Symbol
Parameter
Units
Conditions
Min
2.0
2.0
Max
V
V
V
V
HIGH Level
Input Voltage
LOW Level
Input Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
3-STATE Output
4.5
5.5
4.5
5.5
4.5
4.5
4.5
4.5
2.0
2.0
IH
V
V
0.8
0.8
0.8
0.8
IL
4.40
3.94
4.50
0.0
4.40
3.80
V
V
V
V
V
V
V
I
OH
50
A
OH
OL
IN
IH
or V
I
8 mA
IL OH
0.1
0.1
V
I
50
A
IN
IH
OL
0.36
0.44
or V
I
8 mA
IL OL
I
V
V
V
V
V
V
or V
IL
OZ
IN
IH
5.5
0.25
2.5
A
OFF-State Current
V or GND
CC
OUT
IN
I
I
I
Input Leakage Current
Quiescent Supply Current
0
5.5
0.1
4.0
1.0
40.0
1.50
A
A
5.5V or GND
V or GND
CC
IN
5.5
5.5
CC
CCT
IN
Maximum I /Input
CC
1.35
mA
3.4V
IN
Other Inputs
V 5.5V
OUT
V
or GND
CC
I
Output Leakage Current
(Power Down State)
0.0
0.5
0.5
A
OFF
Noise Characteristics
T
25 C
Limits
V
(V)
A
CC
Symbol
Parameter
Quiet Output Maximum Dynamic V
Units
Conditions
Typ
V
5.0
5.0
5.0
5.0
1.2
1.6
1.6
2.0
0.8
V
V
V
V
C
C
C
C
50 pF
50 pF
50 pF
50 pF
OLP
OL
L
L
L
L
(Note 7)
V
Quiet Output Minimum Dynamic V
1.2
OLV
OL
(Note 7)
V
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
IHD
(Note 7)
V
ILD
(Note 7)
Note 7: Parameter guaranteed by design.
3
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AC Electrical Characteristics
T
25 C
Typ
T
A
40 C to 85 C
V
(V)
A
CC
Symbol
Parameter
Units
ns
Conditions
Min
Max
12.3
13.3
8.5
Min
Max
13.5
14.5
9.5
t
Propagation Delay Time
7.7
8.5
5.1
5.9
6.3
7.1
8.8
1.0
1.0
1.0
1.0
1.0
1.0
1.0
C
C
C
C
C
C
C
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
50 pF
PLH
L
L
L
L
L
L
L
5.0 0.5
t
(LE to O )
n
PHL
t
Propagation Delay Time
PLH
5.0 0.5
5.0 0.5
ns
t
(D to O )
n
9.5
10.5
12.5
13.5
12.0
PHL
t
3-STATE Output Enable Time
10.9
11.9
11.2
R
R
1 k
1 k
PZL
L
ns
ns
t
PZH
t
3-STATE Output Disable Time 5.0 0.5
PLZ
L
t
PHZ
t
Output to Output Skew
5.0 0.5
1.0
10
1.0
10
(Note 8)
OSLH
t
OSHL
C
Input Capacitance
4
6
pF
pF
V
V
Open
5.0V
IN
CC
CC
C
C
Output Capacitance
OUT
PD
Power Dissipation Capacitance
25
pF (Note 9)
Note 8: Parameter guaranteed by design. t
|t
max
t
|; t
|t
t
|
OSLH
PLH
PLH min
OSHL
PHL max
PHL min
Note 9: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation: I (opr.)
CC
C
• V • f
I
/8 (per F/F).
PD
CC
IN
CC
AC Operating Requirements
T
25 C
Typ
T
40 C to 85 C
Min Max
V
(V)
A
A
CC
Symbol
Parameter
Units
Min
6.5
1.5
3.5
Max
t
t
t
(H)
Minimum Pulse Width (LE)
Minimum Set-Up Time
Minimum Hold Time
5.0 0.5
5.0 0.5
5.0 0.5
8.5
1.5
3.5
ns
ns
ns
W
S
H
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
相关型号：
74VHCT373AMX_NL
Bus Driver, AHCT/VHCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20
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