FAN2110MPX_技术文档

August 2009

FAN2110 — TinyBuck™

3-24V Input, 10A, High-Efficiency, Integrated

Synchronous Buck Regulator

Features

Description

The FAN2110 TinyBuck™ is a highly efficient, small

footprint, constant frequency, 10A integrated

synchronous Buck regulator.

Wide Input Voltage Range: 3V-24V

Wide Output Voltage Range: 0.8V to 80% V_IN

10A Output Current

The FAN2110 contains both synchronous MOSFETs

and a controller/driver with optimized interconnects in

one package, which enables designers to solve high-

current requirements in a small area with minimal

external components. Integration helps to minimize

critical inductances making component layout simpler

and more efficient compared to discrete solutions.

1% Reference Accuracy Over Temperature

Over 93% Peak Efficiency

Programmable Frequency Operation: 200KHz to

600KHz

Fully Synchronous Operation with Integrated

Schottky Diode on Low-Side MOSFET Boosts

Efficiency

The FAN2110 provides for external loop compensation,

programmable switching frequency, and current limit.

These features allow design flexibility and optimization.

High frequency operation allows for all ceramic

solutions.

Internal Bootstrap Diode

Power-Good Signal

Starts up on Pre-Bias Outputs

Accepts Ceramic Capacitors on Output

External Compensation for Flexible Design

Programmable Current Limit

The summing current mode modulator uses lossless

current sensing for current feedback and over-current

protection. Voltage feedforward helps operation over a

wide input voltage range.

Fairchild’s advanced BiCMOS power process,

combined with low-R_DS(ON)internal MOSFETs and a

thermally efficient MLP package, provide the ability to

dissipate high power in a small package.

Under-Voltage, Over-Voltage, and Thermal

Shutdown Protections

Internal Soft-Start

5x6mm, 25-Pin, 3-Pad MLP Package

Output over-voltage, under-voltage, and thermal

shutdown protections help protect the device from

damage during fault conditions. FAN2110 also prevents

pre-biased output discharge during startup in point-of-

load applications.

Applications

Servers & Telecom

Graphics Cards & Displays

Computing Systems

Related Application Notes

AN-8022 — TinyCalc™ Calculator

Point-of-Load Regulation

Set-Top Boxes & Game Consoles

Ordering Information

Operating

Part Number Temperature Range

Eco

Status

Packing

Method

Package

FAN2110MPX

-10°C to 85°C

-40°C to 85°C

Molded Leadless Package (MLP) 5x6mm

Green

Tape and Reel

FAN2110EMPX

For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

FAN2110 • Rev. 1.0.2

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Typical Application

Figure 1. Typical Application Diagram

Block Diagram

Figure 2. Block Diagram

FAN2110 • Rev. 1.0.2

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2

Pin Configuration

Figure 3. MLP 5x6mm Pin Configuration (Bottom View)

Pin Definitions

Pin #

P1, 6-12

P2, 2-5

Name Description

SW

VIN

Switching Node. Junction of high-side and low-side MOSFETs.

Power Conversion Input Voltage. Connect to the main input power source.

P3, 21-23

PGND Power Ground. Power return and Q2 source.

High-Side Drive BOOT Voltage. Connect through capacitor (C_BOOT) to SW. The IC

1

BOOT

PGOOD

EN

includes an internal synchronous bootstrap diode to recharge the capacitor on this pin to

_CCwhen SW is LOW.

V

Power-Good Flag. An open-drain output that pulls LOW when FB is outside the limits

specified in electrical specs. PGOOD does not assert HIGH until the fault latch is enabled.

13

14

ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the

regulator after a latched fault condition. This input has an internal pull-up when the IC is

functioning normally. When a latched fault occurs, EN is discharged by a current sink.

Input Bias Supply for IC. The IC’s logic and analog circuitry are powered from this pin.

This pin should be decoupled to AGND through a > 2.2µF X5R / X7R capacitor.

15

16

17

VCC

AGND

ILIM

Analog Ground. The signal ground for the IC. All internal control voltages are referred to

this pin. Tie this pin to the ground island/plane through the lowest impedance connection.

Current Limit. A resistor (R_ILIM) from this pin to AGND can be used to program the current-

limit trip threshold lower than the internal default setting.

Oscillator Frequency. A resistor (R_T) from this pin to AGND sets the PWM switching

frequency.

18

19

20

24

25

R(T)

FB

Output Voltage Feedback. Connect through a resistor divider to the output voltage.

Compensation. Error amplifier output. Connect the external compensation network

between this pin and FB.

COMP

NC

No Connect. This pin is not used.

Ramp Amplitude. A resistor (R_RAMP) connected from this pin to V_INsets the ramp amplitude

and provides voltage feedforward functionality.

RAMP

FAN2110 • Rev. 1.0.2

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3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Parameter

VIN to PGND

VCC to AGND

BOOT to PGND

BOOT to SW

Conditions

Min.

Max.

28

Unit

V

AGND=PGND

Continuous

6

V

35

V

-0.5

-5

6.0

V

24.0

30

V

SW to PGND

All other pins

ESD

Transient (t < 20ns, f < 600KHz)

V

-0.3

2.0

2.5

V_CC+0.3

V

Human Body Model, JEDEC JESD22-A114

Charged Device Model, JEDEC JESD22-C101

KV

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol

V_CC

Parameter

Bias Voltage

Conditions

VCC to AGND

Min.

4.5

3

Typ.

Max.

5.5

Unit

V

5.0

V_IN

Supply Voltage

VIN to PGND

FAN2110MPX

FAN2110EMPX

24

V

-10

-40

+85

+125

600

°C

kHz

T_A

Ambient Temperature

T_J

Junction Temperature

Switching Frequency

f_SW

200

Thermal Information

Symbol

Parameter

Min.

Typ.

Max.

+150

+300

Unit

°C

T_STG

T_L

Storage Temperature

-65

Lead Soldering Temperature, 10 Seconds

Thermal Resistance: Junction-to-Case

°C

P1 (Q2)

P2 (Q1)

P3

4

7

°C/W

W

θ_JC

4

Thermal Resistance: Junction-to-Mounting Surface⁽¹⁾

Power Dissipation, T_A=25°C⁽¹⁾

35

θ_J-PCB

P_D

2.8

Note:

1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 35. Actual results

are dependent on mounting method and surface related to the design.

FAN2110 • Rev. 1.0.2

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4

Electrical Specifications

Electrical specifications are the result of using the circuit shown in Figure 1 with V_IN=12V, unless otherwise noted.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Power Supplies

SW=Open, V_FB=0.7V, V_CC=5V,

8

12

mA

f

_SW=600KHz

I_CC

V_CCCurrent

Shutdown: EN=0, V_CC=5V

Rising V_CC

7

10

µA

V

4.1

4.3

300

4.5

V_UVLO

Oscillator

f_SW

V_CCUVLO Threshold

Hysteresis

mV

255

540

300

600

50

345

660

65

KHz

ns

R_T=50KΩ to GND

R_T=24KΩ to GND

Frequency

t_ONmin

Minimum On-Time⁽²⁾

16V_IN, 1.8V_OUT, R_T=30KΩ,

V_RAMP

Ramp Amplitude, Peak-to-Peak

Minimum Off-Time⁽²⁾

0.53

100

V

R_RAMP=200KΩ

t_OFFmin

150

ns

Reference

FAN2110MPX, 25°C

FAN2110EMPX, 25°C

794

795

800

806

805

mV

Reference Voltage (see Figure 4 for

Temperature Coefficient)

V_FB

Error Amplifier

G

DC Gain⁽²⁾

Gain Bandwidth Product⁽²⁾

Output Voltage⁽²⁾

80

12

85

15

dB

MHz

V

V_CC=5V

GBW

V_COMP

I_SINK

0.4

1.5

0.8

3.2

Output Current, Sourcing

V_CC=5V, V_COMP=2.2V

V_CC=5V, V_COMP=1.2V

V_FB=0.8V, 25°C

2.2

1.2

mA

nA

I_SOURCEOutput Current, Sinking

I_BIASFB Bias Current

Protection and Shutdown

-850 -650 -450

R_ILIM=182 KΩ,, 25°C, f_SW=500KHz,

Current Limit (see Circuit

I_LIM

12

14

16

-9

A

Description)⁽²⁾

V

_OUT=1.5V, R_RAMP=243KΩ,

16 Consecutive Clock Cycles⁽³⁾

V_CC=5V, 25°C

I_ILIM

T_TSD

T_HYS

V_OVP

V_UVSD

V_FLT

I_LIMCurrent

-11

-10

+155

+30

115

73

µA

°C

Over-Temperature Shutdown⁽²⁾

Over-Temperature Hysteresis⁽²⁾

Over-Voltage Threshold

Under-Voltage Shutdown

Fault Discharge Threshold

Internal IC Temperature

2 Consecutive Clock Cycles⁽³⁾

16 Consecutive Clock Cycles⁽³⁾

Measured at FB Pin

110

68

121 %V_OUT

78

%V_OUT

mV

250

V_{FLT_HYS}Fault Discharge Hysteresis

Measured at FB Pin (V_FB~500mV)

mV

Soft-Start

t_SS

t_EN

V_OUTto Regulation (T0.8)

Fault Enable/SSOK (T1.0)⁽²⁾

5.3

6.7

ms

f

_SW=500KHz

Continued on the following page…

FAN2110 • Rev. 1.0.2

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5

Electrical Specifications (Continued)

Electrical specifications are the result of using the circuit shown in Figure 1 with V_IN=12V, unless otherwise noted.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Control Functions

V_EN

EN Threshold, Rising

V_CC=5V

1.35 2.00

V

V_{EN_HYS}EN Hysteresis

250

800

1

mV

KΩ

µA

Ω

R_EN

EN Pull-Up Resistance

I_{EN_DISC}EN Discharge Current

Auto-Restart Mode, V_CC=5V

R_FBok

FB OK Drive Resistance

PGOOD LOW Threshold

800

FB < V_REF, 2 Consecutive Clock

Cycles⁽³⁾

V_{PGTH_LO}

-14

+7

-11

-8

%V_REF

FB > V_REF, 2 Consecutive Clock

Cycles⁽³⁾

V_{PGTH_UP}

+10 +13.5

0.4

V_{PG_LO}PGOOD Output Low

I_OUT< 2mA

V_PGOOD=5V

V

I_{PG_LK}

PGOOD Leakage Current

0.2

1.0

µA

Notes:

2. Specifications guaranteed by design and characterization; not production tested.

3. Delay times are not tested in production. Guaranteed by design.

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FAN2110 • Rev. 1.0.2

6

Typical Characteristics

1.010

1.005

1.000

0.995

0.990

1.20

1.10

1.00

0.90

0.80

-50

0

50

100

150

-50

0

50

100

150

Temperature (^oC)

Figure 4. Reference Voltage (V_FB

)

Figure 5. Reference Bias Current (I_FB

)

vs. Temperature, Normalized

1500

1200

900

600

300

0

1.02

1.01

1.00

0.99

0.98

600KHz

300KHz

-50

0

50

100

150

0

20

40

60

80

100

120

140

Temperature (^oC)

R_T(K )

Ω

Figure 6. Frequency vs. R_T

Figure 7. Frequency vs. Temperature, Normalized

1.4

1.2

1

1.04

1.02

1.00

0.98

0.96

Q1 ~0.32%/°C

Q2 ~0.35%/°C

0.8

0.6

-50

0

50

100

150

0

50

100

150

Temperature (^oC)

Temperature (°C)

Figure 8. R_DSvs. Temperature, Normalized

(V_CC=V_GS=5V), Figure 1

Figure 9. ILIM Current (I_ILIM) vs. Temperature,

Normalized

FAN2110 • Rev. 1.0.2

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Application Circuits

FAN2110

Figure 10. Application Circuit: 1.5V_OUT, 10A, 500KHz (10V-20V_IN)

FAN2110

Figure 11. Application Circuit: 1.5V_OUT, 10A, 500KHz (3.3V-5.5V_IN)

FAN2110 • Rev. 1.0.2

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8

Typical Performance Characteristics

Typical operating characteristics using the circuit in Figure 10. V_IN=12V, V_CC=5V, T_A=25°C, unless otherwise specified.

FAN2110_1.5V_500Khz

FAN2110_3.3V_500Khz

100

95

90

85

80

75

70

100

95

90

85

80

75

70

VIN = 10V

VIN = 12V

VIN = 16V

VIN = 20V

VIN = 10V

VIN = 12V

VIN = 16V

VIN = 20V

0

2

4

6

8

10

0

2

4

6

8

10

Load Current (Amps)

Figure 12. 1.5V_OUTEfficiency, 500KHz

Figure 13. 3.3V_OUTEfficiency, 500KHz⁽⁴⁾

FAN2110_1.5V_300Khz

FAN2110_3.3V_300Khz

100

95

90

85

80

75

70

95

90

85

80

75

70

VIN = 10V

VIN = 12V

VIN = 16V

VIN = 20V

VIN = 12V

VIN = 16V

VIN = 20V

0

2

4

6

8

10

0

2

4

6

8

10

Load Current (Amps)

Figure 14. 1.5V_OUTEfficiency, 300KHz

Figure 15. 3.3V_OUTEfficiency, 300KHz⁽⁴⁾

FAN2110_2.5V_600Khz

FAN2110_1.5V_500K(3.3-5.5V)

95

90

85

80

75

70

100

95

90

85

80

75

70

VIN = 10V

VIN = 12V

VIN = 16V

VIN = 20V

VIN=3.5V

VIN=4.5V

VIN=5.5V

0

2

4

6

8

10

0

2

4

6

8

10

Load Current (Amps)

Figure 16. 2.5V_OUTEfficiency ,600KHz⁽⁴⁾

Figure 17. 1.5V_OUTEfficiency, 500KHz

(V_IN=3.3V to 5V), Figure 11

Note:

4. Circuit values for this configuration change in Figure 10.

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FAN2110 • Rev. 1.0.2

9

Typical Performance Characteristics (Continued)

Typical operating characteristics using the circuit in Figure 10. V_IN=12V, V_CC=5V, T_A=25°C unless otherwise specified.

Peak HS & LS Mosfet Tempr for 1.5V Output

(Measured on Demo Board)

Package Power Dissipation at various Vout(s)

Fsw = 500Khz

80

70

60

50

40

30

20

10

0

3

2.5

2

1.5

1

VIN=10V_HS

VIN=10V_LS

VIN=20V_HS

VIN=20V_LS

Vout = 1.5V

Vout = 1.8V

Vout = 3.3V

0.5

0

2

4

6

8

10

1

2

3

4

5

6

7

8

9

10

Load Current (A)

Load Current (Amps)

Figure 18. Peak MOSFET Temperatures, Figure 10

Figure 19. Device Dissipation Over V_OUTvs. Load

Line Regulation Data

Load Regulation

0.05

0.02

0

0.01

0

2

4

6

8

10

-0.05

-0.1

5

10

15

20

25

-0.01

-0.02

-0.03

-0.04

-0.15

-0.2

VIN=10V

VIN=20V

No Load

1A Load

-0.25

Input Voltage (Volts)

Load Current (Amps)

Figure 20. 1.5V_OUTLine Regulation

Figure 21.

1.5V_OUTLoad Regulation

Peak HS & LS Mosfet Tempr for 3.3V Output

(Measured on Demo Board)

Safe Operating Area curves for 70 Deg Temperature rise

VIN = 20V, Natural Convection

100

80

60

40

20

0

12

10

8

6

4

VIN=10V_HS

300K

500K

600K

VIN=10V_LS

VIN=20V_HS

VIN=20V_LS

2

0

2

4

6

8

10

12

14

1

2

3

4

5

6

7

8

9

10

Load Current (Amps)

Output Voltage (Volts)

Figure 23.

Typical 20V_INSafe Operation Area

Figure 22. Peak MOSFET Temperatures, 3.3V Output⁽⁵⁾

(SOA), 70°C Ambient Temperature, Natural

Convection

Note:

5. Circuit values for this configuration change in Figure 10.

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FAN2110 • Rev. 1.0.2

10

Typical Performance Characteristics (Continued)

Typical operating characteristics using the circuit in Figure 10. V_IN=12V, V_CC=5V, T_A=25°C unless otherwise specified.

V_OUT

V_SW

EN

PGOOD

Figure 24. Startup, 10A Load

Figure 25. Startup with 1.0V Pre-Bias on V_OUT

V_OUT, 50mV/div

V_OUT

EN

V_SW,10V/Div

PGOOD

Figure 26. Shutdown, 10A Resistive Load

Figure 27. V_OUTRipple and SW Voltage, 10A Load

V_OUT, 200mV/div

I_OUT,5A/Div

EN, 2V/Div

Figure 28. Transient Response, 0-8A Load,

5A / µs Slew Rate

Figure 29. Restart on Short Circuit (Fault)

FAN2110 • Rev. 1.0.2

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11

Circuit Description

PWM Generation

1.35V

EN

FB

Refer to Figure 2 for the PWM control mechanism.

FAN2110 uses the summing-mode method of control to

generate the PWM pulses. An amplified current-sense

signal is summed with an internally generated ramp and

the combined signal is compared with the output of the

error amplifier to generate the pulse width to drive the

high-side MOSFET. Sensed current from the previous

cycle is used to modulate the output of the summing

block. The output of the summing block is also

compared against a voltage threshold set by the R_LIM

resistor to limit the inductor current on a cycle-by-cycle

basis. R_RAMPresistor helps set the charging current for

the internal ramp and provides input voltage feed-

forward function. The controller facilitates external

compensation for enhanced flexibility.

2400 CLKs

0.8V

Fault

Latch

Enable

1.0V

0.8V

SS

3200 CLKs

4000 CLKs

T0.8

Initialization

T1.0

Once V_CCexceeds the UVLO threshold and EN is

HIGH, the IC checks for a shorted FB pin before

releasing the internal soft-start ramp (SS).

Figure 31. Soft-Start Timing Diagram

V_CCUVLO or toggling the EN pin discharges the

internal SS and resets the IC. In applications where

external EN signal is used, V_INand V_CCshould be

established before the EN signal comes up to prevent

skipping the soft-start function.

If the parallel combination of R1 and R_BIASis ≤ 1KΩ, the

internal SS ramp is not released and the regulator does

not start.

Enable

Startup on Pre-Bias

FAN2110 has an internal pull-up to the enable (EN) pin

so that the IC is enabled once V_CCexceeds the UVLO

threshold. Connecting a small capacitor across EN and

AGND delays the rate of voltage rise on the EN pin. The

EN pin also serves for the restart whenever a fault

occurs (refer to the Auto-Restart section). If the

regulator is enabled externally, the external EN signal

should go HIGH only after V_CCis established. For

applications where such sequencing is required,

FAN2110 can be enabled (after the V_CCcomes up) with

external control, as shown in Figure 30.

The regulator does not allow the low-side MOSFET to

operate in full synchronous mode until SS reaches 95%

of V_REF(~0.76V). This enables the regulator to startup

on a pre-biased output and ensures that pre-biased

outputs are not discharged during the soft-start cycle.

Protections

The converter output is monitored and protected

against extreme overload, short-circuit, over-voltage,

under-voltage, and over-temperature conditions.

Under-Voltage Shutdown

If voltage on the FB pin remains below the under-

voltage threshold for 16 consecutive clock cycles, the

fault latch is set and the converter shuts down. This

protection is not active until the internal SS ramp

reaches 1.0V during soft-start.

Over-Voltage Protection

Figure 30. Enabling with External Control

If voltage on the FB pin exceeds 115% of V_REFfor two

consecutive clock cycles, the fault latch is set and

shutdown occurs.

Soft-Start

Once internal SS ramp has charged to 0.8V (T0.8), the

output voltage is in regulation. Until SS ramp reaches

1.0V (T1.0), the fault latch is inhibited.

A shorted high-side MOSFET condition is detected

when SW voltage exceeds ~0.7V while the low-side

MOSFET is fully enhanced. The fault latch is set

immediately upon detection.

To avoid skipping the soft-start cycle, it is necessary to

apply V_INbefore V_CCreaches its UVLO threshold. Normal

sequence for powering up would be VINÆVCCÆEN.

The OV/UV fault protection circuits above are active all

the time, including during soft-start.

Soft-start time is a function of oscillator frequency.

FAN2110 • Rev. 1.0.2

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12

If auto-restart is not desired, tie the EN pin to the VCC

pin or pull it HIGH after V_CCcomes up with a logic gate

to keep the 1µA current sink from discharging EN to

1.1V. Figure 32 shows one method to pull up EN to V_CC

for a latch configuration.

Over-Temperature Protection (OTP)

The chip incorporates an over-temperature protection

circuit that sets the fault latch when a die temperature of

about 150°C is reached. The IC restarts when the die

temperature falls below 125°C.

Auto-Restart

After a fault, EN pin is discharged by a 1µA current sink

to a 1.1V threshold before the internal 800KΩ pull-up is

restored. A new soft-start cycle begins when EN

charges above 1.35V.

Depending on the external circuit, the FAN2110 can be

configured to remain latched-off or to automatically

restart after a fault.

Table 1. Fault / Restart Configurations

EN Pin

Controller / Restart State

Figure 32. Enable Control with Latch Option

Pull to GND

OFF (Disabled)

No Restart – Latched OFF

(After V_CCComes Up)

Pull-up to V_CCwith 100K

Open

Power-Good (PGOOD) Signal

Immediate Restart After Fault

PGOOD is an open-drain output that asserts LOW

when V_OUTis out of regulation, as measured at the FB

pin. Thresholds are specified in the Electrical

Specifications section. PGOOD does not assert HIGH

until the fault latch is enabled (T1.0) (see Figure 31).

New Soft-Start Cycle After:

Cap. to GND

t

_DELAY(ms)=3.9 • C(nf)

When EN is left open, restart is immediate.

FAN2110 • Rev. 1.0.2

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13

Application Information

Bias Supply

The FAN2110 requires a 5V supply rail to bias the IC

and provide gate-drive energy. Connect a ≥ 2.2µf X5R

or X7R decoupling capacitor between VCC and AGND.

V_OUT

Vin

ΔIL • f

V_OUT• (1-

)

(4)

L =

where f is the oscillator frequency.

Since V_CCis used to drive the internal MOSFET gates,

supply current is frequency and voltage dependent.

Approximate V_CCcurrent (I_CC) is calculated by:

Setting the Ramp Resistor Value

R_RAMPresistor plays a critical role in the design by

providing charging current to the internal ramp capacitor

and also serving as a means to provide input voltage

feedforward.

V_CC− 5

I_CC

= 4.58 + [(

+ 0.013)•(f −128)]

(1)

(mA)

227

R_RAMPis calculated by the following formula:

where frequency (f) is expressed in KHz.

(V_IN−1.8)•V_OUT

(31− 2.05 •I_OUT)•V_IN• f •10⁻⁶

R_RAMP(KΩ)

=

− 2

Setting the Output Voltage

(5)

The output voltage of the regulator can be set from 0.8V

to 80% of V_INby an external resistor divider (R1 and

R_BIASin Figure 1). For output voltages >3.3V, output

current rating may need to be de-rated depending on

the ambient temperature, power dissipated in the

package and the PCB layout. (Refer to Thermal

Information table on page 4, Figure 22, and Figure 23.)

where frequency (f) is expressed in KHz.

For wide input operation, first calculate R_RAMPfor the

minimum and maximum input voltage conditions and

use larger of the two values calculated.

In all applications, current through the R_RAMPpin must

be greater than 10µA from the equation below for

proper operation:

The external resistor divider is calculated using:

V_OUT− 0.8V

R1

0.8V

=

+ 650nA

(2)

R_BIAS

V_IN−1.8

R_RAMP+ 2

≥ 10μA

(6)

Connect R_BIASbetween FB and AGND.

If R1 is open (see Figure 1), the output voltage is not

regulated and a latched fault occurs after the SS is

complete (T1.0).

If the calculated R_RAMPvalues in Equation (5) result in a

current less than 10µA, use the R_RAMPvalue that

satisfies Equation (6). In applications with large Input

ripple voltage, the R_RAMPresistor should be adequately

decoupled from the input voltage to minimize ripple on

the ramp pin. For example, see Figure 11.

If the parallel combination of R1 and R_BIASis ≤ 1KΩ, the

internal SS ramp is not released and the regulator does

not start.

Setting the Current Limit

Setting the Clock Frequency

Oscillator frequency is determined by an external resistor,

R_T, connected between the R_Tpin and AGND.

Resistance is calculated by:

There are two levels of current-limit thresholds. The first

level of protection is through an internal default limit set

at the factory to limit output current beyond normal

usage levels. The second level of protection is set

externally at the ILIM pin by connecting a resistor (R_ILIM

)

(10⁶/ f ) −135

(3)

between ILIM and AGND. Current-limit protection is

enabled whenever the lower of the two thresholds is

reached (see Figure 33). FAN2110 uses its internal low-

side MOSFET for current-sensing. The current-limit

threshold voltage (V_ILIM) is compared to a scaled

version of voltage drop across the low-side MOSFET

sampled at the end of each PWM off-time/cycle. The

internal default threshold (with I_LIMopen) is temperature

compensated.

R_T

=

(KΩ)

65

where R_Tis in KΩ and frequency (f) is in KHz.

The regulator cannot start if R_Tis left open.

Calculating the Inductor Value

Typically the inductor value is chosen based on ripple

current (ΔI_L), which is chosen between 10 to 35% of the

maximum DC load. Regulator designs that require fast

transient response use a higher ripple-current setting,

while regulator designs that require higher efficiency

keep ripple current on the low side and operate at a

lower switching frequency. The inductor value is

calculated by the following formula:

FAN2110 • Rev. 1.0.2

www.fairchildsemi.com

14

Figure 34. Compensation Network

Figure 33.ILIM Network

Since the FAN2110 employs summing current-mode

architecture, type-2 compensation can be used for

many applications. For applications that require wide

loop bandwidth and/or use very low-ESR output

capacitors, type-3 compensation may be required.

The ILIM pin can source a 10µA current that can be

used to establish a lower, temperature–dependent,

current-limit threshold by connecting an external

resistor (R_ILIM) to AGND. R_ILIMcan be approximated with

the equation:

R_RAMPalso provides feedforward compensation for

changes in V_IN. With a fixed R_RAMPvalue, the modulator

gain increases as V_INis reduced, which could make it

difficult to compensate the loop. For low-input-voltage-

range designs (3V to 8V), R_RAMPand the compensation

component values will be different compared to designs

with V_INbetween 8V and 24V.

(V −1.8)•V_OUT•3.33•10⁶

IN

R_ILIM(KΩ) = 95+ 6.1•I_OUT

+

(7)

(R_RAMP+ 2)•V •f

IN

where:

I_OUT= Full load current in Amps;

V_OUT= Set output voltage;

V_IN= Input voltage;

Recommended PCB Layout

R

f

_RAMP= Ramp resistor used in KΩ; and

Good PCB layout and careful attention to temperature

rise is essential for reliable operation of the regulator.

Four-layer PCB with two-ounce copper on the top and

bottom side and thermal vias connecting the layers is

recommended. Keep power traces wide and short to

minimize losses and ringing. Do not connect AGND to

PGND below the IC. Connect the AGND pin to PGND at

the output OR to the PGND plane.

= Selected switching frequency in KHz.

After 16 consecutive, pulse-by-pulse, current-limit

cycles, the fault latch is set and the regulator shuts

down. Cycling V_CCor EN restores operation after a

normal soft-start cycle (refer to Auto-Restart section).

The over-current protection fault latch is active during

the soft-start cycle. Use a 1% resistor for R_ILIM

.

Always use an external resistor R_ILIMto set the current

limit at the desired level. When R_ILIMis not connected,

the IC’s internal default current limit is fairly high. This

could lead to operation at high load currents, causing

overheating of the regulator. For a given R_ILIMand

V_IN

SW

GND

R_RAMPsetting, the current limit point varies slightly in an

inverse relationship with respect to input voltage (V_IN).

GND

Loop Compensation

The loop is compensated using a feedback network

around the error amplifier. Figure 34 shows a complete

V_OUT

type-3

compensation

network.

For

type-2

compensation, eliminate R3 and C3.

Figure 35. Recommended PCB Layout

FAN2110 • Rev. 1.0.2

www.fairchildsemi.com

15

Physical Dimensions

2X

TOP VIEW

2X

RECOMMENDED LAND PATTERN

ALL VALUES TYPICAL EXCEPT WHERE NOTED

SIDE VIEW

SEATING

PLANE

OPTIONAL LEAD DESIGN

(LEADS# 1, 24 & 25 ONLY)

SCALE: 1.5X

A) DIMENSIONS ARE IN MILLIMETERS.

B) DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 1994

BOTTOM VIEW

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) DESIGN BASED ON JEDEC MO-220

VARIATION WJHC

E) TERMINALS ARE SYMMETRICAL AROUND THE

X & Y AXIS EXCEPT WHERE DEPOPULATED.

F) DRAWING FILENAME: MKT-MLP25AREV3

Figure 36. 5x6mm Molded Leadless Package (MLP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN2110 • Rev. 1.0.2

www.fairchildsemi.com

16

FAN2110 • Rev. 1.0.2

www.fairchildsemi.com

17


型号：	FAN2110MPX
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	TinyBuck™, 3-24V Input, 10A, High-Efficiency, Integrated Synchronous Buck Regulator TinyBuck一体化™ ， 3-24V输入， 10A ，高效，集成的同步降压稳压器稳压器
文件：	总17页 (文件大小：1484K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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