FAN302ULMY [FAIRCHILD]
PWM Controller for Low Standby Power Battery-Charger Applications; PWM控制器，用于低待机功耗电池充电器应用
| 型号： | FAN302ULMY |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | PWM Controller for Low Standby Power Battery-Charger Applications |
| 文件： | 总19页 (文件大小：1943K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2012
FAN302UL
PWM Controller for Low Standby Power Battery-
Charger Applications — mWSaver™ Technology
Features
Description
.
.
.
.
.
.
mWSaver™ Technology Provides
Best-in-Class Standby Power
Advanced PWM controller FAN302UL significantly
simplifies isolated power supply designs that require
Constant Current (CC) regulation of the output. The
output current is precisely estimated with information in
the primary side of the transformer and controlled with
an internal compensation circuit, not only removing the
output current sensing loss, but also eliminating external
CC control circuitry. A Green-Mode function with an
extremely low operating current (200µA) in Burst Mode
maximizes light-load efficiency, enabling conformance
to worldwide Standby Mode efficiency guidelines.
Achieves <10mW, Far Below Energy Star’s 5-Star
Level (<30mW).
Proprietary 500V High-Voltage JFET Startup
Reduces Startup Resistor Loss
Low Operation Current in Burst Mode:
350µA Maximum
Constant-Current (CC) Control without Secondary-
Side Feedback Circuitry
Integrated protections include two-level pulse-by-pulse
current limit, Over-Voltage Protection (OVP), brownout
protection, and Over-Temperature Protection (OTP).
Fixed PWM Frequency at 140kHz with Frequency
Hopping to Reduce EMI
.
.
.
High-Voltage Startup
Compared with a conventional approach using external
control circuit in the secondary side for CC regulation;
the FAN302UL reduces total cost, component count,
size, and weight, while simultaneously increasing
efficiency, productivity, and system reliability.
Low Operating Current: 3.5mA
Peak-Current-Mode Control with Slope
Compensation
.
.
.
.
.
.
.
Cycle-by-Cycle Current Limiting
Maximum
Typical
Minimum
VO
VDD Over-Voltage Protection (Auto-Restart)
VS Over-Voltage Protection (Latch Mode)
VDD Under-Voltage Lockout (UVLO)
Gate Output Maximum Voltage Clamped at 15V
Fixed Over-Temperature Protection (Latch Mode)
Available in an 8-Lead SOIC Package
Applications
IO
Battery chargers for cellular phones, cordless phones,
PDA, digital cameras, and power tools. Replaces linear
transformers and RCC SMPS.
Figure 1. Typical Output V-I Characteristic
Ordering Information
Operating
Part Number
Packing
Method
Package
Temperature Range
8-Lead, Small-Outline Integrated Circuit (SOIC),
JEDEC MS-012, .150-Inch Narrow Body
FAN302ULMY
Tape & Reel
-40°C to +105°C
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
Application Diagram
Figure 2. Typical Application
Internal Block Diagram
Figure 3. Functional Block Diagram
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
2
Marking Information
F- Fairchild Logo
Z: Assembly Plant Code
X: Year Code
Y: Week Code
TT: Die Run Code
T: M=SOP
P: Y= Green Package
M: Manufacture Flow Code
Figure 4.Top Mark
Pin Configuration
Figure 5. Pin Assignments
Description
Pin Definitions
Pin #
Name
Current Sense. This pin connects a current-sense resistor to detect the MOSFET current for
Peak-Current-Mode control for output regulation. The current-sense information is also used to
estimate the output current for CC regulation.
1
CS
PWM Signal Output. This pin has an internal totem-pole output driver to drive the power
MOSFET. It is internally clamped at 15V.
2
3
GATE
VDD
Power Supply. IC operating current and MOSFET driving current are supplied through this pin.
This pin is typically connected to an external VDD capacitor.
Voltage Sense. This pin detects the output voltage information and diode current discharge
time based on voltage of the auxiliary winding.
4
5
VS
GND
Ground
Feedback. Typically, an Opto-Coupler is connected to this pin to provide feedback information
to the internal PWM comparator. This feedback is used to control the duty cycle in CV
regulation.
6
FB
7
8
NC
HV
No Connect
High Voltage. This pin connects to the DC bus for high-voltage startup.
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VHV
VVDD
VVS
VCS
VFB
PD
HV Pin Input Voltage
DC Supply Voltage(1,2)
VS Pin Input Voltage
CS Pin Input Voltage
FB Pin Input Voltage
500
30
V
V
-0.3
-0.3
-0.3
7.0
7.0
7.0
660
150
V
V
V
mW
°C/W
Power Dissipation (TA=25°C)
θJA
Thermal Resistance (Junction-to-Air)
Thermal Resistance (Junction-to-Case)
Operating Junction Temperature
θJC
TJ
39
°C/W
°C
-40
-55
+150
+150
+260
TSTG
TL
Storage Temperature Range
°C
Lead Temperature (Wave Soldering or IR, 10 Seconds)
°C
Human Body Model,
JEDEC:JESD22_A114
5.0
1.5
(Except HV Pin)(3)
Electrostatic Discharge Capability
ESD
kV
Charged Device Model,
JEDEC:JESD22_C101
(Except HV Pin)(3)
Notes:
1. All voltage values, except differential voltages, are given with respect to the GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
3. ESD ratings including the HV pin: HBM=500V, CDM=750V.
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
4
Electrical Characteristics
VDD=15V and TA=25°C unless noted.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
HV Section
VHV-MIN Minimum Startup Voltage on HV Pin
50
V
VHV=100V, VDD=0V,
Controller Off
IHV
Supply Current Drawn from HV Pin
0.8
1.5
0.8
5.0
mA
VHV=500V, VDD=15V
(Controller On with
Auxiliary Supply)
IHV-LC
Leakage Current Drawn from HV Pin
3.0
μA
VDD Section
VDD-ON Turn-On Threshold Voltage
VDD-OFF Turn-Off Threshold Voltage
VDD-LH Threshold Voltage for Latch-Off Release
VDD Rising
15
16
5.0
17
V
V
VDD Falling
4.7
5.3
VDD Falling
2.50
V
IDD-ST
Startup Current
VDD=VDD-ON – 0.16V
VDD=18V, f=fOSC, CL=1nF
VDD=8V, CL=1nF
400 450
3.5 4.0
200 350
μA
mA
μA
V
IDD-OP Operating Supply Current
IDD-BURST Burst-Mode Operating Supply Current
VDD-OVP VDD Over-Voltage Protection Level
tD-VDDOVP VDD Over-Voltage Protection Debounce Time
Oscillator Section
25.0 26.5 28.0
100 180
f=140kHz
μs
Center Frequency
VCS=5V, VS=2.5, VFB=5V
135 140 145
fOSC
Frequency
kHz
Hopping Range
±5
Minimum Frequency by Continuous Conduction
Mode (CCM) Prevention Circuit(4)
fOSC-CM-MIN
17
40
22
45
27
50
kHz
kHz
fOSC-CCM Minimum Frequency in (CC) Regulation
VCS=5V, VS=0V
Feedback Input Section
AV
Internal Voltage Scale-Down Ratio of FB Pin(5)
1/3.5 1/3.0 1/2.5 V/V
ZFB
FB Pin Input Impedance
38
42
5.3
1.1
44
kΩ
V
VFB-OPEN FB Pin Pull-Up Voltage
FB Pin Open
VFB-L
FB Threshold to Disable Gate Drive in Burst Mode VFB Falling,VCS=5V, VS=0V 1.0
1.2
V
VFB-H FB Threshold to Enable Gate Drive in Burst Mode
Over-Temperature Protection Section
VFB Rising,VCS=5V, VS=0V 1.05 1.15 1.25
V
Threshold Temperature for Over-Temperature
TOTP
+130 +140 +150
°C
Protection(6)
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN302UL • Rev. 1.0.3
5
Electrical Characteristics (Continued)
VDD=15V and TA=25°C unless noted.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Voltage-Sense Section
ITC
Bias Current
VS Sampling Voltage to Switch to the Second
VCS=5V
8.75 10.00 11.25 μA
VVS-CM-MIN Pulse-by-Pulse Current Limit in Power Limit
0.55
V
Mode(6)
VS Sampling Voltage to Switch Back to the
VVS-CM-MAX
0.75
2.15
0.70
64
V
V
Normal Pulse-by-Pulse Current Limit(6)
VS Sampling Voltage to Start Frequency
Decreasing in CC Mode
VSN-CC
VCS=5V, fS1=fOSC-2KHz
VS Sampling Voltage to End Frequency
Decreasing in CC Mode
VCS=5V, fS2=fOSC-CCM
+2KHz
VSG-CC
V
SG-CC= (fS1-fS2)
kHz/V
SG-CC
Frequency Decreasing Slope of CC Regulation
52
76
/(VSN-CC-VSG-CC
)
Sinking Current Threshold for Brownout
Protection(6)
VVS-OFFSET ZCD Comparator Internal Offset Voltage(6)
IVS-UVP
47
μA
mV
V
200
Output Over-Voltage Protection with VS Sampling
VVS-OVP
Voltage
2.80 2.85
60 120
tVS-OVP
Output Over-Voltage Protection Debounce Time f=140kHz
μs
Current-Sense Section
VVR
Internal Reference Voltage for CC Regulation
2.475 2.500 2.525
2.405 2.430 2.455
V
V
Variation Test Voltage on CS Pin for CC Output
(Non-Inverting Input of Error Amplifier for CC
Regulation)
VCCR
VCS=0.41V
VSTH
VSTH-VA
tPD
Normal Current Limit Threshold Voltage
0.7
V
V
Second Current Limit Threshold Voltage at Power
VVS=0.3V
0.25 0.30 0.35
100 150
Limit Mode (Vs<VVS-CM-MAX
)
GATE Output Turn-Off Delay
ns
ns
VCS=5V, VVS=2.5, VFB=5V
(Test Mode)
tMIN
Minimum On Time
180 250 320
tLEB
Leading-Edge Blanking Time(6)
100 150 200
0.3
ns
V
VSLOPE Slope Compensation(6)
Maximum Duty Cycle
GATE Section
DCYMAX Maximum Duty Cycle
VGATE-L Output Voltage Low
VGATE-H Output Voltage High
VGATE-H Output Voltage High
61
64
67
1.5
8
%
V
VDD=25V, IO=10mA
VDD=8V, IO=1mA
VDD=5.5V, IO=1mA
VDD=15V, CL=1nF
VDD=15V, CL=1nF
5
V
4.0
5.5
V
tr
tf
Rising Time
Falling Time
100 140 180
ns
ns
30
50
70
VGATE-
CLAMP
Gate Output Clamping Voltage
VDD=25V
13
15
17
V
Notes:
4. fOSC-CM-MIN occurs when the power unit enters CCM operation.
5. AV is a scale-down ratio of the internal voltage divider of the FB pin.
6. Not tested; guaranteed by design.
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN302UL • Rev. 1.0.3
6
Typical Performance Characteristics
Figure 6. VDD Turn-On Threshold Voltage (VDD-ON
)
Figure 7. VDD Turn-Off Threshold Voltage (VDD-OFF
)
vs. Temperature
vs. Temperature
Figure 8. Operating Current (IDD-OP) vs. Temperature
Figure 9. Burst Mode Operating Current (IDD-BURST
vs. Temperature
)
Figure 10. CC Regulation Minimum Frequency
(fOSC-CCM) vs. Temperature
Figure 11. Enter Zero Duty Cycle of FB Voltage (VFB-L
vs. Temperature
)
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
7
Typical Performance Characteristics
2.95
2.90
2.85
2.80
2.75
2.70
2.65
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Figure 12. Leave Zero Duty Cycle of FB Voltage
(VFB-H) vs. Temperature
Figure 13. VS Over-Voltage Protection (VVS-OVP
vs. Temperature
)
Figure 14. Reference Voltage of CS (VVR
)
Figure 15. Variation Voltage on CS Pin for CC
Regulation (VCCR) vs. Temperature
vs. Temperature
Figure 16. Starting Voltage of Frequency Decreasing Figure 17. Ending Voltage of Frequency Decreasing of
of CC Regulation (VSN-CC) vs. Temperature CC Regulation (VSG-CC) vs. Temperature
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
8
Typical Performance Characteristics
Figure 18. Threshold Voltage for Current Limit (VSTH
)
Figure 19. Threshold Voltage for Current Limit at
Power Mode (VSTH-VA) vs. Temperature
vs. Temperature
Figure 20. Minimum On Time (tMIN) vs. Temperature
Figure 21.Leading-Edge Blanking Time (tLEB
)
vs. Temperature
Figure 22. Maximum Duty Cycle (DCYMAX
vs. Temperature
)
Figure 23. Gate Output Clamp Voltage (VGATE-CLAMP
vs. Temperature
)
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
9
Operational Description
Basic Control Principle
VEA.I
VEA.V
VEA.I
VEA.V
Figure 24 shows the internal PWM control circuit. The
Constant Voltage (CV) regulation is implemented in the
same way as in a conventional isolated power supply,
where the output voltage is sensed using a voltage
divider and compared with the internal 2.5V reference of
shut regulator (KA431) to generate a compensation
signal. The compensation signal is transferred to the
primary side using an opto-coupler and scaled down
through an attenuator, Av, generating VEA.V signal. Then,
the error signal VEA.V is applied to the PWM comparator
(PWM.V) to determine the duty cycle.
VSAW
Gate
PWM.V
PWM.I
OSC CLK
Meanwhile, CC regulation is implemented internally
without directly sensing output current. The output
CV Regulation
CC Regulation
current estimator reconstructs output current data (VCCR
)
using the transformer primary-side current and diode
current discharge time. Then VCCR is compared with a
reference voltage (2.5V) by an internal error amplifier,
generating a VEA.I signal to determine duty cycle.
Figure 25.PWM Operation for CC and CV
Output Current Estimation
Figure 26 shows the key waveform of a flyback
converter operating in Discontinuous Conduction Mode
(DCM), where the secondary-side diode current reaches
zero before the next switching cycle begins. Since the
output current estimator is designed for DCM operation,
the power stage should be designed such that DCM is
guaranteed for the entire operating range. The output
current is obtained by averaging the triangular output
diode current area over a switching cycle as:
The two error signals, VEA.I and VEA.V, are compared with
an internal sawtooth waveform (VSAW
) by PWM
comparators PWM.I and PWM.V, respectively, to
determine the duty cycle. Figure 24 shows the outputs
of two comparators (PWM.I and PWM.V) combined with
OR gate and used as a reset signal of flip-flop to
determine the MOSFET turn-off instant. Of VEA.V and
VEA.I, the lower signal determines the duty cycle, as
shown in Figure 25. During CV regulation, VEA.V
determines the duty cycle while VEA.I is saturated to
HIGH. During CC regulation mode, VEA.I determines the
duty cycle while VEA.V is saturated to HIGH.
NP TDIS
IO =< ID >AVG = IPK
⋅
(1)
NS 2TS
where IPK is the peak value of the primary-side
current; NP and NS are the number of turns of
transformer primary side and secondary side,
respectively; tDIS is the diode current discharge time;
and tS is the switching period.
I PK
NP
IPK
⋅
NS
< ID >AVG = IO
Figure 24. Internal PWM Control Circuit
Figure 26. Key Waveforms of DCM Flyback
Converter
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
10
With a given current sensing resistor, the output current
can be programmed as:
1.25 NP
IO =
(2)
K ⋅ RSENSE NS
where K is the design parameter of IC, which is 12
for FAN302UL.
The peak value of primary-side current is obtained by an
internal peak-detection circuit while diode current
discharge time is obtained by detecting the diode
current zero-crossing instant. Since the diode current
cannot be sensed directly with primary-side control, the
Zero Crossing Detection (ZCD) is accomplished
indirectly by monitoring the auxiliary winding voltage.
When the diode current reaches zero, the transformer
winding voltage begins to drop by the resonance
between the MOSFET output capacitance and
transformer magnetizing inductance. To detect the
starting instant of the resonance, the VS is sampled at
85% of the diode current discharge time of the previous
switching cycle and compared with the instantaneous VS
voltage. When instantaneous voltage of the VS pin
drops below the sampled voltage by more than 200mV,
ZCD of diode current is obtained as shown in Figure 27.
Figure 28. tDIS Variation in CC Mode
0.85 tDIS (n-1)
ZCD
VS
VSH
Sampling
200mV
tDIS (n)
Figure 29. Frequency Reduction with VSH
Figure 27. Detailed Waveform for ZCD
Frequency Reduction in CC Mode
The transformer should be designed to guarantee DCM
operation over the whole operation range since the
output current is properly estimated only in DCM
operation. As can be seen in Figure 28, the discharge
time (tDIS) of the diode current increases as the output
voltage decreases in CC Mode. The converter tends to
go into CCM as output voltage drops in CC Mode when
operating at the fixed switching frequency. To prevent
this CCM operation and maintain good output current
estimation in DCM, FAN302UL decreases switching
frequency as output voltage drops, as shown in Figure
28 and Figure 29. FAN302UL indirectly monitors the
output voltage by the sample-and-hold voltage (VSH) of
VS, which is taken at 85% of diode current discharge
time of the previous switching cycle, as shown in Figure
27. Figure 30 shows how the frequency reduces as the
sample-and-hold voltage of the VS pin decreases.
Δf
ΔV
= SG−CC
Figure 30. Frequency Reduction Curve in
CC Regulation
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
11
CCM Prevention Function
Even if the power supply is designed to operate in DCM,
it can go into Continuous Conduction Mode (CCM)
when there is not enough design margin to cover all the
circuit parameter variations and operating conditions.
FAN302UL has a CCM-prevention function that delays
the next cycle turn-on of MOSFET until ZCD on the VS
pin is obtained, as shown in Figure 31. To guarantee
stable DCM operation, FAN302UL prohibits the turn-on
of the next switching cycle for 10% of its switching
period after ZCD is obtained. In Figure 31, the first
switching cycle has ZCD before 90% of its original
switching period and, therefore, the turn-on instant of
the next cycle is determined from its original switching
period without being affected by the ZCD instant. The
second switching cycle does not have ZCD by the end
of its original switching period. The turn-on of the third
switching cycle occurs after ZCD is obtained, with a
delay of 10% of its original switching period. The
minimum switching frequency the CCM-prevention
function allows is 22kHz (fOSC-CM-MIN). If the ZCD is not
given until the end of maximum switching period of
45.5µs (1/22kHz), the converter can go into CCM
operation losing output regulation.
Figure 32. Power-Limit Mode Operation
High-Voltage (HV) Startup
Figure 33 shows the high-voltage startup circuit for
FAN302UL applications. Internally a JFET is used to
implement the high-voltage current source, whose
characteristics are shown in Figure 34. Technically, the
HV pin can be directly connected to the DC link (VDL).
However, to improve reliability and surge immunity, it is
typical to use about 100kꢀ resistor between the HV pin
and DC link. The actual HV current with given DC link
voltage and startup resistor is determined by the
intersection of V-I characteristics line and load line, as
shown in Figure 34.
During startup, the internal startup circuit is enabled and
the DC link supplies the current, IHV, to charge the hold-
up capacitor, CVDD, through RSTART. When the VDD
voltage reaches VDD-ON, the internal HV startup circuit is
disabled and the IC starts PWM switching. Once the HV
startup circuit is disabled, the energy stored in CVDD
should supply the IC operating current until the
transformer auxiliary winding voltage reaches the
nominal value. Therefore, CVDD should be designed to
prevent VDD from dropping to VDD-OFF before the auxiliary
winding builds up enough voltage to supply VDD
.
Figure 31. CCM Prevention Function
Power-Limit Mode
When the sampled voltage of VS (VSH) drops below VS-
(0.55V), FAN302UL enters Constant Power Limit
CM-MIN
Mode, where the primary-side current limit voltage (VCS
)
changes from VSTH (0.7V) to VSTH-VA (0.3V) to avoid
miss-operation of VS sampling and ZCD, as shown in
Figure 32. Once the VS sampling voltage is higher than
VS-CM-MAX (0.75V), the VCS returns to VSTH. This mode
prevents the power supply from going into CCM and
losing output regulation when the output voltage is too
low. This effectively protects the power supply when
there is a fault condition in the load, such as output
short or overload. This operation mode also implements
soft-start by limiting the transformer current until the VS
sampling voltage reaches VS-CM-MAX (0.75V).
Figure 33. HV Startup Circuit
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
12
VDL −VHV
IHV
=
RHV
VDL
RHV
VDL
Figure 36. Burst-Mode Operation
Figure 34.V-I Characteristics of HV Pin
Slope Compensation
The sensed voltage across the current-sense resistor is
used for current-mode control and pulse-by-pulse
Frequency Hopping
EMI reduction is accomplished by frequency hopping,
which spreads the energy over a wider frequency range
than the bandwidth of the EMI test equipment, allowing
compliance with EMI limitations. The internal frequency-
hopping circuit changes the switching frequency
progressively between 135kHz and 145kHz with a
period of tp, as shown in Figure 35.
current limiting.
A synchronized ramp signal with
positive slope is added to the current-sense information
at each switching cycle, improving noise immunity of
current-mode control.
Protections
The FAN302UL self-protection functions include VDD
Over-Voltage Protection (VDD OVP), internal Over-
Temperature Protection (OTP), VS Over-Voltage
Protection (VS OVP), and brownout protection. The VDD
OVP and brownout protection are implemented as Auto-
Restart Mode, while the VS OVP and internal OTP are
implemented as Latch Mode.
When an Auto Restart Mode protection is triggered,
switching is terminated and the MOSFET remains off,
causing VDD to drop. When VDD drops to the VDD turn-off
voltage of 5V; the protection is reset, the internal startup
circuit is enabled, and the supply current drawn from the
HV pin charges the hold-up capacitor. When VDD
reaches the turn-on voltage of 16V, normal operation
resumes. In this manner, auto restart alternately
enables and disables MOSFET switching until the
abnormal condition is eliminated, as shown in Figure 37.
When a Latch Mode protection is triggered, PWM
switching is terminated and the MOSFET remains off,
causing VDD to drop. When VDD drops to the VDD turn-off
voltage of 5V, the internal startup circuit is enabled
without resetting the protection, and the supply current
drawn from HV pin charges the hold-up capacitor. Since
the protection is not reset, the IC does not resume PWM
switching even when VDD reaches the turn-on voltage of
16V, disabling the HV startup circuit. Then, VDD drops
again down to 5V. In this manner, the Latch Mode
protection alternately charges and discharges VDD until
there is no more energy in the DC link capacitor. The
protection is reset when VDD drops to 2.5V, which is
allowed only after power supply is unplugged from the
AC line, as shown in Figure 38.
Figure 35. Frequency Hopping
Burst-Mode Operation
The power supply enters Burst Mode at no-load or
extremely light-load conditionS. As shown in Figure 36,
when VFB drops below VFBL, the PWM output shuts off
and the output voltage drops at a rate dependent on
load current. This causes the feedback voltage to rise.
Once VFB exceeds VFBH, the internal circuit starts to
provide switching pulse. The feedback voltage then falls
and the process repeats. Burst Mode alternately
enables and disables switching of the MOSFET,
reducing the switching losses in Standby Mode. Once
FAN302UL enters Burst Mode, the operating current is
reduced from 3.5mA to 200μA to minimize power
consumption in Burst Mode.
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
13
NP
VDL
PWM
Control
Block
RVS1
Minimum
On Time
Modulation
Current
Monitoring
Block
VS
RVS2
CVS
Brownout
Protection
NA
Figure 39.VS Pin Current Sensing
FAN302UL modulates the minimum ON time of the
MOSFET such that it reduces as input voltage
increases, as shown Figure 40. This allows smaller
minimum ON time for high-line condition, ensuring Burst
Mode operation occurs at almost the same power level,
regardless of line voltage variation. The minimum ON
time is also related to the bundle frequency of Burst
Mode operation.
Figure 37. Auto-Restart Mode Operation
The VS current is also used for brownout protection.
When the current out of the VS pin while the MOSFET
is on is smaller than 47μA for longer than 10ms, the
brownout protection is triggered.
Figure 38. Latch-Mode Operation
VDD Over-Voltage Protection
VDD over-voltage protection prevents IC damage from
over-voltage exceeding the IC voltage rating. When the
VDD voltage exceeds 26.5V due to abnormal conditions,
the protection is triggered. This protection is typically
caused by an open circuit of the secondary-side
feedback network.
Figure 40. Minimum On Time vs. VS Pin Current
Over-Temperature Protection (OTP)
The temperature-sensing circuit shuts down PWM
output if the junction temperature exceeds 140°C (tOTP).
VS Over-Voltage Protection (OVP)
Input Voltage Sensing and Brownout Protection
The FAN302UL indirectly senses input voltage using the
VS pin current while the MOSFET is turned on. Since
the VS pin voltage is clamped at 0.7V when the
MOSFET is turned on, the current flowing out of the VS
pin is approximately proportional to the input voltage, as
shown in Figure 38. Current flowing out of the VS pin is
calculated by:
VS over-voltage protection prevents damage due to
output over-voltage conditions. Figure 41 shows the VS
OVP protection method. When abnormal system
conditions occur that cause VS to exceed 2.8V, after a
period of debounce time; PWM pulses are disabled and
FAN302UL enters Latch Mode until VDD drops to under
VDD-LH. By that time, PWM pulses revive. VS over-voltage
conditions are usually caused by an open circuit of the
secondary-side feedback network or abnormal behavior
by the VS pin divider resistor.
NA
IVS.ON = ( VDL + 0.7)
NP
1
0.7 NA VDL
+
≅
(3)
RVS1 RVS 2 NP RVS1
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
14
Figure 41. VS OVP Protection
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse, a 150ns leading-edge
blanking time is built in. Conventional RC filtering can
therefore be omitted. During this blanking period, the
current-limit comparator is disabled and it cannot switch
off the gate driver.
Noise Immunity
Noise from the current sense or the control signal can
cause significant pulse-width jitter. While slope
compensation helps alleviate these problems, further
precautions should still be taken. Good placement and
layout practices should be followed. Avoid long PCB
traces and component leads and, locate bypass filter
components near the PWM IC.
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
15
Typical Application Circuit (Flyback Charger)
Application
Fairchild Device
Input Voltage Range
Output
Cell Phone Charger
FAN302UL
90~265VAC
5V/1.2A (6W)
Features
.
.
Ultra-Low Standby Power Consumption: <20mW at 264VAC (Pin=6.3mW for 115VAC and Pin=7.3mW for 230VAC)
Output Regulation: CV:±5%, CC:±15%
Figure 42.Measured Efficiency and Output Regulation
Figure 43.Schematic of Typical Application Circuit
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
16
Typical Application Circuit (Continued)
Transformer Specification
.
.
Core: EI12.5
Bobbin: EI12.5
Figure 44.Transformer
.
.
W1 is space winding in one layer.
W2 consists of three layers with different numbers of turns. The number of turns of each layer is specified in
Table 1.
.
W3 consists of two layers with triple-insulated wire. The leads of positive and negative fly lines are 3.5cm and
2.5cm, respectively.
Table 1. Transformer Winding Specifications
Terminal
No.
Insulation
Wire
Turns
Start Pin
End Pin
Turns
W1
W2
W3
1
2
2UEW 0.15*2
8
2
0
1
3
3
22
22
22
5
4
5
2UEW 0.12*1
TEX-E 0.4*1
Fly+
Fly-
Pin
4－5
4－5
Specifications
530μH ±7%
Remark
Primary-Side Inductance
100kHz, 1V
Short One of the Secondary Windings
Primary-Side Effective Leakage Inductance
52μH ±5%
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
17
Physical Dimensions
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
0.406
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
Figure 45. 8-Lead, Small Outline Integrated Circuit (SOIC), JEDEC MS-012, .150-Inch, Narrow Body
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
18
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
www.fairchildsemi.com
19
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