FAN3850AUC16X [FAIRCHILD]
Microphone Pre-Amplifier with Digital Output; 麦克风前置放大器，数字输出
| 型号： | FAN3850AUC16X |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Microphone Pre-Amplifier with Digital Output |
| 文件： | 总11页 (文件大小：698K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2011
FAN3850A
Microphone Pre-Amplifier with Digital Output
Features
Description
The FAN3850A integrates a pre-amplifier, LDO, and
ADC that converts Electret Condenser Microphone
(ECM) outputs to digital Pulse Density Modulation
(PDM) data streams. The pre-amplifier accepts analog
signals from the ECM and drives an over-sampled
sigma delta Analog-to-Digital Converter (ADC) and
outputs PDM data. The PDM digital audio has the
advantage of noise rejection and easy interface to
mobile handset processors.
ꢀ
Optimized for Mobile Handset and Notebook PC
Microphone Applications
ꢀ
Accepts Input from Electret Condenser
Microphones (ECM)
ꢀ
ꢀ
ꢀ
ꢀ
Pulse Density Modulation (PDM) Output
Standard 5-Wire Digital Interface
16dB and 19dB Gain Versions Available(1)
The FAN3850A features an integrated LDO and is
powered from the system supply rails up to 3.63V, with
low power consumption of only 0.85mW and less than
20ꢀW in Power-Down Mode.
Low Input Capacitance, High PSR, 20kHz
Pre-Amplifier
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Low-Power 1.5μA Sleep Mode
Typical 470μA Supply Current
Applications
SNR of 62/61dB(A) for 16/19dB Gain Respectively
Total Harmonic Distortion 0.02%
ꢀ
ꢀ
ꢀ
ꢀ
Electret Condenser Microphones with Digital Output
Mobile Handset
Input Clock Frequency Range of 1-4MHz
Integrated Low Drop-Out Regulator (LDO)
Small 1.26mm x 0.86mm 6-Ball WLCSP Package
Headset Accessories
Personal Computer (PC)
.
Ordering Information
Operating
Temperature
Range
Packing
Part Number
Package
Method
3000 Units on
Tape & Reel
FAN3850AUC16X
-30°C to +85°C 6 Ball, Wafer-Level Chip-Scale Package (WLCSP)
-30°C to +85°C 6-Ball, Wafer-Level Chip-Scale Package (WLCSP)
3000 Units on
Tape & Reel
FAN3850AUC19X
Note:
1. Alternate gain options are possible. Please contact Fairchild.
© 2010 Fairchild Semiconductor Corporation
FAN3850A • Rev. 3.0.6
www.fairchildsemi.com
Block Diagram
VDD
Sleep
Mode Ctrl
LDO
CLOCK
ꢀꢀꢀꢁꢂꢃ
INPUT
Pre-Amp
ADC
DATA
SELECT
GND
Figure 1. Block Diagram
Pin Configuration
Figure 2. Pin Assignments
Pin Definitions
Pin#
A1
Name
CLOCK
GND
Type
Input
Input
Output
Input
Input
Input
Description
Clock Input
Ground Pin
B1
C1
A2
DATA
PDM Output – 1 Bit ADC
Rising or Falling Clock Edge Select
Microphone Input
SELECT
INPUT
VDD
B2
C2
Device Power Pin
© 2010 Fairchild Semiconductor Corporation
FAN3850A • Rev. 3.0.6
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VDD
Parameter
Min.
-0.3
-0.3
Max.
4.0
Unit
V
DC Supply Voltage
VIO
Analog and Digital I/O
VCC+0.3
V
Human Body Model, JESD22-A114, All Pins Except
Microphone Input
7
kV
V
ESD
Human Body Model, JESD22-A114 – Microphone Input
300
Note:
2. This device is fabricated using CMOS technology and is therefore susceptible to damage from electrostatic
discharges. Appropriate precautions must be taken during handling and storage of this device to prevent
exposure to ESD.
Reliability Information
Symbol
TJ
Parameter
Junction Temperature
Min.
Typ.
Max.
+150
+125
+260
Unit
°C
TSTG
Storage Temperature Range
Peak Reflow Temperature
-65
°C
TRFLW
°C
Thermal Resistance, JEDEC Standard,
Multilayer Test Boards, Still Air
90
°C/W
ꢄJA
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Temperature Range
Supply Voltage Range
Min.
-30
Typ.
Max.
+85
3.63
10
Unit
°C
VDD
1.64
1.80
V
tRF-CLK
Clock Rise and Fall Time
ns
© 2010 Fairchild Semiconductor Corporation
FAN3850A • Rev. 3.0.6
www.fairchildsemi.com
3
Device Specific Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB (SPL), and fCLK=2.4MHz.
Duty Cycle=50% and CMIC=15pF.
FAN3850AUC16X
FAN3850AUC19X
Symbol
Parameter
Unit
Min. Typ. Max. Min.
Typ.
Max.
Signal-to-Noise Ratio
SNR
eN
62
61
dB(A)
μVRMS
mVPP
fIN=1kHz (1Pa), A-Weighted
Total Input RMS Noise(4)
20Hz to 20kHz, A-Weighted
Maximum Input Signal
fIN=1kHz, THD+N < 10%, Level=0V
5.74
6.80
448
4.45
5.30
317
VIN
Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB (SPL), and fCLK=2.4MHz.
Duty Cycle=50% and CMIC=15pF.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VDD
Supply Voltage Range
1.64
1.80
3.63
V
INPUT=AC Coupled to GND,
CLOCK=On, No Load
IDD
Supply Current
470
1.5
ꢀA
ꢀA
ISLEEP
Sleep Mode Current
fCLK=GND
8.0
INPUT=AC Coupled to GND,
Test Signal on VDD=217Hz
Square Wave and
PSR
Power Supply Rejection(4)
-74
dBFS
Broadband Noise(3), Both
100mVP-P
INNOM
THD
Nominal Sensitivity(5)
Total Harmonic Distortion(6)
INPUT=94dBSPL (1Pa)
-26
dBFS
%
fIN=1kHz, INPUT=-26dBFS
0.02
0.20
1.0
50Hz ꢁ fIN ꢁ 1kHz,
INPUT=-20dBFS
0.2
THD+N
THD and Noise(4)
%
fIN=1kHz, INPUT=-5dBFS
fIN=1kHz, INPUT=0dBFS
INPUT
1.0
5.0
0.2
5.0
10.0
CIN
RIN
Input Capacitance(7)
Input Resistance(7)
pF
INPUT
>100
1.5
Gꢂ
CLOCK & SELECT Input
Logic LOW Level
VIL
VIH
VOL
0.3
V
V
V
CLOCK & SELECT Input
Logic HIGH Level
VDD+0.3
0.35*VDD
Data Output Logic LOW
Level
Data Output Logic HIGH
Level
Acoustic Overload Point(7)
VOH
0.65*VDD
120
V
VOUT
THD < 10%
dBSPL
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN3850A • Rev. 3.0.6
www.fairchildsemi.com
4
Electrical Characteristics (Continued)
Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB(SPL), and fCLK=2.4MHz.
Duty Cycle=50% and CMIC=15pF.
Symbol
Parameter
Condition
Min.
Typ. Max.
Unit
Time from CLOCK Transition
to Data becoming Valid
On Falling Edge of CLOCK,
SELECT=GND, CLOAD=15pF
tA
18
43
ns
Time from CLOCK Transition
to Data becoming HIGH-Z
On Rising Edge of CLOCK,
SELECT=GND, CLOAD=15pF
tB
tA
tB
0
18
0
5
56
5
16
16
ns
ns
ns
Time from CLOCK Transition
to Data becoming Valid
On Rising Edge of CLOCK,
SELECT=VDD, CLOAD=15pF
Time from CLOCK Transition
to Data becoming HIGH-Z
On Falling Edge of CLOCK,
SELECT=VDD, CLOAD=15pF
fCLK
Input CLOCK Frequency(8)
CLOCK Duty Cycle(4)
Wake-Up Time(9)
Active Mode
1.0
40
2.4
50
4.0
60
MHz
%
CLKdc
tWAKEUP
fCLK=2.4MHz
fCLK=2.4MHz
0.35
0.01
2.00
1.00
100
ms
ms
pF
tFALLASLEEP Fall-Asleep Time(10)
0
CLOAD
Notes:
Load Capacitance on Data
3. Pseudo-random noise with triangular probability density function. Bandwidth up to 10MHz.
4. Guaranteed by characterization.
5. Assuming that 120dB(SPL) is mapped to 0dBFS.
6. Assuming an input of -45dBV
7. Guaranteed by design.
8. All parameters are tested at 2.4MHz. Frequency range guaranteed by characterization.
9. Device wakes up when fCLK ꢃ 300kHz.
10. Device falls asleep when fCLK ꢁ 70kHz.
Figure 3. Interface Timing
© 2010 Fairchild Semiconductor Corporation
FAN3850A • Rev. 3.0.6
www.fairchildsemi.com
5
Typical Performance Characteristics
Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB(SPL), fCLK=2.4MHz, and duty
cycle=50%.
Amplitude Spectrum [dBFS], Fo = 1000.2135 Hz, Fs = 2.400000 MHz, SNR = 56.89 dB, SNR = 60.88 dB(A), THD = 0.008 %
Noise
Noise(A)
Signal
-20
Fo(0)= -26.15 dBFS
ꢅ
THD = 81.95 dB
SNR = 60.88 dBc(A)
SINAD = 56.87 dB
ENOB = 13.50
N = 2097152 pts
Blackman Window
-40
-60
-80
Integrated Noise = -87.03 dBFS(A)
ꢆ
ꢆ
-100
-120
-140
-160
Spur = -101.34 dBFS, SFDR = 75.19 dBc
Fo(1)= -110.28 dBFS
ꢅ
Fo(2)= -116.40 dBFS
ꢅ
Fo(3)= -120.45 dBFS
ꢅ
Fo(4)= -125.03 dBFS
ꢅ
101
102
103
Frequency [Hz]
104
105
106
Filename: fan3850a-1-BD92M-20110125T122914.dat
Figure 4. Noise vs. Frequency
Figure 5. THD, SINDA, and SNR vs. Input Amplitude
© 2010 Fairchild Semiconductor Corporation
FAN3850A • Rev. 3.0.6
www.fairchildsemi.com
6
Typical Performance Characteristics (Continued)
Figure 6. THD, SINAD, and SNR vs. Output Level
Tempꢀ(ꢁC)
Delta(dB)
0.1971
0.1644
0.1260
0.0954
0.0657
0.0359
0.0139
0.0000
ꢂ0.0097
ꢂ0.0344
ꢂ0.0514
ꢂ0.0739
ꢂ0.0998
ꢂ0.1183
ꢂ0.1271
ꢂ40
ꢂ30
ꢂ20
ꢂ10
0
10
20
25
30
40
50
60
70
80
85
Figure 7. ꢀ Gain vs. Temperature (Nominal Temperature= 25°C)
© 2010 Fairchild Semiconductor Corporation
FAN3850A • Rev. 3.0.6
www.fairchildsemi.com
7
Applications Information
VDD
Audio
Output
SPEAKER
CLOCK
DATA
INPUT
Pre-
Amp
ADC
SELECT
CLK SDI
SDO L/R
Serial Port
Noise Shaper
Interpolation
Low Pass Filter
Decimation
Applications Software
Figure 8. Mono Microphone Application Circuit
VDD
Audio
Output
SPEAKER
CLOCK
INPUT
Pre-
Amp
ADC
DATA
SELECT
SDI
SDO
CLK
L/R
Serial Port
Noise Shaper
Interpolation
Low Pass Filter
Decimation
VDD
CLOCK
DATA
Applications Software
INPUT
Pre-
Amp
ADC
SELECT
Figure 9. Stereo Microphone Application Circuit
© 2010 Fairchild Semiconductor Corporation
FAN3850A • Rev. 3.0.6
www.fairchildsemi.com
8
Applications Information (Continued)
ꢀ
ꢀ
ꢀ
Diaphragm
Airgap
Electret
ꢀ
Backplate
INPUT
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
FAN3850A
VDD
CLOCK
DATA
SELECT
ꢀ
GND
Figure 10. MIC Element Drawing
A 0.1μF decoupling capacitor is required for VDD. It can
be located inside the microphone or on the PCB very
close to the VDD pin.
A 100ꢂ resistance is recommended on the clock output
of the device driving the FAN3850A to minimize ringing
and improve signal integrity.
Due to high input impedance, care should be taken to
remove all flux used during the reflow soldering process.
For optimal PSR, route a trace to the VDD pin. Do not
place a VDD plane under the device.
© 2010 Fairchild Semiconductor Corporation
FAN3850A • Rev. 3.0.6
www.fairchildsemi.com
9
Physical Dimensions
F
0.03 C
E
A
2X
0.570
A1
0.485
B
D
(Ø0.120)
CU PAD
PIN A1
AREA
(Ø0.220)
SOLDER MASK
0.03 C
RECOMMENDED LAND
PATTERN (NSMD)
2X
TOP VIEW
0.06 C
0.300
0.197 0.013
0.01 C
E
0.254
0.080 0.010
C
SEATING
PLANE
D
SIDE VIEWS
NOTES:
0.005
C A B
A. NO JEDEC REGISTRATION APPLIES.
0.570
Ø0.120 0.010
6X
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
C
B
A
0.485
D. DATUM C, THE SEATING PLANE IS DEFINED
BY THE SPHERICAL CROWNS OF THE BALLS.
(Y) +/-0.018
F
2
1
E. PACKAGE TYPICAL HEIGHT IS 273 MICRONS
23 MICRONS (254-300 MICRONS).
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
(X) +/-0.018
BOTTOM VIEW
G. DRAWING FILENAME: UC006AHrev3.
Figure 11. 6-Ball, Wafer-Level Chip-Scale Package (WLCSP)
FAN3850A External Product Dimensions
Product ID
D
E
X
Y
All options
1.260mm
0.860mm
0.145mm
0.145mm
Ball Composition: SN97.5-Ag2.5
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent version. Package specifications do not expand Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductors online packaging area for the most recent packaging drawings and tape and reel
specifications. http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
FAN3850A • Rev. 3.0.6
www.fairchildsemi.com
10
© 2010 Fairchild Semiconductor Corporation
FAN3850A • Rev. 3.0.6
www.fairchildsemi.com
11
相关型号：
FAN3988IL6X
Power Supply Support Circuit, Fixed, 1 Channel, PDSO6, PLASTIC, MO-252UAAD, MLP-6
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明