FAN5240MTCX_NL [FAIRCHILD]
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| 型号： | FAN5240MTCX_NL |
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FAIRCHILD SEMICONDUCTOR |
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March 2006
FAN5240
Multi-Phase PWM Controller for AMD Mobile Athlon™
and Duron™
Features
General Description
■ CPU Core power: 0.925V to 2.0V output range
■ ±1% reference precision over temperature
■ Dynamic voltage setting with 5-bit DAC
■ 6V to 24V input voltage range
The FAN5240 is a single output 2-Phase synchronous
buck controller to power AMD’s mobile CPU core. The
FAN5240 includes a 5-bit digital-to-analog converter
(DAC) that adjusts the core PWM output voltage from
0.925VDC to 2.0VDC, which may be changed during
operation. Special measures are taken to allow the out-
put to transition with controlled slew rate to comply with
AMD’s Power Now technology. The FAN5240 includes
a precision reference, and a proprietary architecture with
integrated compensation providing excellent static and
dynamic core voltage regulation. The regulator includes
special circuitry which balances the 2 phase currents for
maximum efficiency.
■ 2 phase interleaved switching
■ Active droop to reduce output capacitor size
■ Differential remote voltage sense
■ High efficiency:
>90% efficiency over wide load range
>80% efficiency at light load
■ Excellent dynamic response with Voltage
Feed-Forward and Average Current Mode control
At light loads, when the filter inductor current becomes
discontinuous, the controller operates in a hysteretic
mode, dramatically improving system efficiency. The hys-
teretic mode of operation can be inhibited by the FPWM
control pin.
■ Dynamic duty cycle clamp minimizes inductor current
build up
■ Lossless current sensing on low-side MOSFET or
Precision current sensing using sense resistor
■ Fault protections: Over-voltage, Over-current, and
The FAN5240 monitors the output voltage and issues a
PGOOD (Power-Good) when soft start is completed and
the output is in regulation. A pin is provided to add delay
to PGOOD with an external capacitor.
Thermal Shut-down
■ Controls: Enable, Forced PWM, Power Good, Power
Good Delay
■ QSOP28, TSSOP28
A built-in over-voltage protection (OVP) forces the lower
MOSFET on to prevent the output from exceeding a set
voltage. The PWM controller's overcurrent circuitry moni-
tors the converter load by sensing the voltage drop
across the lower MOSFET. The overcurrent threshold is
set by an external resistor. If precision overcurrent pro-
tection is required, an optional external current-sense
resistor may be used.
Applications
■ AMD Mobile Athlon CPU V
Regulator
CORE
■ Graphic chip V
Regulator
CORE
Ordering Information
Part Number
FAN5240QSC
FAN5240QSCX
FAN5240MTC
FAN5240MTCX
Temperature Range
-10°C to 85°C
Package
QSOP-28
QSOP-28
TSSOP-28
TSSOP-28
Packing
Rails
-10°C to 85°C
Tape and Reel
Rails
-10°C to 85°C
-10°C to 85°C
Tape and Reel
©2006 Fairchild Semiconductor Corporation
FAN5240 Rev. 1.2.0
1
www.fairchildsemi.com
Typical Application
VIN (BATTERY)
= 5 to 24V
VIN
21
C1
C7
C2
+5
D2
VCC
BOOT1
+5
28
25
C3 C4
Q1
C8
HDRV1
24
23
SW1
+5
Phase 1
Q2
Q3
R1
LDRV1
27
R2
PGOOD
EN
19
14
PGND1
ISNS1
26
22
R6
VCORE
C15 C16
VCORE +
VCORE D
C5
18
17
C12 C13 C14
FPWM
12
VID0
VID1
VID2
VID3
VID4
11
10
9
D1
+5
BOOT2
3
VIN
C9
Q4
HDRV2
SW2
8
C6
Q6
4
5
7
Phase 2
SS
C11
20
16
Q5
C10
DELAY
LDRV2
1
R3
R4
ILIM
PGND2
ISNS2
13
15
2
6
AGND
Figure 1. AMD Mobile Athlon/Duron CPU Core Supply
Table 1. BOM for Figure 1
Description
Capacitor 22µF, Ceramic X7R 25V
Capacitor 1µF, Ceramic
Qty
2
Ref.
Vendor
TDK
Part Number
C1, C2
3
C3, C7, C9
C4–C6, C8, C11, C12
C10
Any
Capacitor 0.1µF, Ceramic
Capacitor 0.22µF, Ceramic
Capacitor 270µF, 2V, ESR 15mΩ
10KΩ, 5% Resistor
6
Any
1
Any
4
C13–C16
R1
Panasonic
Any
EEFUE0D271R
2
1KΩ, 1% Resistor
1
R2, R3, R6
R4
Any
56.2KΩ, 1% Resistor
2
Any
Schottky Diode 40V
2
D1, D2
Fairchild
Panasonic
Fairchild
Fairchild
MBR0540
Inductor 1.6µH, 20A, 2.4mΩ
N-Channel SO-8 MOSFET, 11mΩ
N-Channel SO-8 SyncFET™ MOSFET, 6mΩ
1
L1, L2
ETQP6F0R8LFA
FDS6694
1
Q1, Q4
1
Q2, Q3, Q5, Q6
FDS6676S
2
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
Pin Configuration
LDRV2
PGND2
BOOT2
HDRV2
SW2
VCC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LDRV1
PGND1
BOOT1
HDRV1
SW1
2
3
4
5
ISNS2
VID4
6
ISNS1
VIN
7
FAN5240
VID3
8
VID2
SS
9
VID1
PGOOD
VCORE+
VCORED
DELAY
AGND
10
11
12
13
14
VID0
FPWM
ILIM
EN
QSOP-28 or TSSOP-28
θ
= 90°C/W
JA
Pin Assignments
Pin
Pin
Number
Name
Pin Function Description
1
27
LDRV2
LDRV1
Low-Side Drive. The low-side (lower) MOSFET driver output.
2
26
PGND2
PGND1
Power Ground. The return for the low-side MOSFET driver.
3
25
BOOT2
BOOT1
BOOT. The positive supply for the upper MOSFET driver. Connect as shown in Figure 1.
High-Side Drive. The high-side (upper) MOSFET driver output.
Switching node. The return for the high-side MOSFET driver.
4
24
HDRV2
HDRV1
5
23
SW2
SW1
6
22
ISNS2
ISNS1
Current Sense input. Monitors the voltage drop across the lower MOSFET or external
sense resistor for current feedback.
7 –11
12
VID4–VID0 Voltage Identification Code. Input to VID DAC. Sets the output voltage according to the
codes set as defined in Table Figure . These inputs have 1µA internal pull-up.
FPWM
Forced PWM mode. When logic high, inhibits the chip from entering hysteretic operating
mode. If tied low, hysteretic mode will be allowed.
13
14
ILIM
EN
Current Limit. A resistor from this pin to GND sets the current limit.
ENABLE. This pin enables IC operation when either left open, or pulled up to V . Toggling
CC
EN will also reset the chip after a latched fault condition.
15
16
AGND
Analog Ground. This is the signal ground reference for the IC. All voltage levels are
measured with respect to this pin.
DELAY
Power Good / Over-Current Delay. A capacitor to GND on this pin delays the PGOOD
from going high as well delaying the over-current shutdown.
18
17
VCORE+ VCORE Output Sense. Differential sensing of the output voltage. Used for regulation as
VCORE– well as PGOOD, under-voltage and over-voltage protection and monitoring. A resistor in
series with this VCORE+ sets the output voltage droop.
3
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
Pin Assignments (Continued)
Pin
Pin
Number
Name
Pin Function Description
19
PGOOD
Power Good Flag. An open-drain output that will pull LOW when the core output below
825mV. PGOOD delays its low to high transition for a time determined by CDELAY when
VCORE rises above 875mV.
20
SS
Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during
initialization as well as in operation. This pin is used as the reference against which the
output is compared. During initialization, this pin is charged with a 25µA current source.
Once this pin reaches 0.5V, its function changes, and it assumes the value of the voltage as
set by the VID programming. The current driving this pin is then limited to ±500µA, that
together with C sets a controlled slew rate for VID code changes.
SS
21
28
V
Input voltage from battery. This voltage is used by the oscillator for feed-forward
compensation of input voltage variation.
IN
V
V
. This pin powers the chip. The IC starts to operate when voltage on this pin exceeds
CC
CC
4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling).
Absolute Maximum Ratings
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The
device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables
are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the
conditions for actual device operation.
Parameter
Min.
Typ.
Max.
6.5
27
Units
V
V
V
Supply Voltage
CC
V
IN
BOOT, SW, HDRV Pins
BOOT to SW
33
V
6.5
V
All Other Pins
–0.3
–10
–65
V
+ 0.3
V
CC
Junction Temperature (T )
150
°C
°C
°C
J
Storage Temperature
150
300
Lead Soldering Temperature, 10 seconds
Recommended Operating Conditions
Parameter
Conditions
Min.
4.75
6
Typ.
Max.
Units
Supply Voltage V
5
5.25
24
V
V
CC
IN
Supply Voltage V
Ambient Temperature (T )
–20
85
°C
A
4
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
Electrical Specifications
(V = 5V, V = 6V–24V, and T = recommended operating ambient temperature range using circuit of Figure 1,
CC
IN
A
unless otherwise noted.)
Parameter
Conditions
Min.
Typ.
Max.
Units
Power Supplies
V
Current
Operating, C = 10pF
2
10
mA
µA
µA
µA
V
CC
L
Shut-down (EN=0)
1
V
Current
Operating
25
IN
Shut-down (EN=0)
1
UVLO Threshold
Rising V
4.3
3.8
4.45
3.95
4.6
4.10
CC
Falling V
V
CC
Regulator/Control Functions
Output voltage
per Table Figure
0.925
2.00
V
dB
MHz
V/µS
µA
V
Error Amplifier Gain
Error Amplifier GBW
Error Amplifier Slew Rate
VCORE+ Input Current
ILIM Voltage
86
2.7
1
25
30
35
R
C
= 30KΩ
0.89
0.91
ILIM
ILIM T
= 22nF
1.16
2.35
2
mS
V
HOLDOFF
DELAY
Over-voltage Threshold
Over-voltage Protection delay
EN, input threshold
2.2
2
2.5
0.8
±5
µS
V
Logic LOW
Logic HIGH
V
Phase to Phase current mismatch
IC contribution only
%
Guaranteed by design
Over-Temperature Shut-down
Over-Temperature Hysteresis
150
25
°C
°C
(1)
Output Drivers
HDRV Output Resistance
Sourcing
Sinking
3.8
1.6
3.8
0.8
5
3
Ω
Ω
Ω
Ω
LDRV Output Resistance
Sourcing
Sinking
5
1.5
Oscillator
Frequency
255
300
2
345
KHz
V
Ramp Amplitude, pk–pk
Ramp Offset
Ramp Gain
V
= 16V
IN
0.5
125
V
RampAmplitude
----------------------------------------------
VIN
mV/V
Reference, DAC and Soft-Start
VID input threshold
Logic LOW
Logic HIGH
0.8
V
V
2.0
VID pull-up current
to V
1
µA
%
CC
DAC output accuracy
–1
20
1
Soft Start Charging current (I
)
V
V
< 90% of Programmed output
> 90% of Programmed output
27
34
µA
µA
SS
SS
350
500
650
SS
5
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FAN5240 Rev. 1.2.0
Electrical Specifications (Continued)
Parameter
Conditions
Min.
Typ.
Max.
Units
PGOOD
VCORE Lower Threshold
Falling Edge
Rising Edge
Low to High, C
785
835
825
875
12
865
915
mV
mV
mS
V
PGOOD Output Delay
PGOOD Output Low
Leakage Current
= 22nF
DELAY
I
= 4mA
0.5
1
PGOOD
V
= 5V
µA
PULLUP
Note:
1. Guaranteed by slew rate testing.
5V
VDD
CBOOT
BOOT
EN
VIN
Q1
POR/UVLO
SS
HYST
HDRV
SW
HYST
VCORE
L OUT
+
VOUT'
DAC
Q2
COUT
FPWM
Soft Start &
OVP
VDD
PGOOD
VIN
LDRV
Q
R
PWM
PGND
OSC
RAMP CLK
S
S/H
PWM/HYST
PWM
EA1
DUTY
CYCLE
CLAMP
RSENSE1
ILIM
det.
MODE
ISNS1
ISNS2
A
CURRENT
PROCESSING
RSENSE2
ISNS1-ISNS2
ISNS1+ISNS2
5
ISNS1 ISNS2
A2
VCORE+
A1
VOUT'
30µA
ILIM
B
VCORE-
TO PH 2
MODULATOR
ISNS2-ISNS1
1K
R6
Figure 2. IC Block Diagram
6
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FAN5240 Rev. 1.2.0
Circuit Description
Overview
Output Voltage Programming
The FAN5240 is a 2-phase, single output power man-
agement IC, which supplies the low-voltage, high-current
power to modern processors for notebook PCs. Using
very few external components, the IC controls a preci-
sion programmable synchronous buck converter driving
external N-Channel power MOSFETs. The output volt-
age is adjustable from 0.925V to 2.0V by changing the
DAC (VID) code settings (see Table 2). The output volt-
age of the core converter can be changed on-the-fly with
programmable slew rate, which meets a key requirement
of AMD's Mobile Athlon/Duron processors.
The output voltage of the converter is programmed by an
internal DAC in discrete steps of 25mV from 0.925V to
1.300V and then in 50mV steps from 1.300V to 2.00V:
Table 2. Output voltage VID
VID4 VID3 VID2 VID1 VID0 VOUT to CPU
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0.000
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
0.000
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
The converter can operate in two modes: fixed frequency
PWM, and variable frequency hysteretic depending on
the load. At loads lower than the point where filter induc-
tor current becomes discontinuous, hysteretic mode of
operation is activated. Switchover from PWM to hyster-
etic operation at light loads improves the converter’s effi-
ciency and prolongs battery run time. As the filter
inductor resumes continuous current, the PWM mode of
operation is restored.
1 = Logic High or open, 0 = Logic Low
VID0–4 pins will assume a logic 1 level if left open as
each input is pulled up with a 1µA internal current
source.
7
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
The PGOOD delay (TDLY, Figure 3) can be programmed
with a capacitor to GND on pin 16 (C ):
Initialization, Soft Start and PGOOD
DELAY
Assuming EN is high, FAN5240 is initialized when power
is applied on V . Should V
threshold, an internal Power-On Reset function disables
the chip.
drop below the UVLO
CC
CC
C
DELAY(in nF) = 1.8 × TDLY(in mS)
(3)
For 12mS of TDLY, C = 22nF.
DELAY
The IC attempts to regulate the VCORE output accord-
ing to the voltage that appears on the SS pin (V ). Dur-
C
is typically chosen to provide 1mS of “blanking”
SS
DELAY
ing start-up of the converter, this voltage is initially 0, and
rises linearly to 90% of the VID programmed voltage via
for the over-current shut-down (see Over-Current Sens-
ing, on page 12).
the current supplied to C by the 25µA internal current
source. The time it takes to reach this threshold is:
SS
The following conditions set the PGOOD pin low:
1. Under-voltage – VCORE is below a fixed voltage.
0.9 × VVID × CSS
(1)
2. Chip shut-down due to over-temperature or
over-current as defined below.
T90% = --------------------------------------------
25
where T
is in seconds if C is in µF.
90%
SS
Converter Operation (see Figure 2)
At that point, the current source changes to 500µA,
which establishes the slew rate of voltage changes at the
output in response to changes in VID.
At nominal current the converter operates in fixed fre-
quency PWM mode. The output voltage is compared
with a reference voltage set by the DAC, which appears
on the SS pin. The derived error signal is amplified by an
internally compensated error amplifier and applied to the
inverting input of the PWM comparator. To provide output
voltage droop for enhanced dynamic load regulation, a
signal proportional to the output current is added to the
voltage feedback signal at the + input of A1. Since the
processor specifies a +100mV/-50mV tolerance on
VCORE, a fixed positive offset of 30mV is created with a
30µA current source and external 1K resistor. Phase
load balancing is accomplished by adding a signal pro-
portional to the difference of the two phase currents
before the error amplifier (at nodes A and B). This feed-
back scheme in conjunction with a PWM ramp propor-
tional to the input voltage allows for fast and stable loop
response over a wide range of input voltage and output
current variations. For the sake of efficiency and maxi-
mum simplicity, the current sense signal is derived from
the voltage drop across the lower MOSFET during its
conduction time. This current sense signal is used to set
droop levels as well as for phase balancing and current
limiting.
This dual slope approach helps to provide safe rise of
voltages and currents in the converters during initial
start-up and at the same time sets a controlled speed of
the core voltage change when the processor commands
to do so.
1.5V
1.35V
SS
EN
TDLY
PGOOD
Figure 3. Soft-Start function
C
typically is chosen based on the slew rate desired in
SS
response to a VID change. For example, if the spec
requires a 500mV step to occur in 100µS:
The PWM controller has a built-in duty cycle clamp in the
path from the error amplifier to the PWM comparator.
During a severe load step, the output signal from the
error amp can go to its rail, pushing the duty cycle to
almost 100% for a significant amount of time. This could
cause a severe rise in the inductor current, especially at
high battery voltage, and lead to a long recovery time or
even failure of the converter. To prevent this, the output
of the error amplifier is clamped to a fixed value after two
clock cycles if a large output voltage excursion is
detected. Sensitivity of this circuit is set in such a way as
not to affect the PWM control during transients normally
expected from the load.
ISS
500µA
-------------------
500mV
(2)
------------------
CSS
=
∆t =
100µS = 0.1µF
∆VDAC
Assuming VID is set to 1.5V, with this value of C , the
time for the output voltage to rise to 0.9 of V
using equation 1:
SS
is found
VID
1.35V × 0.1
T90% = ------------------------------ = 5.4mS
25
The transition from 90% VID to 100% VID occupies 0.5%
of the total soft-start time, so TSS is essentially T
.
90%
8
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
increase causes an instantaneous decrease in the
output voltage due to the voltage drop on the output
capacitor ESR. If the load causes the output voltage (as
presented at VSNS) to drop below the hysteretic regula-
tion level (20mV below VREF), the mode is changed to
PWM on the next clock cycle. This insures the full power
required by the increase in output current.
Operation Mode Control
The mode-control circuit changes the converter’s mode
of operation from PWM to Hysteretic and visa versa,
based on the voltage polarity of the SW node when the
lower MOSFET is conducting and just before the upper
MOSFET turns on. For continuous inductor current, the
SW node is negative when the lower MOSFET is con-
ducting and the converters operate in fixed-frequency
PWM mode as shown in Figure 4. This mode of opera-
tion achieves high efficiency at nominal load. When the
load current decreases to the point where the inductor
current flows through the lower MOSFET in the ‘reverse’
direction, the SW node becomes positive, and the mode
is changed to hysteretic, which achieves higher effi-
ciency at low currents by decreasing the effective switch-
ing frequency.
In hysteretic mode, the PWM comparator and the error
amplifier that provide control in PWM mode are inhibited
and the hysteretic comparator is activated. In hysteretic
mode the low side MOSFET is operated as a synchro-
nous rectifier, where the voltage across V
is moni-
DS(ON)
tored, and its gate switched off when V
) goes
DS(ON
positive (current flowing back from the load) blocking
reverse conduction
The hysteretic comparator initiates a PFM signal to turn
on HDRV when the output voltage (at VSNS) falls below
the lower threshold (10mV below VREF) and terminates
the PFM signal when VSNS rises over the higher thresh-
old (5mV above VREF).
To prevent accidental mode change or “mode chatter”
the transition from PWM to Hysteretic mode occurs when
the SW node is positive for eight consecutive clock
cycles (see Figure 4). The polarity of the SW node is
sampled at the end of the lower MOSFET's conduction
time. At the transition between PWM and hysteretic
mode both the upper and lower MOSFETs are turned
off. The phase node will ‘ring’ based on the output induc-
tor and the parasitic capacitance on the phase node and
settle out at the value of the output voltage.
The switching frequency is primarily a function of:
1. Spread between the two hysteretic thresholds
2.
I
LOAD
3. Output Inductor and Capacitor ESR
A transition back to PWM (Continuous Conduction Mode
or CCM) mode occurs when the inductor current rises
sufficiently to stay positive for 8 consecutive cycles. This
occurs when:
The boundary value of inductor current, where current
becomes discontinuous, can be estimated by the follow-
ing expression.
(VIN – V
)VOUT
ILOAD(DIS) = ----------------------O----U----T-------------------
∆VHYSTERESIS
(4)
(5)
ILOAD(CCM) = ----------------------------------------
2FSWLOUTVIN
2 ESR
where ∆V
series resistance of C
= 15mV and ESR is the equivalent
Hysteretic Mode
HYSTERESIS
.
OUT
Conversely, the transition from Hysteretic mode to PWM
mode occurs when the SW node is negative for 8 con-
secutive cycles.
Because of the different control mechanisms, the value
of the load current where transition into CCM operation
takes place is typically higher compared to the load level
at which transition into hysteretic mode occurs.
A sudden increase in the output current will also cause a
change from hysteretic to PWM mode. This load
VCORE
PWM Mode
Hysteretic Mode
IL
0
1
2
3
4
5
6
7
8
VCORE
Hysteretic Mode
3
PWM Mode
IL
0
1
2
4
5
6
7
8
Figure 4. Transitioning between PWM and Hysteretic Mode
9
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
With Active Droop, the output voltage varies with the load
as if a resistor were connected in series with the con-
verter’s output, in other words, it's effect is to raise the
output resistance of the converter.
Current Processing Section
The following discussion refers to Figure 6.
Setting RSENSE
Each phase current is sampled about 200nS after the
SW node crosses 0V. For proper converter operation,
choose an RSENSE value of:
1.2
VDROOP
RDS(ON) • IMAX
RSENSE = ----------------------------------------
40µA
which is about 1K for the components in Figure 1.
Active Droop
ILOAD
IMAX
The core converter incorporates a proprietary output
voltage droop method for optimum handling of fast load
transients found in modern processors.
Figure 5. Active Droop
To get the most from the Active Droop, its magnitude
should be scaled to match the output capacitor’s ESR
voltage drop.
“Active droop” or voltage positioning is now widely used
in the computer power applications. The technique is
based on raising the converter voltage at light load in
anticipation of a step increase in load current, and con-
versely, lowering VCORE in anticipation of a step
decrease in load current.
VDROOP = IMAX × ESR
(6)
Active Droop allows the size and cost of the output
capacitors required to handle CPU current transients to
be reduced. The reduction may be almost a factor of 2
when compared to a system without Active Droop.
S/H
B-A
ISNS1-ISNS2
V to I
A
B
RSENSE
ISNS2
ISNS1
Σ
ISNS1
in +
in D
ISNS2-ISNS1
A-B
ISNS2
5
ISNS1
5
ISNS1
8
LDRV1
PGND1
To A1 (+)
RILIM
ILIM
0.9V
2.5V
I2 =
ILIM
ILIM det. 1
ILIM mirror
Figure 6. Current Limit and Active Droop Circuits
10
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
Additionally, the CPU power dissipation is also slightly
reduced as it is proportional to the applied voltage
squared and even slight voltage decrease translates to a
measurable reduction in power dissipated.
The current through each R
resistor (ISNS) is
SENSE
sampled shortly after LDRV is turned on. That current is
held for the remainder of the cycle, and then injected to
produce an offset to VCORE+ through the external 1K
resistor (R6 in Figure 1). This creates a voltage at the
input to the error amplifier that rises with increasing
current, causing the regulator’s output to droop as the
current increases.
ILOAD
upper lim
Vout
I
LOAD • RDS(ON)
(no droop)
VDROOP = -------------------------------------------
3 • RSENSE
(7)
VES
lower lim
upper lim
Gate Driver
VES
Vout
droop ≈ ESR
The gate control logic translates the internal PWM con-
trol signal into the MOSFET gate drive signals providing
necessary amplification, level shifting and shoot-through
protection. Also, it has functions that help optimize the IC
performance over a wide range of operating conditions.
Since MOSFET switching time can vary dramatically
from type to type and with the input voltage, the gate
control logic provides adaptive dead time by monitoring
the gate-to-source voltages of both upper and lower
MOSFETs. The lower MOSFET drive is not turned on
until the gate-to-source voltage of the upper MOSFET
has decreased to less than approximately 1V. Similarly,
the upper MOSFET is not turned on until the gate-to-
source voltage of the lower MOSFET has decreased to
less than approximately 1V. This allows a wide variety of
upper and lower MOSFETs to be used without a concern
for simultaneous conduction, or shoot-through.
lower lim
Figure 7. Effect of Active Droop on ESR
The processor regulation window including transients is
specified as +100mV…–50mV. To accommodate the
droop, the output voltage of the converter is raised by
about 30mV at no load.
The converter response to the load step is shown in
Figure 8. At zero load current, the output voltage is
raised ~30mV above nominal value of 1.5V. When the
load current increases, the output voltage droops down
approximately 55mV. Due to use of Active Droop, the
converter’s output voltage adaptively changes with the
load current allowing better utilization of the regulation
window.
There must be a low-resistance, low-inductance path
between the driver pin and the MOSFET gate for the
adaptive dead-time circuit to work properly. Any delay
along that path will subtract from the delay generated by
the adaptive dead-time circit and a shoot-through condi-
tion may occur.
Frequency Loop Compensation
Due to the implemented current mode control, the modu-
lator has a single pole response with -1 slope at fre-
quency determined by load:
1
FPO = -----------------------
(8)
2πROCO
where R is load resistance, C is load capacitance. For
O
O
this type of modulator Type 2 compensation circuit is
usually sufficient. To reduce the number of external com-
ponents and simplify the design task, the PWM controller
has an internally compensated error amplifier. Figure 9
shows a Type 2 amplifier and its response along with the
responses of a current mode modulator and of the con-
verter. The Type 2 amplifier, in addition to the pole at the
origin, has a zero-pole pair that causes a flat gain region
at frequencies between the zero and the pole.
Figure 8. Converter Response to 5A Load Step
11
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
Over-Current Sensing (see Figure 10)
C2
When the circuit's current limit signal (“ILIM det” as
shown in Figure 6) goes high, a pulse-skipping circuit is
activated and a 16-clock cycle counter is started. HDRV
will be inhibited as long as the sensed current is higher
than the ILIM value. This limits the current supplied by
the DC input.
R2 C1
R1
VIN
–
+
REF
EAOut
RESET
Clock
16 Clock
Counter and
Logic
Q TIMER
START
ILIM det. 1
ILIM det. 2
Modulator
Shut-down
18
14
0
DELAY
FP0
FZ
FP
Figure 10. Over-Current Shut-Down Delay Logic
If ILIM det goes high during counts 9–16 of the counter,
the overcurrent delay timer is started and the 16-clock
counter starts again. This timer delays the shut-down of
Figure 9. Compensation
the chip and its time is a function of the value of C
.
1
DELAY
FZ = --------------------- = 6 kHz
2πR2C1
(9a)
(9b)
C
DELAY(in nF)
HOLDOFF(in mS) = ---------------------------------------
19
T
(10)
1
FP = --------------------- = 600 kHz
2πR2C2
Over-current must detected at least once during the first
nd
8 clock cycles and once during the 2 8 clock cycles of
This region is also associated with phase ‘bump’ or
reduced phase shift. The amount of phase shift reduction
depends on how wide the region of flat gain is and has a
maximum value of 90°. To further simplify the converter
compensation, the modulator gain is kept independent of
the input voltage variation by providing feed-forward of
the 16-cycle counter for the timer to continue timing. If
the over-current condition does not occur at least once
per 8 clock counts during any clock counter cycle while
the timer is high, the timer and the over-current detection
circuit are reset, preventing shutdown. The clock counter
coutinues to count and look for ILIM det pulses in this
manner until either:
V
to the oscillator ramp.
IN
The zero frequency, the amplifier high frequency gain
and the modulator gain are chosen to satisfy most typical
applications. The crossover frequency will appear at the
point where the modulator attenuation equals the ampli-
fier high frequency gain. The only task that the system
designer has to complete is to specify the output filter
capacitors to position the load main pole somewhere
within one decade lower than the amplifier zero fre-
quency. With this type of compensation plenty of phase
margin is easily achieved due to zero-pole pair phase
‘boost’.
1. The IC is shut-down because the timer timed out:
If the timer pulse is allowed to finish by timing out,
the IC is shut-down and can only be restarted by
removing power or toggling the EN pin.
2. ILIM det does not go high at least once per 8 clock
counts. In this case, the timer and over-current
shutdown logic are reset, and a chip shut-down is
averted.
PGOOD will go LOW if the IC shuts down from over-
current.
Conditional stability may occur only when the main load
pole is positioned too much to the left side on the fre-
quency axis due to excessive output filter capacitance. In
this case, the ESR zero placed within the 10kHz...50kHz
range gives some additional phase ‘boost’. Fortunately,
there is an opposite trend in mobile applications to keep
the output capacitor as small as possible.
Setting the Current Limit
ISNS is compared to the current established when a
0.9V internal reference drives the ILIM pin. The threshold
is determined at the point when the
I
LOAD • RDS(ON)
ISNS = -------------------------------------------
RSENSE
ISNS 0.9V
. Since
-------------- --------------
>
8
RILIM
Protection
therefore,
The converter output is monitored and protected against
short circuit (over-current), and over-voltage conditions.
8 • (RSENSE
)
0.9V
ILIMIT
-------------- -----------------------------------
RILIM
=
×
(11)
RDS(ON)
12
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
Since the tolerance on the current limit is largely depen-
dent on the ratio of the external resistors it is fairly accu-
rate if the voltage drop on the Switching Node side of
The over-current comparator is sampled just after LDRV
is turned on, when the current is near its peak in the
cycle. Assuming 20% inductor ripple current, we can
then add 1/2 of the ripple current, or 10%. An additional
factor of 1.2 accounts for the inaccuracy in the initial
R
is an accurate representation of the load current.
SENSE
When using the MOSFET as the sensing element, the
variation of R causes proportional variation in the
(room temperature) R
of the MOSFETs with an
DS(ON)
DS(ON)
ISNS. This value not only varies from device to device,
but also has a typical junction temperature coefficient of
about 0.4% / °C (consult the MOSFET datasheet for
actual values), so the actual current limit set point will
decrease propotional to increasing MOSFET die temper-
additional factor of 1.4 to accommodate the rise of the
MOSFET R when operating with T @ 125°C.
DS(ON)
J
With a maximum load current of 12.5A/phase, the target
for I (per phase) would be:
LIMIT
ature. The same discussion applies to the V
lation.
calcu-
20A
LIMIT > 1.1 • 1.2 • 1.4 • 12.5A + ---------- ≈ 42A
DROOP
I
(12c)
2
so using equation 11, with R
= 3mΩ for the 2
DS(ON)
parallel FDS6688 MOSFETs, R
≈ 56K:
ILIM
Q2
LDRV
Over-Voltage Protection
RSENSE
Should the output voltage exceed 2.35V due to an upper
MOSFET failure, or for other reasons, the overvoltage
protection comparator will force the LDRV high. This
action actively pulls down the output voltage and, in the
event of the upper MOSFET failure, will eventually blow
the battery fuse. As soon as the output voltage drops
below the threshold, the OVP comparator is disengaged.
ISNS
21
PGND
22
This OVP scheme provides a ‘soft’ crowbar function
which helps to tackle severe load transients and does
not invert the output voltage when activated—a common
problem for OVP schemes with a latch.
Figure 11. Improving current sensing accuracy
More accurate sensing can be achieved by using a resis-
tor (R1) instead of the R
of the FET as shown in
DS(ON)
Figure 11. This approach causes higher losses, but
Over-Temperature Protection
yields greater accuracy in both V
and I
. R1 is
DROOP
LIMIT
a low value (e.g. 10mΩ) resistor.
The chip incorporates an over temperature protection
circuit that shuts the chip down when a die temperature
of 150°C is reached. Normal operation is restored at die
temperature below 125°C with internal Power On Reset
asserted, resulting in a full soft-start cycle.
The current limit (I
) set point chosen needs to
LIMIT
accommodate ripple current, slew current, and variability
in the MOSFET's R
.
DS(ON)
dV
-------
I
LIMIT > ILOAD + C
(12a)
OUT dt
dV
-------
) is the current required for the
Slew current (
C
OUT dt
output voltage to slew upwards during VID code
changes, since the circuit will limit the regulator’s output
current by pulse skipping when I
dV
is reached. The
LIMIT
-------
term we used earlier in the discussion (set up by the
dt
C
) was 500mV/100µS or 5V/mS. Assuming C
of
SS
OUT
4000µF, the current required to slew C
at this rate is:
(12b)
OUT
dV
-------
C
= 4mF • 5V/mS = 20A
OUT dt
which is contributed roughly equally from each phase,
therefore, 1/2 of the slew current comes from a single
phase.
13
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
Design and Component Selection Guidelines
As an initial step, define operating voltage range and
minimum and maximum load currents for the controller.
For this discussion,
The load transient requirements are a function of the
slew rate (di/dt) and the magnitude of the transient load
current. Modern microprocessors produce transient load
rates in excess of 10A/µs. High frequency ceramic
capacitors placed beneath the processor socket initially
supply the transient and reduce the slew rate seen by
the bulk capacitors. The bulk capacitor values are gener-
ally determined by the total allowable ESR rather than
actual capacitance requirements.
I
Max
25A
OUT
V
V
5.5V to 21V
0.925V to 2 V
IN
OUT
Output Inductor Selection
High frequency decoupling capacitors should be placed
as close to the processor power pins as physically possi-
ble. Consult with the processor manufacturer for specific
decoupling requirements. Use only specialized low-ESR
electrolytic capacitors intended for switching-regulator
applications for the bulk capacitors. The bulk capacitor’s
ESR will determine the output ripple voltage and the ini-
tial voltage drop after a transient. In most cases, multiple
electrolytic capacitors of small case size perform better
than a single large case capacitor.
The minimum practical output inductor value is the one
that keeps inductor current just on the boundary of con-
tinuous conduction at some minimum load. The industry
standard practice is to choose the ripple current to be
somewhere from 15% to 35% of the nominal current. At
light load, the ripple current also determines the point
where the converter will automatically switch to hyster-
etic mode of operation (I ) to sustain high efficiency.
MIN
The following equations help to choose the proper value
of the output filter inductor.
Input Capacitor Selection
∆VOUT
The input capacitor should be selected by its ripple cur-
rent rating. For a 2 phase converter, the RMS currents is
calculated:
∆I = 2 × IMIN = ------------------
,
ESR
where ∆I is the inductor ripple current, which we will
choose for 20% of the full load current (12.5A in each
IPK
IRMS
=
2D – 4D2
-------
(14)
phase) and ∆V
is the maximum output ripple voltage
2
OUT
allowed.
This equation produces the worst case value at maxi-
V
IN – VOUT VOUT
mum duty cycle. For our example, that occurs when V
(13)
IN
----------------------------- --------------
L =
×
= 5.5V and V
= 2V. For 25A maximum output the
F
SW × ∆I
VIN
OUT
maximum RMS current at C :
IN
for this example we’ll use:
= 20V, V = 1.5V
IRMS(MAX) = 5.6A
V
IN
OUT
∆I = 20% *12.5A (per phase) = 2.5A
= 300KHz.
Power MOSFET Selection
F
SW
For the example in the following discussion, we will be
selecting components for:
Therefore,
L ≈ 1.8µH
V
V
from 5V to 20V
IN
The inductor's current rating should be chosen per the
calculated above. Some transient currents over the
= 1.5V @ I
= 12.5A/phase
OUT
LOAD(MAX)
I
LIMIT
inductor current rating may be tolerable if the inductor’s
dL
The FAN5240 converter’s output voltage is very low
with respect to the input voltage, therefore the Lower
MOSFET (Q2) is conducting the full load current for most
of the cycle. Therefore, Q2 should be selected to be a
------
saturation characteristic
is sufficiently “soft”.
dI
Output Capacitor Selection
MOSFET with low R
losses.
to minimize conduction
DS(ON)
The output capacitor serves two major functions in a
switching power supply. Along with the inductor it filters
the sequence of pulses produced by the switcher, and it
supplies the load transient currents. The filtering require-
ments are a function of the switching frequency and the
ripple current allowed, and are usually easy to satisfy in
high frequency converters.
In contrast, Q1 is on for a maximum of 20% (when V
=
IN
5V) of the cycle, and its conduction loss will have less of
an impact. Q1, however, sees most of the switching
losses, so Q1’s primary selection criteria should be gate
charge (Q
).
G(SW)
14
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
impedance of the driver and the Q
of the MOSFET.
High-Side Losses
G(SW)
Since most of t occurs when V = V we can use a
S
GS
SP
constant current assumption for the driver to simplify the
CISS
CRSS
CISS
calculation of t :
S
VDS
QG(SW)
QG(SW)
-------------------- -----------------------------------------------------
tS
=
≈
(16)
IDRIVER
VDD – VSP
------------------------------------------------
DRIVER + RGATE
R
For the high-side MOSFET, V = V , which can be as
DS
IN
high as 20V in a typical portable application. Q2, how-
ever, switches on or off with its parallel shottky diode
ID
conducting, therefore V ≈ 0.5V. Since P
is propor-
DS
SW
tional to V , Q2's switching losses are negligible and
DS
QGS
QGD
VGS
we can select Q2 based on R
only.
DS(ON)
4.5V
Care should also be taken to include the delivery of the
MOSFET's gate power ( P ) in calculating the power
dissipation required for the FAN5240:
VSP
VTH
GATE
QG(SW)
t1
CISS = CGS || CGD
t2
t3
t4
t5
PGATE = QG × VDD × FSW
(17)
Low-Side Losses
Conduction losses for Q2 are given by:
Figure 12. Switching losses and Q
G
PCOND = (1 – D) × IOUT2 × RDS(ON)
VIN
(18)
5V
CGD
RGATE
where RDS(ON) is the RDS(ON) of the MOSFET at the
VOUT
RD
HDRV
SW
highest operating junction temperature and D = -------------- is
19
20
G
VIN
MIN
CGS
the minimum duty cycle for the converter. Since D
is
5% for portable computers, (1–D) ≈ 1, further simplifying
the calculation.
Figure 13. Drive Equivalent Circuit
The maximum power dissipation (P
) is a function
D(MAX)
of the maximum allowable die temperature of the low-
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1’s switching losses,
as can be seen by Figure 12, are given by:
side MOSFET, the θ , and the maximum allowable
ambient temperature rise:
J-A
TJ(MAX) – TA(MAX)
PD(MAX) = ------------------------------------------------
θJ – A
PUPPER = PSW + PCOND
(15a)
(15b)
θ
, depends primarily on the amount of PCB area
V
DS × IL
J-A
---------------------
PSW
=
× 2 × tS FSW
that can be devoted to heat sinking (see FSC app note
AN-1029 for SO-8 MOSFET thermal information).
2
VOUT
× IOUT2 × RDS(ON)
(15c)
--------------
PCOND
=
VIN
where R
is @T
and:
DS(ON)
J(MAX)
t
is the switching period (rise or fall time) and is pre-
S
dominantly the sum of t2, t3 (Figure 12), a function of the
15
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
Layout Considerations
Switching converters, even during normal operation, pro-
duce short pulses of current which could cause substan-
tial ringing and be a source of EMI if layout constrains
are not observed.
Keep the wiring traces from the IC to the MOSFET gate
and source as short as possible and capable of handling
peak currents of 2A. Minimize the area within the gate-
source path to reduce stray inductance and eliminate
parasitic ringing at the gate.
There are two sets of critical components in a DC-DC
converter. The switching power components process
large amounts of energy at high rate and are noise gen-
erators. The low power components responsible for bias
and feedback functions are sensitive to noise.
Locate small critical components like the soft-start
capacitor and current sense resistors as close as possi-
ble to the respective pins of the IC.
The FAN5240 utilizes advanced packaging technology
that will have lead pitch of 0.6mm. High performance
analog semiconductors utilizing narrow lead spacing
may require special considerations in PWB design and
manufacturing. It is critical to maintain proper cleanliness
of the area surrounding these devices. It is not recom-
mended to use any type of rosin or acid core solder, or
the use of flux in either the manufacturing or touch up
process as these may contribute to corrosion or enable
electromigration and/or eddy currents near the sensitive
low current signals. When chemicals such as these are
used on or near the PWB, it is suggested that the entire
PWB be cleaned and dried completely before applying
power.
A multi-layer printed circuit board is recommended. Ded-
icate one solid layer for a ground plane. Dedicate
another solid layer as a power plane and break this plane
into smaller islands of common voltage levels.
Notice all the nodes that are subjected to high dV/dt volt-
age swing such as SW, HDRV and LDRV, for example.
All surrounding circuitry will tend to couple the signals
from these nodes through stray capacitance. Do not
oversize copper traces connected to these nodes. Do not
place traces connected to the feedback components
adjacent to these traces. It is not recommended to use
High Density Interconnect Systems, or micro-vias on
these signals. The use of blind or buried vias should be
limited to the low current signals only. The use of normal
thermal vias is left to the discretion of the designer.
16
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
Mechanical Dimensions
28-Pin QSOP
Notes:
Inches
Millimeters
Symbol
Notes
1. Symbols are defined in the "MO Series Symbol List" in
Section 2.2 of Publication Number 95.
Min.
Max.
Min.
Max.
A
A1
A2
B
C
D
E
e
0.053
0.004
-
0.069
0.010
0.061
0.012
0.010
0.394
0.157
1.35
0.10
-
1.75
0.25
1.54
0.30
0.25
10.00
3.98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusions shall not exceed
0.25mm (0.010 inch) per side.
0.008
0.007
0.386
0.150
0.20
0.18
9.81
3.81
9
4. Dimension "E" does not include interlead flash or
protrusions. Interlead flash and protrusions shall not
exceed 0.25mm (0.010 inch) per side.
3
4
5. The chamber on the body is optional. If it is not present,
a visual index feature must be located within the
crosshatched area.
0.025 BSC
0.635 BSC
H
h
0.228
0.244
5.80
0.26
0.41
6.19
0.49
1.27
0.0099 0.0196
5
6
7
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the maximum number of terminals.
0.016
0.050
L
N
α
28
28
8. Terminal numbers are shown for reference only.
0°
8°
0°
8°
9. Dimension "B" does not include dambar protrusion.
Allowable dambar protrusion shall be 0.10mm (0.004
inch) total in excess of "B" dimension at maximum
material condition.
10. Controlling dimension: INCHES. Converted millimeter
dimensions are not necessarily exact.
D
E
H
C
A1
A
A2
α
SEATING
PLANE
– C –
L
B
LEAD COPLANARITY
ccc C
e
17
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
Mechanical Dimensions (Continued)
28-Pin TSSOP
9.7 ± 0.1
0.51 TYP
28
15
– B –
0.2
B A
0.65
0.42
14
ALL Lead Tips
PIN # 1 IDENT
LAND PATTERN RECOMMENDATION
1.2 MAX
0.1 C
+0.15
–0.10
0.90
See Detail A
ALL LEAD TIPS
0.09–0.20
– C –
0.10 ± 0.05
0.65
0.19–0.30
0.13
A B
C
12.00° Top & Botom
R0.16
R0.31
GAGE PLANE
.025
DIMENSIONS ARE IN MILLIMETERS
0°–8°
0.61 ± 0.1
NOTES:
SEATING PLANE
A. Conforms to JEDEC registration MO-153, variation AB,
Ref. Note 6, dated 7/93.
1.00
B. Dimensions are in millimeters.
C. Dimensions are exclusive of burrs, mold flash, and tie bar extensions.
D Dimensions and Tolerances per ANsI Y14.5M, 1982
DETAIL A
18
www.fairchildsemi.com
FAN5240 Rev. 1.2.0
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
FAST®
FASTr™
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PowerTrench®
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SuperSOT™-8
SyncFET™
TCM™
ISOPLANAR™
LittleFET™
MICROCOUPLER™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
ActiveArray™
Bottomless™
Build it Now™
CoolFET™
CROSSVOLT™
DOME™
EcoSPARK™
E2CMOS™
EnSigna™
FACT™
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
µSerDes™
ScalarPump™
SILENT SWITCHER®
SMART START™
SPM™
TinyLogic®
TINYOPTO™
TruTranslation™
UHC™
HiSeC™
I2C™
MSXPro™
OCX™
OCXPro™
UltraFET®
UniFET™
VCX™
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ImpliedDisconnect™
IntelliMAX™
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OPTOPLANAR™
PACMAN™
POP™
Wire™
FACT Quiet Series™
Across the board. Around the world.™
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FAIRCHILD SEMICONDUCTOR RESERVESTHE RIGHTTO MAKE CHANGES WITHOUTFURTHER NOTICETOANY
PRODUCTS HEREINTO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOTASSUMEANYLIABILITY
ARISING OUTOFTHEAPPLICATION OR USE OFANYPRODUCTOR CIRCUITDESCRIBED HEREIN; NEITHER DOES IT
CONVEYANYLICENSE UNDER ITS PATENTRIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILDíS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUTTHE EXPRESS WRITTENAPPROVALOF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I18
19
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FAN5240 Rev. 1.2.0
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